ti_gpio.c revision 1.3
1 /* $NetBSD: ti_gpio.c,v 1.3 2019/11/03 11:34:40 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.3 2019/11/03 11:34:40 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 #include <sys/bitops.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <dev/gpio/gpiovar.h> 44 45 #include <arm/ti/ti_prcm.h> 46 47 #define TI_GPIO_NPINS 32 48 49 enum ti_gpio_type { 50 TI_GPIO_OMAP3, 51 TI_GPIO_OMAP4, 52 TI_NGPIO 53 }; 54 55 enum { 56 GPIO_IRQSTATUS1, 57 GPIO_IRQENABLE1, /* OMAP3 */ 58 GPIO_IRQENABLE1_SET, /* OMAP4 */ 59 GPIO_IRQENABLE1_CLR, /* OMAP4 */ 60 GPIO_OE, 61 GPIO_DATAIN, 62 GPIO_DATAOUT, 63 GPIO_LEVELDETECT0, 64 GPIO_LEVELDETECT1, 65 GPIO_RISINGDETECT, 66 GPIO_FALLINGDETECT, 67 GPIO_CLEARDATAOUT, 68 GPIO_SETDATAOUT, 69 GPIO_NREG 70 }; 71 72 static const u_int ti_gpio_regmap[TI_NGPIO][GPIO_NREG] = { 73 [TI_GPIO_OMAP3] = { 74 [GPIO_IRQSTATUS1] = 0x18, 75 [GPIO_IRQENABLE1] = 0x1c, 76 [GPIO_OE] = 0x34, 77 [GPIO_DATAIN] = 0x38, 78 [GPIO_DATAOUT] = 0x3c, 79 [GPIO_LEVELDETECT0] = 0x40, 80 [GPIO_LEVELDETECT1] = 0x44, 81 [GPIO_RISINGDETECT] = 0x48, 82 [GPIO_FALLINGDETECT] = 0x4c, 83 [GPIO_CLEARDATAOUT] = 0x90, 84 [GPIO_SETDATAOUT] = 0x94, 85 }, 86 [TI_GPIO_OMAP4] = { 87 [GPIO_IRQSTATUS1] = 0x2c, 88 [GPIO_IRQENABLE1_SET] = 0x34, 89 [GPIO_IRQENABLE1_CLR] = 0x38, 90 [GPIO_OE] = 0x134, 91 [GPIO_DATAIN] = 0x138, 92 [GPIO_DATAOUT] = 0x13c, 93 [GPIO_LEVELDETECT0] = 0x140, 94 [GPIO_LEVELDETECT1] = 0x144, 95 [GPIO_RISINGDETECT] = 0x148, 96 [GPIO_FALLINGDETECT] = 0x14c, 97 [GPIO_CLEARDATAOUT] = 0x190, 98 [GPIO_SETDATAOUT] = 0x194, 99 }, 100 }; 101 102 static const struct of_compat_data compat_data[] = { 103 { "ti,omap3-gpio", TI_GPIO_OMAP3 }, 104 { "ti,omap4-gpio", TI_GPIO_OMAP4 }, 105 { NULL } 106 }; 107 108 struct ti_gpio_intr { 109 u_int intr_pin; 110 int (*intr_func)(void *); 111 void *intr_arg; 112 bool intr_mpsafe; 113 }; 114 115 struct ti_gpio_softc { 116 device_t sc_dev; 117 bus_space_tag_t sc_bst; 118 bus_space_handle_t sc_bsh; 119 kmutex_t sc_lock; 120 enum ti_gpio_type sc_type; 121 const char *sc_modname; 122 void *sc_ih; 123 124 struct gpio_chipset_tag sc_gp; 125 gpio_pin_t sc_pins[TI_GPIO_NPINS]; 126 bool sc_pinout[TI_GPIO_NPINS]; 127 struct ti_gpio_intr sc_intr[TI_GPIO_NPINS]; 128 device_t sc_gpiodev; 129 }; 130 131 struct ti_gpio_pin { 132 struct ti_gpio_softc *pin_sc; 133 u_int pin_nr; 134 int pin_flags; 135 bool pin_actlo; 136 }; 137 138 #define RD4(sc, reg) \ 139 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)]) 140 #define WR4(sc, reg, val) \ 141 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val)) 142 143 static int ti_gpio_match(device_t, cfdata_t, void *); 144 static void ti_gpio_attach(device_t, device_t, void *); 145 146 CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc), 147 ti_gpio_match, ti_gpio_attach, NULL, NULL); 148 149 static int 150 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags) 151 { 152 uint32_t oe; 153 154 KASSERT(mutex_owned(&sc->sc_lock)); 155 156 oe = RD4(sc, GPIO_OE); 157 if (flags & GPIO_PIN_INPUT) 158 oe |= __BIT(pin); 159 else if (flags & GPIO_PIN_OUTPUT) 160 oe &= ~__BIT(pin); 161 WR4(sc, GPIO_OE, oe); 162 163 sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0; 164 165 return 0; 166 } 167 168 static void * 169 ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 170 { 171 struct ti_gpio_softc * const sc = device_private(dev); 172 struct ti_gpio_pin *gpin; 173 const u_int *gpio = data; 174 int error; 175 176 if (len != 12) 177 return NULL; 178 179 const uint8_t pin = be32toh(gpio[1]) & 0xff; 180 const bool actlo = be32toh(gpio[2]) & 1; 181 182 if (pin >= __arraycount(sc->sc_pins)) 183 return NULL; 184 185 mutex_enter(&sc->sc_lock); 186 error = ti_gpio_ctl(sc, pin, flags); 187 mutex_exit(&sc->sc_lock); 188 189 if (error != 0) 190 return NULL; 191 192 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 193 gpin->pin_sc = sc; 194 gpin->pin_nr = pin; 195 gpin->pin_flags = flags; 196 gpin->pin_actlo = actlo; 197 198 return gpin; 199 } 200 201 static void 202 ti_gpio_release(device_t dev, void *priv) 203 { 204 struct ti_gpio_softc * const sc = device_private(dev); 205 struct ti_gpio_pin *pin = priv; 206 207 mutex_enter(&sc->sc_lock); 208 ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT); 209 mutex_exit(&sc->sc_lock); 210 211 kmem_free(pin, sizeof(*pin)); 212 } 213 214 static int 215 ti_gpio_read(device_t dev, void *priv, bool raw) 216 { 217 struct ti_gpio_softc * const sc = device_private(dev); 218 struct ti_gpio_pin *pin = priv; 219 uint32_t data; 220 int val; 221 222 KASSERT(sc == pin->pin_sc); 223 224 const uint32_t data_mask = __BIT(pin->pin_nr); 225 226 /* No lock required for reads */ 227 if (sc->sc_pinout[pin->pin_nr]) 228 data = RD4(sc, GPIO_DATAOUT); 229 else 230 data = RD4(sc, GPIO_DATAIN); 231 val = __SHIFTOUT(data, data_mask); 232 if (!raw && pin->pin_actlo) 233 val = !val; 234 235 return val; 236 } 237 238 static void 239 ti_gpio_write(device_t dev, void *priv, int val, bool raw) 240 { 241 struct ti_gpio_softc * const sc = device_private(dev); 242 struct ti_gpio_pin *pin = priv; 243 244 KASSERT(sc == pin->pin_sc); 245 246 const uint32_t data_mask = __BIT(pin->pin_nr); 247 248 if (!raw && pin->pin_actlo) 249 val = !val; 250 251 const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT; 252 253 WR4(sc, data_reg, data_mask); 254 } 255 256 static struct fdtbus_gpio_controller_func ti_gpio_funcs = { 257 .acquire = ti_gpio_acquire, 258 .release = ti_gpio_release, 259 .read = ti_gpio_read, 260 .write = ti_gpio_write, 261 }; 262 263 static void 264 ti_gpio_intr_disestablish(device_t dev, void *ih) 265 { 266 struct ti_gpio_softc * const sc = device_private(dev); 267 struct ti_gpio_intr *intr = ih; 268 const u_int pin = intr->intr_pin; 269 const uint32_t pin_mask = __BIT(pin); 270 uint32_t val; 271 272 /* Disable interrupts */ 273 if (sc->sc_type == TI_GPIO_OMAP3) { 274 val = RD4(sc, GPIO_IRQENABLE1); 275 WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask); 276 } else { 277 WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask); 278 } 279 280 intr->intr_func = NULL; 281 intr->intr_arg = NULL; 282 } 283 284 static void * 285 ti_gpio_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 286 int (*func)(void *), void *arg) 287 { 288 struct ti_gpio_softc * const sc = device_private(dev); 289 uint32_t val; 290 291 /* 1st cell is the pin */ 292 /* 2nd cell is flags */ 293 const u_int pin = be32toh(specifier[0]); 294 const u_int type = be32toh(specifier[2]) & 0xf; 295 296 if (ipl != IPL_VM || pin >= __arraycount(sc->sc_pins)) 297 return NULL; 298 299 /* 300 * Enabling both high and low level triggers will cause the GPIO 301 * controller to always assert the interrupt. 302 */ 303 if ((type & (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) == 304 (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) 305 return NULL; 306 307 if (sc->sc_intr[pin].intr_func != NULL) 308 return NULL; 309 310 /* Set pin as input */ 311 if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0) 312 return NULL; 313 314 sc->sc_intr[pin].intr_pin = pin; 315 sc->sc_intr[pin].intr_func = func; 316 sc->sc_intr[pin].intr_arg = arg; 317 sc->sc_intr[pin].intr_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 318 319 const uint32_t pin_mask = __BIT(pin); 320 321 /* Configure triggers */ 322 val = RD4(sc, GPIO_LEVELDETECT0); 323 if ((type & FDT_INTR_TYPE_LOW_LEVEL) != 0) 324 val |= pin_mask; 325 else 326 val &= ~pin_mask; 327 WR4(sc, GPIO_LEVELDETECT0, val); 328 329 val = RD4(sc, GPIO_LEVELDETECT1); 330 if ((type & FDT_INTR_TYPE_HIGH_LEVEL) != 0) 331 val |= pin_mask; 332 else 333 val &= ~pin_mask; 334 WR4(sc, GPIO_LEVELDETECT1, val); 335 336 val = RD4(sc, GPIO_RISINGDETECT); 337 if ((type & FDT_INTR_TYPE_POS_EDGE) != 0) 338 val |= pin_mask; 339 else 340 val &= ~pin_mask; 341 WR4(sc, GPIO_RISINGDETECT, val); 342 343 val = RD4(sc, GPIO_FALLINGDETECT); 344 if ((type & FDT_INTR_TYPE_NEG_EDGE) != 0) 345 val |= pin_mask; 346 else 347 val &= ~pin_mask; 348 WR4(sc, GPIO_FALLINGDETECT, val); 349 350 /* Enable interrupts */ 351 if (sc->sc_type == TI_GPIO_OMAP3) { 352 val = RD4(sc, GPIO_IRQENABLE1); 353 WR4(sc, GPIO_IRQENABLE1, val | pin_mask); 354 } else { 355 WR4(sc, GPIO_IRQENABLE1_SET, pin_mask); 356 } 357 358 return &sc->sc_intr[pin]; 359 } 360 361 static bool 362 ti_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 363 { 364 struct ti_gpio_softc * const sc = device_private(dev); 365 366 /* 1st cell is the pin */ 367 /* 2nd cell is flags */ 368 const u_int pin = be32toh(specifier[0]); 369 370 if (pin >= __arraycount(sc->sc_pins)) 371 return false; 372 373 snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin); 374 return true; 375 } 376 377 static struct fdtbus_interrupt_controller_func ti_gpio_intrfuncs = { 378 .establish = ti_gpio_intr_establish, 379 .disestablish = ti_gpio_intr_disestablish, 380 .intrstr = ti_gpio_intrstr, 381 }; 382 383 static int 384 ti_gpio_pin_read(void *priv, int pin) 385 { 386 struct ti_gpio_softc * const sc = priv; 387 uint32_t data; 388 int val; 389 390 KASSERT(pin < __arraycount(sc->sc_pins)); 391 392 const uint32_t data_mask = __BIT(pin); 393 394 data = RD4(sc, GPIO_DATAIN); 395 val = __SHIFTOUT(data, data_mask); 396 397 return val; 398 } 399 400 static void 401 ti_gpio_pin_write(void *priv, int pin, int val) 402 { 403 struct ti_gpio_softc * const sc = priv; 404 405 KASSERT(pin < __arraycount(sc->sc_pins)); 406 407 const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT; 408 const uint32_t data_mask = __BIT(pin); 409 410 WR4(sc, data_reg, data_mask); 411 } 412 413 static void 414 ti_gpio_pin_ctl(void *priv, int pin, int flags) 415 { 416 struct ti_gpio_softc * const sc = priv; 417 418 KASSERT(pin < __arraycount(sc->sc_pins)); 419 420 mutex_enter(&sc->sc_lock); 421 ti_gpio_ctl(sc, pin, flags); 422 mutex_exit(&sc->sc_lock); 423 } 424 425 static void 426 ti_gpio_attach_ports(struct ti_gpio_softc *sc) 427 { 428 struct gpio_chipset_tag *gp = &sc->sc_gp; 429 struct gpiobus_attach_args gba; 430 u_int pin; 431 432 gp->gp_cookie = sc; 433 gp->gp_pin_read = ti_gpio_pin_read; 434 gp->gp_pin_write = ti_gpio_pin_write; 435 gp->gp_pin_ctl = ti_gpio_pin_ctl; 436 437 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) { 438 sc->sc_pins[pin].pin_num = pin; 439 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 440 sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin); 441 } 442 443 memset(&gba, 0, sizeof(gba)); 444 gba.gba_gc = gp; 445 gba.gba_pins = sc->sc_pins; 446 gba.gba_npins = __arraycount(sc->sc_pins); 447 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 448 } 449 450 static int 451 ti_gpio_intr(void *priv) 452 { 453 struct ti_gpio_softc * const sc = priv; 454 uint32_t status; 455 u_int bit; 456 int rv = 0; 457 458 status = RD4(sc, GPIO_IRQSTATUS1); 459 WR4(sc, GPIO_IRQSTATUS1, status); 460 461 while ((bit = ffs32(status)) != 0) { 462 const u_int pin = bit - 1; 463 const uint32_t pin_mask = __BIT(pin); 464 struct ti_gpio_intr *intr = &sc->sc_intr[pin]; 465 status &= ~pin_mask; 466 if (intr->intr_func == NULL) 467 continue; 468 if (!intr->intr_mpsafe) 469 KERNEL_LOCK(1, curlwp); 470 rv |= intr->intr_func(intr->intr_arg); 471 if (!intr->intr_mpsafe) 472 KERNEL_UNLOCK_ONE(curlwp); 473 } 474 475 return rv; 476 } 477 478 static int 479 ti_gpio_match(device_t parent, cfdata_t cf, void *aux) 480 { 481 struct fdt_attach_args * const faa = aux; 482 483 return of_match_compat_data(faa->faa_phandle, compat_data); 484 } 485 486 static void 487 ti_gpio_attach(device_t parent, device_t self, void *aux) 488 { 489 struct ti_gpio_softc * const sc = device_private(self); 490 struct fdt_attach_args * const faa = aux; 491 const int phandle = faa->faa_phandle; 492 char intrstr[128]; 493 bus_addr_t addr; 494 bus_size_t size; 495 496 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 497 aprint_error(": couldn't get registers\n"); 498 return; 499 } 500 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 501 aprint_error(": couldn't decode interrupt\n"); 502 return; 503 } 504 if (ti_prcm_enable_hwmod(phandle, 0) != 0) { 505 aprint_error(": couldn't enable module\n"); 506 return; 507 } 508 509 sc->sc_dev = self; 510 sc->sc_bst = faa->faa_bst; 511 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 512 aprint_error(": couldn't map registers\n"); 513 return; 514 } 515 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 516 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 517 518 sc->sc_modname = fdtbus_get_string(phandle, "ti,hwmods"); 519 if (sc->sc_modname == NULL) 520 sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods"); 521 522 aprint_naive("\n"); 523 aprint_normal(": GPIO (%s)\n", sc->sc_modname); 524 525 fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs); 526 527 ti_gpio_attach_ports(sc); 528 529 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 530 ti_gpio_intr, sc); 531 if (sc->sc_ih == NULL) { 532 aprint_error_dev(self, "failed to establish interrupt on %s\n", 533 intrstr); 534 return; 535 } 536 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 537 fdtbus_register_interrupt_controller(self, phandle, &ti_gpio_intrfuncs); 538 } 539
Indexes created Tue Sep 30 11:09:46 GMT 2025