ti_iic.c revision 1.1
1 /* $NetBSD: ti_iic.c,v 1.1 2019/10/27 19:11:07 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2012 Jared D. McNeill <jmcneill (at) invisible.ca> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.1 2019/10/27 19:11:07 jmcneill Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/conf.h> 59 #include <sys/bus.h> 60 #include <sys/proc.h> 61 #include <sys/kernel.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 65 #include <dev/i2c/i2cvar.h> 66 67 #include <dev/fdt/fdtvar.h> 68 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_iicreg.h> 71 72 #ifndef OMAP2_I2C_SLAVE_ADDR 73 #define OMAP2_I2C_SLAVE_ADDR 0x01 74 #endif 75 76 #define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd)) 77 78 #ifdef I2CDEBUG 79 #define DPRINTF(args) printf args 80 #else 81 #define DPRINTF(args) 82 #endif 83 84 static const char * compatible [] = { 85 "ti,omap4-i2c", 86 NULL 87 }; 88 89 /* operation in progress */ 90 typedef enum { 91 TI_I2CREAD, 92 TI_I2CWRITE, 93 TI_I2CDONE, 94 TI_I2CERROR 95 } ti_i2cop_t; 96 97 struct ti_iic_softc { 98 device_t sc_dev; 99 struct i2c_controller sc_ic; 100 kmutex_t sc_lock; 101 device_t sc_i2cdev; 102 103 bus_space_tag_t sc_iot; 104 bus_space_handle_t sc_ioh; 105 106 void *sc_ih; 107 kmutex_t sc_mtx; 108 kcondvar_t sc_cv; 109 ti_i2cop_t sc_op; 110 int sc_buflen; 111 int sc_bufidx; 112 char *sc_buf; 113 114 bool sc_busy; 115 116 int sc_rxthres; 117 int sc_txthres; 118 }; 119 120 #define I2C_READ_REG(sc, reg) \ 121 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg)) 122 #define I2C_READ_DATA(sc) \ 123 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA); 124 #define I2C_WRITE_REG(sc, reg, val) \ 125 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 126 #define I2C_WRITE_DATA(sc, val) \ 127 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA, (val)) 128 129 static int ti_iic_match(device_t, cfdata_t, void *); 130 static void ti_iic_attach(device_t, device_t, void *); 131 132 static int ti_iic_intr(void *); 133 134 static int ti_iic_acquire_bus(void *, int); 135 static void ti_iic_release_bus(void *, int); 136 static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, 137 size_t, void *, size_t, int); 138 139 static int ti_iic_reset(struct ti_iic_softc *); 140 static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, 141 uint8_t *, size_t, int); 142 static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t); 143 static void ti_iic_do_read(struct ti_iic_softc *, uint32_t); 144 static void ti_iic_do_write(struct ti_iic_softc *, uint32_t); 145 146 static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int); 147 static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t); 148 static int ti_iic_flush(struct ti_iic_softc *); 149 150 static i2c_tag_t ti_iic_get_tag(device_t); 151 152 static const struct fdtbus_i2c_controller_func ti_iic_funcs = { 153 .get_tag = ti_iic_get_tag, 154 }; 155 156 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc), 157 ti_iic_match, ti_iic_attach, NULL, NULL); 158 159 static int 160 ti_iic_match(device_t parent, cfdata_t match, void *opaque) 161 { 162 struct fdt_attach_args * const faa = opaque; 163 164 return of_match_compatible(faa->faa_phandle, compatible); 165 } 166 167 static void 168 ti_iic_attach(device_t parent, device_t self, void *opaque) 169 { 170 struct ti_iic_softc *sc = device_private(self); 171 struct fdt_attach_args * const faa = opaque; 172 const int phandle = faa->faa_phandle; 173 int scheme, major, minor, fifodepth, fifo; 174 char intrstr[128]; 175 bus_addr_t addr; 176 bus_size_t size; 177 uint16_t rev; 178 179 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 180 aprint_error(": couldn't get registers\n"); 181 return; 182 } 183 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 184 aprint_error(": couldn't decode interrupt\n"); 185 return; 186 } 187 188 if (ti_prcm_enable_hwmod(OF_parent(phandle), 0) != 0) { 189 aprint_error(": couldn't enable module\n"); 190 return; 191 } 192 193 sc->sc_dev = self; 194 sc->sc_iot = faa->faa_bst; 195 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 196 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 197 cv_init(&sc->sc_cv, "tiiic"); 198 sc->sc_ic.ic_cookie = sc; 199 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus; 200 sc->sc_ic.ic_release_bus = ti_iic_release_bus; 201 sc->sc_ic.ic_exec = ti_iic_exec; 202 203 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 204 aprint_error(": couldn't map registers\n"); 205 return; 206 } 207 208 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0, 209 ti_iic_intr, sc); 210 if (sc->sc_ih == NULL) { 211 aprint_error(": couldn't establish interrupt\n"); 212 return; 213 } 214 215 scheme = I2C_REVNB_HI_SCHEME(I2C_READ_REG(sc, OMAP2_I2C_REVNB_HI)); 216 rev = I2C_READ_REG(sc, OMAP2_I2C_REVNB_LO); 217 if (scheme == 0) { 218 major = I2C_REV_SCHEME_0_MAJOR(rev); 219 minor = I2C_REV_SCHEME_0_MINOR(rev); 220 } else { 221 major = I2C_REVNB_LO_MAJOR(rev); 222 minor = I2C_REVNB_LO_MINOR(rev); 223 } 224 aprint_normal(": rev %d.%d, scheme %d\n", major, minor, scheme); 225 aprint_naive("\n"); 226 227 fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT)); 228 fifo = OMAP2_I2C_FIFOBYTES(fifodepth); 229 aprint_normal_dev(self, "%d-bytes FIFO\n", fifo); 230 sc->sc_rxthres = sc->sc_txthres = fifo >> 1; 231 232 ti_iic_reset(sc); 233 ti_iic_flush(sc); 234 235 fdtbus_register_i2c_controller(self, phandle, &ti_iic_funcs); 236 237 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 238 } 239 240 static int 241 ti_iic_intr(void *arg) 242 { 243 struct ti_iic_softc *sc = arg; 244 uint32_t stat; 245 246 mutex_enter(&sc->sc_mtx); 247 DPRINTF(("ti_iic_intr\n")); 248 stat = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS); 249 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op)); 250 ti_iic_handle_intr(sc, stat); 251 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat); 252 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) { 253 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op)); 254 cv_broadcast(&sc->sc_cv); 255 } 256 mutex_exit(&sc->sc_mtx); 257 DPRINTF(("ti_iic_intr status 0x%x\n", stat)); 258 return 1; 259 } 260 261 static int 262 ti_iic_acquire_bus(void *opaque, int flags) 263 { 264 struct ti_iic_softc *sc = opaque; 265 266 mutex_enter(&sc->sc_lock); 267 while (sc->sc_busy) 268 cv_wait(&sc->sc_cv, &sc->sc_lock); 269 sc->sc_busy = true; 270 mutex_exit(&sc->sc_lock); 271 272 return 0; 273 } 274 275 static void 276 ti_iic_release_bus(void *opaque, int flags) 277 { 278 struct ti_iic_softc *sc = opaque; 279 280 mutex_enter(&sc->sc_lock); 281 sc->sc_busy = false; 282 cv_broadcast(&sc->sc_cv); 283 mutex_exit(&sc->sc_lock); 284 } 285 286 static int 287 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr, 288 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 289 { 290 struct ti_iic_softc *sc = opaque; 291 int err; 292 293 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n", 294 op, cmdlen, len, flags)); 295 296 if (cmdlen > 0) { 297 err = ti_iic_op(sc, addr, TI_I2CWRITE, 298 __UNCONST(cmdbuf), cmdlen, 299 (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags); 300 if (err) 301 goto done; 302 } 303 304 if (I2C_OP_STOP_P(op)) 305 flags |= I2C_F_STOP; 306 307 /* 308 * I2C controller doesn't allow for zero-byte transfers. 309 */ 310 if (len == 0) { 311 err = EINVAL; 312 goto done; 313 } 314 315 if (I2C_OP_READ_P(op)) { 316 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags); 317 } else { 318 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags); 319 } 320 321 done: 322 if (err) 323 ti_iic_reset(sc); 324 325 ti_iic_flush(sc); 326 327 DPRINTF(("ti_iic_exec: done %d\n", err)); 328 return err; 329 } 330 331 static int 332 ti_iic_reset(struct ti_iic_softc *sc) 333 { 334 uint32_t psc, scll, sclh; 335 int i; 336 337 DPRINTF(("ti_iic_reset\n")); 338 339 /* Disable */ 340 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 341 /* Soft reset */ 342 I2C_WRITE_REG(sc, OMAP2_I2C_SYSC, I2C_SYSC_SRST); 343 delay(1000); 344 /* enable so that we can check for reset complete */ 345 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN); 346 delay(1000); 347 for (i = 0; i < 1000; i++) { /* 1s delay for reset */ 348 if (I2C_READ_REG(sc, OMAP2_I2C_SYSS) & I2C_SYSS_RDONE) 349 break; 350 } 351 /* Disable again */ 352 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 353 delay(50000); 354 355 if (i >= 1000) { 356 aprint_error_dev(sc->sc_dev, ": couldn't reset module\n"); 357 return 1; 358 } 359 360 361 /* XXX standard speed only */ 362 psc = 3; 363 scll = 53; 364 sclh = 55; 365 366 /* Clocks */ 367 I2C_WRITE_REG(sc, OMAP2_I2C_PSC, psc); 368 I2C_WRITE_REG(sc, OMAP2_I2C_SCLL, scll); 369 I2C_WRITE_REG(sc, OMAP2_I2C_SCLH, sclh); 370 371 /* Own I2C address */ 372 I2C_WRITE_REG(sc, OMAP2_I2C_OA, OMAP2_I2C_SLAVE_ADDR); 373 374 /* 5 bytes fifo */ 375 I2C_WRITE_REG(sc, OMAP2_I2C_BUF, 376 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres)); 377 378 /* Enable */ 379 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN); 380 381 return 0; 382 } 383 384 static int 385 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op, 386 uint8_t *buf, size_t buflen, int flags) 387 { 388 uint16_t con, stat, mask; 389 int err, retry; 390 391 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE); 392 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n", 393 addr, op, buf, (unsigned int) buflen, flags)); 394 395 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL; 396 if (op == TI_I2CREAD) { 397 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY; 398 } else { 399 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY; 400 } 401 402 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags); 403 if (err) { 404 DPRINTF(("ti_iic_op: wait error %d\n", err)); 405 return err; 406 } 407 408 con = I2C_CON_EN; 409 con |= I2C_CON_MST; 410 con |= I2C_CON_STT;; 411 if (flags & I2C_F_STOP) 412 con |= I2C_CON_STP; 413 if (addr & ~0x7f) 414 con |= I2C_CON_XSA; 415 if (op == TI_I2CWRITE) 416 con |= I2C_CON_TRX; 417 418 mutex_enter(&sc->sc_mtx); 419 sc->sc_op = op; 420 sc->sc_buf = buf; 421 sc->sc_buflen = buflen; 422 sc->sc_bufidx = 0; 423 424 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP); 425 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con)); 426 I2C_WRITE_REG(sc, OMAP2_I2C_CNT, buflen); 427 I2C_WRITE_REG(sc, OMAP2_I2C_SA, (addr & I2C_SA_MASK)); 428 DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, OMAP2_I2C_SA), I2C_READ_REG(sc, OMAP2_I2C_CNT))); 429 430 if ((flags & I2C_F_POLL) == 0) { 431 /* clear any pending interrupt */ 432 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, 433 I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS)); 434 /* and enable */ 435 I2C_WRITE_REG(sc, OMAP2_I2C_IRQENABLE_SET, mask); 436 } 437 /* start transfer */ 438 I2C_WRITE_REG(sc, OMAP2_I2C_CON, con); 439 440 if ((flags & I2C_F_POLL) == 0) { 441 /* and wait for completion */ 442 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op)); 443 while (sc->sc_op == op) { 444 if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx, 445 mstohz(5000)) == EWOULDBLOCK) { 446 /* timeout */ 447 op = TI_I2CERROR; 448 } 449 } 450 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op)); 451 452 /* disable interrupts */ 453 I2C_WRITE_REG(sc, OMAP2_I2C_IRQENABLE_CLR, 0xffff); 454 } else { 455 /* poll for completion */ 456 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op)); 457 while (sc->sc_op == op) { 458 stat = ti_iic_stat(sc, mask); 459 DPRINTF(("ti_iic_op stat 0x%x\n", stat)); 460 if (stat == 0) { 461 /* timeout */ 462 sc->sc_op = TI_I2CERROR; 463 } else { 464 ti_iic_handle_intr(sc, stat); 465 } 466 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat); 467 } 468 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op)); 469 } 470 mutex_exit(&sc->sc_mtx); 471 retry = 10000; 472 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 473 while (I2C_READ_REG(sc, OMAP2_I2C_CON) & I2C_CON_MST) { 474 delay(100); 475 if (--retry == 0) 476 break; 477 } 478 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO; 479 } 480 481 static void 482 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat) 483 { 484 KASSERT(mutex_owned(&sc->sc_mtx)); 485 KASSERT(stat != 0); 486 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat)); 487 488 if (stat & 489 (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) { 490 sc->sc_op = TI_I2CERROR; 491 return; 492 } 493 if (stat & I2C_IRQSTATUS_ARDY) { 494 sc->sc_op = TI_I2CDONE; 495 return; 496 } 497 if (sc->sc_op == TI_I2CREAD) 498 ti_iic_do_read(sc, stat); 499 else if (sc->sc_op == TI_I2CWRITE) 500 ti_iic_do_write(sc, stat); 501 else 502 return; 503 } 504 void 505 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat) 506 { 507 int len = 0; 508 509 KASSERT(mutex_owned(&sc->sc_mtx)); 510 DPRINTF(("ti_iic_do_read stat %#x\n", stat)); 511 if (stat & I2C_IRQSTATUS_RDR) { 512 len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT); 513 len = I2C_BUFSTAT_RXSTAT(len); 514 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n", 515 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 516 } else if (stat & I2C_IRQSTATUS_RRDY) { 517 len = sc->sc_rxthres + 1; 518 DPRINTF(("ti_iic_do_read receive len %d left %d\n", 519 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 520 } 521 for (; 522 sc->sc_bufidx < sc->sc_buflen && len > 0; 523 sc->sc_bufidx++, len--) { 524 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc); 525 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx, 526 sc->sc_buf[sc->sc_bufidx])); 527 } 528 DPRINTF(("ti_iic_do_read done\n")); 529 } 530 531 void 532 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat) 533 { 534 int len = 0; 535 536 DPRINTF(("ti_iic_do_write stat %#x\n", stat)); 537 KASSERT(mutex_owned(&sc->sc_mtx)); 538 if (stat & I2C_IRQSTATUS_XDR) { 539 len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT); 540 len = I2C_BUFSTAT_TXSTAT(len); 541 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n", 542 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 543 } else if (stat & I2C_IRQSTATUS_XRDY) { 544 len = sc->sc_txthres + 1; 545 DPRINTF(("ti_iic_do_write xmit len %d left %d\n", 546 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 547 } 548 for (; 549 sc->sc_bufidx < sc->sc_buflen && len > 0; 550 sc->sc_bufidx++, len--) { 551 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n", 552 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx])); 553 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]); 554 } 555 DPRINTF(("ti_iic_do_write done\n")); 556 } 557 558 static int 559 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags) 560 { 561 int retry = 10; 562 uint16_t v; 563 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags)); 564 565 while (((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & mask) != val) { 566 --retry; 567 if (retry == 0) { 568 aprint_error_dev(sc->sc_dev, ": wait timeout, " 569 "mask = %#x val = %#x stat = %#x\n", 570 mask, val, v); 571 return EBUSY; 572 } 573 if (flags & I2C_F_POLL) { 574 delay(50000); 575 } else { 576 kpause("tiiic", false, mstohz(50), NULL); 577 } 578 } 579 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 580 581 return 0; 582 } 583 584 static uint32_t 585 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask) 586 { 587 uint32_t v; 588 int retry = 500; 589 DPRINTF(("ti_iic_wait mask %#x\n", mask)); 590 while (--retry > 0) { 591 v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW) & mask; 592 if (v != 0) 593 break; 594 delay(100); 595 } 596 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 597 return v; 598 } 599 600 static int 601 ti_iic_flush(struct ti_iic_softc *sc) 602 { 603 DPRINTF(("ti_iic_flush\n")); 604 #if 0 605 int retry = 1000; 606 uint16_t v; 607 608 while ((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) { 609 if (--retry == 0) { 610 aprint_error_dev(sc->sc_dev, 611 ": flush timeout, stat = %#x\n", v); 612 return EBUSY; 613 } 614 (void)I2C_READ_DATA(sc); 615 delay(1000); 616 } 617 #endif 618 619 I2C_WRITE_REG(sc, OMAP2_I2C_CNT, 0); 620 return 0; 621 } 622 623 static i2c_tag_t 624 ti_iic_get_tag(device_t dev) 625 { 626 struct ti_iic_softc * const sc = device_private(dev); 627 628 return &sc->sc_ic; 629 } 630
Indexes created Tue Sep 30 20:09:53 GMT 2025