ti_iic.c revision 1.15
1 /* $NetBSD: ti_iic.c,v 1.15 2025/09/16 11:55:17 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2012 Jared D. McNeill <jmcneill (at) invisible.ca> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.15 2025/09/16 11:55:17 thorpej Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/conf.h> 59 #include <sys/bus.h> 60 #include <sys/proc.h> 61 #include <sys/kernel.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 65 #include <dev/i2c/i2cvar.h> 66 67 #include <dev/fdt/fdtvar.h> 68 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_iicreg.h> 71 72 #ifndef OMAP2_I2C_SLAVE_ADDR 73 #define OMAP2_I2C_SLAVE_ADDR 0x01 74 #endif 75 76 #define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd)) 77 78 #ifdef I2CDEBUG 79 #define DPRINTF(args) printf args 80 #else 81 #define DPRINTF(args) 82 #endif 83 84 enum ti_iic_type { 85 TI_IIC_OMAP3, 86 TI_IIC_OMAP4, 87 TI_NTYPES 88 }; 89 90 enum { 91 I2C_SYSC, 92 I2C_IRQSTATUS_RAW, 93 I2C_IRQSTATUS, 94 I2C_IRQENABLE, /* OMAP3 */ 95 I2C_IRQENABLE_SET, /* OMAP4 */ 96 I2C_IRQENABLE_CLR, /* OMAP4 */ 97 I2C_SYSS, 98 I2C_BUF, 99 I2C_CNT, 100 I2C_DATA, 101 I2C_CON, 102 I2C_OA, 103 I2C_SA, 104 I2C_PSC, 105 I2C_SCLL, 106 I2C_SCLH, 107 I2C_BUFSTAT, 108 TI_NREGS 109 }; 110 111 static const u_int ti_iic_regmap[TI_NTYPES][TI_NREGS] = { 112 [TI_IIC_OMAP3] = { 113 [I2C_SYSC] = 0x20, 114 [I2C_IRQSTATUS_RAW] = 0x08, 115 [I2C_IRQSTATUS] = 0x08, 116 [I2C_IRQENABLE] = 0x04, 117 [I2C_SYSS] = 0x10, 118 [I2C_BUF] = 0x14, 119 [I2C_CNT] = 0x18, 120 [I2C_DATA] = 0x1c, 121 [I2C_CON] = 0x24, 122 [I2C_OA] = 0x28, 123 [I2C_SA] = 0x2c, 124 [I2C_PSC] = 0x30, 125 [I2C_SCLL] = 0x34, 126 [I2C_SCLH] = 0x38, 127 [I2C_BUFSTAT] = 0x40, 128 }, 129 [TI_IIC_OMAP4] = { 130 [I2C_SYSC] = 0x10, 131 [I2C_IRQSTATUS_RAW] = 0x24, 132 [I2C_IRQSTATUS] = 0x28, 133 [I2C_IRQENABLE_SET] = 0x2c, 134 [I2C_IRQENABLE_CLR] = 0x30, 135 [I2C_SYSS] = 0x90, 136 [I2C_BUF] = 0x94, 137 [I2C_CNT] = 0x98, 138 [I2C_DATA] = 0x9c, 139 [I2C_CON] = 0xa4, 140 [I2C_OA] = 0xa8, 141 [I2C_SA] = 0xac, 142 [I2C_PSC] = 0xb0, 143 [I2C_SCLL] = 0xb4, 144 [I2C_SCLH] = 0xb8, 145 [I2C_BUFSTAT] = 0xc0, 146 }, 147 }; 148 149 static const struct device_compatible_entry compat_data[] = { 150 /* compatible type */ 151 { .compat = "ti,omap3-i2c", .value = TI_IIC_OMAP3 }, 152 { .compat = "ti,omap4-i2c", .value = TI_IIC_OMAP4 }, 153 DEVICE_COMPAT_EOL 154 }; 155 156 /* operation in progress */ 157 typedef enum { 158 TI_I2CREAD, 159 TI_I2CWRITE, 160 TI_I2CDONE, 161 TI_I2CERROR 162 } ti_i2cop_t; 163 164 struct ti_iic_softc { 165 device_t sc_dev; 166 struct i2c_controller sc_ic; 167 kmutex_t sc_lock; 168 device_t sc_i2cdev; 169 170 bus_space_tag_t sc_iot; 171 bus_space_handle_t sc_ioh; 172 173 enum ti_iic_type sc_type; 174 175 void *sc_ih; 176 kmutex_t sc_mtx; 177 kcondvar_t sc_cv; 178 ti_i2cop_t sc_op; 179 int sc_opflags; 180 int sc_buflen; 181 int sc_bufidx; 182 char *sc_buf; 183 184 bool sc_busy; 185 186 int sc_rxthres; 187 int sc_txthres; 188 }; 189 190 #define I2C_READ_REG(sc, reg) \ 191 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)]) 192 #define I2C_READ_DATA(sc) \ 193 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA]) 194 #define I2C_WRITE_REG(sc, reg, val) \ 195 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)], (val)) 196 #define I2C_WRITE_DATA(sc, val) \ 197 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA], (val)) 198 199 static int ti_iic_match(device_t, cfdata_t, void *); 200 static void ti_iic_attach(device_t, device_t, void *); 201 202 static int ti_iic_intr(void *); 203 204 static int ti_iic_acquire_bus(void *, int); 205 static void ti_iic_release_bus(void *, int); 206 static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, 207 size_t, void *, size_t, int); 208 209 static int ti_iic_reset(struct ti_iic_softc *); 210 static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, 211 uint8_t *, size_t, int); 212 static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t); 213 static void ti_iic_do_read(struct ti_iic_softc *, uint32_t); 214 static void ti_iic_do_write(struct ti_iic_softc *, uint32_t); 215 216 static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int); 217 static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t); 218 static int ti_iic_flush(struct ti_iic_softc *); 219 220 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc), 221 ti_iic_match, ti_iic_attach, NULL, NULL); 222 223 static int 224 ti_iic_match(device_t parent, cfdata_t match, void *opaque) 225 { 226 struct fdt_attach_args * const faa = opaque; 227 228 return of_compatible_match(faa->faa_phandle, compat_data); 229 } 230 231 static void 232 ti_iic_attach(device_t parent, device_t self, void *opaque) 233 { 234 struct ti_iic_softc *sc = device_private(self); 235 struct fdt_attach_args * const faa = opaque; 236 const int phandle = faa->faa_phandle; 237 int fifodepth, fifo; 238 const char *modname; 239 char intrstr[128]; 240 bus_addr_t addr; 241 bus_size_t size; 242 243 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 244 aprint_error(": couldn't get registers\n"); 245 return; 246 } 247 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 248 aprint_error(": couldn't decode interrupt\n"); 249 return; 250 } 251 252 if (ti_prcm_enable_hwmod(phandle, 0) != 0) { 253 aprint_error(": couldn't enable module\n"); 254 return; 255 } 256 257 sc->sc_dev = self; 258 sc->sc_iot = faa->faa_bst; 259 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 260 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 261 cv_init(&sc->sc_cv, "tiiic"); 262 iic_tag_init(&sc->sc_ic); 263 sc->sc_ic.ic_cookie = sc; 264 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus; 265 sc->sc_ic.ic_release_bus = ti_iic_release_bus; 266 sc->sc_ic.ic_exec = ti_iic_exec; 267 268 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 269 aprint_error(": couldn't map registers\n"); 270 return; 271 } 272 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 273 274 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 0, 275 ti_iic_intr, sc, device_xname(self)); 276 if (sc->sc_ih == NULL) { 277 aprint_error(": couldn't establish interrupt\n"); 278 return; 279 } 280 281 modname = fdtbus_get_string(phandle, "ti,hwmods"); 282 if (modname == NULL) 283 modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods"); 284 285 fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, I2C_BUFSTAT)); 286 fifo = OMAP2_I2C_FIFOBYTES(fifodepth); 287 sc->sc_rxthres = sc->sc_txthres = fifo >> 1; 288 289 aprint_naive("\n"); 290 if (modname != NULL) 291 aprint_normal(": I2C controller (%s), %d-bytes FIFO\n", modname, fifo); 292 else 293 aprint_normal(": I2C controller (i2c@%" PRIxBUSADDR "), %d-bytes FIFO\n", 294 addr, fifo); 295 296 ti_iic_reset(sc); 297 ti_iic_flush(sc); 298 299 iicbus_attach(self, &sc->sc_ic); 300 } 301 302 static int 303 ti_iic_intr(void *arg) 304 { 305 struct ti_iic_softc *sc = arg; 306 uint32_t stat; 307 308 mutex_enter(&sc->sc_mtx); 309 DPRINTF(("ti_iic_intr opflags=%#x\n", sc->sc_opflags)); 310 if ((sc->sc_opflags & I2C_F_POLL) == 0) { 311 stat = I2C_READ_REG(sc, I2C_IRQSTATUS); 312 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op)); 313 ti_iic_handle_intr(sc, stat); 314 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat); 315 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) { 316 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op)); 317 cv_broadcast(&sc->sc_cv); 318 } 319 } 320 mutex_exit(&sc->sc_mtx); 321 DPRINTF(("ti_iic_intr status 0x%x\n", stat)); 322 return 1; 323 } 324 325 static int 326 ti_iic_acquire_bus(void *opaque, int flags) 327 { 328 struct ti_iic_softc *sc = opaque; 329 330 mutex_enter(&sc->sc_lock); 331 while (sc->sc_busy) 332 cv_wait(&sc->sc_cv, &sc->sc_lock); 333 sc->sc_busy = true; 334 mutex_exit(&sc->sc_lock); 335 336 return 0; 337 } 338 339 static void 340 ti_iic_release_bus(void *opaque, int flags) 341 { 342 struct ti_iic_softc *sc = opaque; 343 344 mutex_enter(&sc->sc_lock); 345 sc->sc_busy = false; 346 cv_broadcast(&sc->sc_cv); 347 mutex_exit(&sc->sc_lock); 348 } 349 350 static int 351 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr, 352 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 353 { 354 struct ti_iic_softc *sc = opaque; 355 int err; 356 357 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n", 358 op, cmdlen, len, flags)); 359 360 if (cmdlen > 0) { 361 err = ti_iic_op(sc, addr, TI_I2CWRITE, 362 __UNCONST(cmdbuf), cmdlen, 363 (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags); 364 if (err) 365 goto done; 366 } 367 368 if (I2C_OP_STOP_P(op)) 369 flags |= I2C_F_STOP; 370 371 /* 372 * I2C controller doesn't allow for zero-byte transfers. 373 */ 374 if (len == 0) { 375 err = EINVAL; 376 goto done; 377 } 378 379 if (I2C_OP_READ_P(op)) { 380 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags); 381 } else { 382 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags); 383 } 384 385 done: 386 if (err) 387 ti_iic_reset(sc); 388 389 ti_iic_flush(sc); 390 391 DPRINTF(("ti_iic_exec: done %d\n", err)); 392 return err; 393 } 394 395 static int 396 ti_iic_reset(struct ti_iic_softc *sc) 397 { 398 uint32_t psc, scll, sclh; 399 int i; 400 401 DPRINTF(("ti_iic_reset\n")); 402 403 /* Disable */ 404 I2C_WRITE_REG(sc, I2C_CON, 0); 405 /* Soft reset */ 406 I2C_WRITE_REG(sc, I2C_SYSC, I2C_SYSC_SRST); 407 delay(1000); 408 /* enable so that we can check for reset complete */ 409 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN); 410 delay(1000); 411 for (i = 0; i < 1000; i++) { /* 1s delay for reset */ 412 if (I2C_READ_REG(sc, I2C_SYSS) & I2C_SYSS_RDONE) 413 break; 414 } 415 /* Disable again */ 416 I2C_WRITE_REG(sc, I2C_CON, 0); 417 delay(50000); 418 419 if (i >= 1000) { 420 aprint_error_dev(sc->sc_dev, ": couldn't reset module\n"); 421 return 1; 422 } 423 424 425 /* XXX standard speed only */ 426 if (sc->sc_type == TI_IIC_OMAP3) { 427 psc = (96000000 / 19200000) - 1; 428 scll = sclh = (19200000 / (2 * 100000)) - 6; 429 } else { 430 psc = 3; 431 scll = 53; 432 sclh = 55; 433 } 434 435 /* Clocks */ 436 I2C_WRITE_REG(sc, I2C_PSC, psc); 437 I2C_WRITE_REG(sc, I2C_SCLL, scll); 438 I2C_WRITE_REG(sc, I2C_SCLH, sclh); 439 440 /* Own I2C address */ 441 I2C_WRITE_REG(sc, I2C_OA, OMAP2_I2C_SLAVE_ADDR); 442 443 /* 5 bytes fifo */ 444 I2C_WRITE_REG(sc, I2C_BUF, 445 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres)); 446 447 /* Enable */ 448 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN); 449 450 return 0; 451 } 452 453 static int 454 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op, 455 uint8_t *buf, size_t buflen, int flags) 456 { 457 uint16_t con, stat, mask; 458 int err, retry; 459 460 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE); 461 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n", 462 addr, op, buf, (unsigned int) buflen, flags)); 463 464 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL; 465 if (op == TI_I2CREAD) { 466 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY; 467 } else { 468 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY; 469 } 470 471 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags); 472 if (err) { 473 DPRINTF(("ti_iic_op: wait error %d\n", err)); 474 return err; 475 } 476 477 con = I2C_CON_EN; 478 con |= I2C_CON_MST; 479 con |= I2C_CON_STT; 480 if (flags & I2C_F_STOP) 481 con |= I2C_CON_STP; 482 if (addr & ~0x7f) 483 con |= I2C_CON_XSA; 484 if (op == TI_I2CWRITE) 485 con |= I2C_CON_TRX; 486 487 mutex_enter(&sc->sc_mtx); 488 sc->sc_op = op; 489 sc->sc_opflags = flags; 490 sc->sc_buf = buf; 491 sc->sc_buflen = buflen; 492 sc->sc_bufidx = 0; 493 494 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP); 495 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con)); 496 I2C_WRITE_REG(sc, I2C_CNT, buflen); 497 I2C_WRITE_REG(sc, I2C_SA, (addr & I2C_SA_MASK)); 498 DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, I2C_SA), I2C_READ_REG(sc, I2C_CNT))); 499 500 if ((flags & I2C_F_POLL) == 0 || sc->sc_type == TI_IIC_OMAP3) { 501 /* clear any pending interrupt */ 502 I2C_WRITE_REG(sc, I2C_IRQSTATUS, 503 I2C_READ_REG(sc, I2C_IRQSTATUS)); 504 /* and enable */ 505 if (sc->sc_type == TI_IIC_OMAP4) { 506 I2C_WRITE_REG(sc, I2C_IRQENABLE_SET, mask); 507 } else { 508 I2C_WRITE_REG(sc, I2C_IRQENABLE, mask); 509 } 510 } 511 /* start transfer */ 512 I2C_WRITE_REG(sc, I2C_CON, con); 513 514 if ((flags & I2C_F_POLL) == 0) { 515 /* and wait for completion */ 516 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op)); 517 while (sc->sc_op == op) { 518 if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx, 519 mstohz(5000)) == EWOULDBLOCK) { 520 /* timeout */ 521 op = TI_I2CERROR; 522 } 523 } 524 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op)); 525 526 /* disable interrupts */ 527 if (sc->sc_type == TI_IIC_OMAP4) { 528 I2C_WRITE_REG(sc, I2C_IRQENABLE_CLR, 0xffff); 529 } else { 530 I2C_WRITE_REG(sc, I2C_IRQENABLE, 0); 531 } 532 } else { 533 /* poll for completion */ 534 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op)); 535 while (sc->sc_op == op) { 536 stat = ti_iic_stat(sc, mask); 537 DPRINTF(("ti_iic_op stat 0x%x\n", stat)); 538 if (stat == 0) { 539 /* timeout */ 540 sc->sc_op = TI_I2CERROR; 541 } else { 542 ti_iic_handle_intr(sc, stat); 543 } 544 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat); 545 } 546 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op)); 547 } 548 mutex_exit(&sc->sc_mtx); 549 retry = 10000; 550 I2C_WRITE_REG(sc, I2C_CON, 0); 551 while (I2C_READ_REG(sc, I2C_CON) & I2C_CON_MST) { 552 delay(100); 553 if (--retry == 0) 554 break; 555 } 556 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO; 557 } 558 559 static void 560 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat) 561 { 562 KASSERT(mutex_owned(&sc->sc_mtx)); 563 KASSERT(stat != 0); 564 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat)); 565 566 if (stat & 567 (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) { 568 sc->sc_op = TI_I2CERROR; 569 return; 570 } 571 if (stat & I2C_IRQSTATUS_ARDY) { 572 sc->sc_op = TI_I2CDONE; 573 return; 574 } 575 if (sc->sc_op == TI_I2CREAD) 576 ti_iic_do_read(sc, stat); 577 else if (sc->sc_op == TI_I2CWRITE) 578 ti_iic_do_write(sc, stat); 579 else 580 return; 581 } 582 void 583 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat) 584 { 585 int len = 0; 586 587 KASSERT(mutex_owned(&sc->sc_mtx)); 588 DPRINTF(("ti_iic_do_read stat %#x\n", stat)); 589 if (stat & I2C_IRQSTATUS_RDR) { 590 len = I2C_READ_REG(sc, I2C_BUFSTAT); 591 len = I2C_BUFSTAT_RXSTAT(len); 592 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n", 593 len, I2C_READ_REG(sc, I2C_CNT))); 594 } else if (stat & I2C_IRQSTATUS_RRDY) { 595 len = sc->sc_rxthres + 1; 596 DPRINTF(("ti_iic_do_read receive len %d left %d\n", 597 len, I2C_READ_REG(sc, I2C_CNT))); 598 } 599 for (; 600 sc->sc_bufidx < sc->sc_buflen && len > 0; 601 sc->sc_bufidx++, len--) { 602 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc); 603 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx, 604 sc->sc_buf[sc->sc_bufidx])); 605 } 606 DPRINTF(("ti_iic_do_read done\n")); 607 } 608 609 void 610 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat) 611 { 612 int len = 0; 613 614 DPRINTF(("ti_iic_do_write stat %#x\n", stat)); 615 KASSERT(mutex_owned(&sc->sc_mtx)); 616 if (stat & I2C_IRQSTATUS_XDR) { 617 len = I2C_READ_REG(sc, I2C_BUFSTAT); 618 len = I2C_BUFSTAT_TXSTAT(len); 619 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n", 620 len, I2C_READ_REG(sc, I2C_CNT))); 621 } else if (stat & I2C_IRQSTATUS_XRDY) { 622 len = sc->sc_txthres + 1; 623 DPRINTF(("ti_iic_do_write xmit len %d left %d\n", 624 len, I2C_READ_REG(sc, I2C_CNT))); 625 } 626 for (; 627 sc->sc_bufidx < sc->sc_buflen && len > 0; 628 sc->sc_bufidx++, len--) { 629 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n", 630 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx])); 631 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]); 632 } 633 DPRINTF(("ti_iic_do_write done\n")); 634 } 635 636 static int 637 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags) 638 { 639 int retry = 10; 640 uint16_t v; 641 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags)); 642 643 while (((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & mask) != val) { 644 --retry; 645 if (retry == 0) { 646 aprint_error_dev(sc->sc_dev, ": wait timeout, " 647 "mask = %#x val = %#x stat = %#x\n", 648 mask, val, v); 649 return EBUSY; 650 } 651 if (flags & I2C_F_POLL) { 652 delay(50000); 653 } else { 654 kpause("tiiic", false, mstohz(50), NULL); 655 } 656 } 657 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 658 659 return 0; 660 } 661 662 static uint32_t 663 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask) 664 { 665 uint32_t v; 666 int retry = 500; 667 DPRINTF(("ti_iic_wait mask %#x\n", mask)); 668 while (--retry > 0) { 669 v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW) & mask; 670 if (v != 0) 671 break; 672 delay(100); 673 } 674 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 675 return v; 676 } 677 678 static int 679 ti_iic_flush(struct ti_iic_softc *sc) 680 { 681 DPRINTF(("ti_iic_flush\n")); 682 #if 0 683 int retry = 1000; 684 uint16_t v; 685 686 while ((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) { 687 if (--retry == 0) { 688 aprint_error_dev(sc->sc_dev, 689 ": flush timeout, stat = %#x\n", v); 690 return EBUSY; 691 } 692 (void)I2C_READ_DATA(sc); 693 delay(1000); 694 } 695 #endif 696 697 I2C_WRITE_REG(sc, I2C_CNT, 0); 698 return 0; 699 } 700
Indexes created Tue Sep 30 20:09:53 GMT 2025