ti_iic.c revision 1.2
1 /* $NetBSD: ti_iic.c,v 1.2 2019/10/29 22:19:13 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2012 Jared D. McNeill <jmcneill (at) invisible.ca> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.2 2019/10/29 22:19:13 jmcneill Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/conf.h> 59 #include <sys/bus.h> 60 #include <sys/proc.h> 61 #include <sys/kernel.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 65 #include <dev/i2c/i2cvar.h> 66 67 #include <dev/fdt/fdtvar.h> 68 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_iicreg.h> 71 72 #ifndef OMAP2_I2C_SLAVE_ADDR 73 #define OMAP2_I2C_SLAVE_ADDR 0x01 74 #endif 75 76 #define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd)) 77 78 #ifdef I2CDEBUG 79 #define DPRINTF(args) printf args 80 #else 81 #define DPRINTF(args) 82 #endif 83 84 static const struct of_compat_data compat_data[] = { 85 /* compatible reg shift */ 86 { "ti,omap3-i2c", 2 }, 87 { "ti,omap4-i2c", 0 }, 88 { NULL } 89 }; 90 91 /* operation in progress */ 92 typedef enum { 93 TI_I2CREAD, 94 TI_I2CWRITE, 95 TI_I2CDONE, 96 TI_I2CERROR 97 } ti_i2cop_t; 98 99 struct ti_iic_softc { 100 device_t sc_dev; 101 struct i2c_controller sc_ic; 102 kmutex_t sc_lock; 103 device_t sc_i2cdev; 104 105 bus_space_tag_t sc_iot; 106 bus_space_handle_t sc_ioh; 107 108 u_int sc_reg_shift; 109 110 void *sc_ih; 111 kmutex_t sc_mtx; 112 kcondvar_t sc_cv; 113 ti_i2cop_t sc_op; 114 int sc_buflen; 115 int sc_bufidx; 116 char *sc_buf; 117 118 bool sc_busy; 119 120 int sc_rxthres; 121 int sc_txthres; 122 }; 123 124 #define I2C_READ_REG(sc, reg) \ 125 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg) << (sc)->sc_reg_shift) 126 #define I2C_READ_DATA(sc) \ 127 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA << (sc)->sc_reg_shift); 128 #define I2C_WRITE_REG(sc, reg, val) \ 129 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg) << (sc)->sc_reg_shift, (val)) 130 #define I2C_WRITE_DATA(sc, val) \ 131 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA << (sc)->sc_reg_shift, (val)) 132 133 static int ti_iic_match(device_t, cfdata_t, void *); 134 static void ti_iic_attach(device_t, device_t, void *); 135 136 static int ti_iic_intr(void *); 137 138 static int ti_iic_acquire_bus(void *, int); 139 static void ti_iic_release_bus(void *, int); 140 static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, 141 size_t, void *, size_t, int); 142 143 static int ti_iic_reset(struct ti_iic_softc *); 144 static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, 145 uint8_t *, size_t, int); 146 static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t); 147 static void ti_iic_do_read(struct ti_iic_softc *, uint32_t); 148 static void ti_iic_do_write(struct ti_iic_softc *, uint32_t); 149 150 static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int); 151 static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t); 152 static int ti_iic_flush(struct ti_iic_softc *); 153 154 static i2c_tag_t ti_iic_get_tag(device_t); 155 156 static const struct fdtbus_i2c_controller_func ti_iic_funcs = { 157 .get_tag = ti_iic_get_tag, 158 }; 159 160 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc), 161 ti_iic_match, ti_iic_attach, NULL, NULL); 162 163 static int 164 ti_iic_match(device_t parent, cfdata_t match, void *opaque) 165 { 166 struct fdt_attach_args * const faa = opaque; 167 168 return of_match_compat_data(faa->faa_phandle, compat_data); 169 } 170 171 static void 172 ti_iic_attach(device_t parent, device_t self, void *opaque) 173 { 174 struct ti_iic_softc *sc = device_private(self); 175 struct fdt_attach_args * const faa = opaque; 176 const int phandle = faa->faa_phandle; 177 int scheme, major, minor, fifodepth, fifo; 178 char intrstr[128]; 179 bus_addr_t addr; 180 bus_size_t size; 181 uint16_t rev; 182 183 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 184 aprint_error(": couldn't get registers\n"); 185 return; 186 } 187 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 188 aprint_error(": couldn't decode interrupt\n"); 189 return; 190 } 191 192 if (ti_prcm_enable_hwmod(phandle, 0) != 0) { 193 aprint_error(": couldn't enable module\n"); 194 return; 195 } 196 197 sc->sc_dev = self; 198 sc->sc_iot = faa->faa_bst; 199 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 200 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 201 cv_init(&sc->sc_cv, "tiiic"); 202 sc->sc_ic.ic_cookie = sc; 203 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus; 204 sc->sc_ic.ic_release_bus = ti_iic_release_bus; 205 sc->sc_ic.ic_exec = ti_iic_exec; 206 207 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 208 aprint_error(": couldn't map registers\n"); 209 return; 210 } 211 sc->sc_reg_shift = of_search_compatible(phandle, compat_data)->data; 212 213 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0, 214 ti_iic_intr, sc); 215 if (sc->sc_ih == NULL) { 216 aprint_error(": couldn't establish interrupt\n"); 217 return; 218 } 219 220 scheme = I2C_REVNB_HI_SCHEME(I2C_READ_REG(sc, OMAP2_I2C_REVNB_HI)); 221 rev = I2C_READ_REG(sc, OMAP2_I2C_REVNB_LO); 222 if (scheme == 0) { 223 major = I2C_REV_SCHEME_0_MAJOR(rev); 224 minor = I2C_REV_SCHEME_0_MINOR(rev); 225 } else { 226 major = I2C_REVNB_LO_MAJOR(rev); 227 minor = I2C_REVNB_LO_MINOR(rev); 228 } 229 aprint_normal(": rev %d.%d, scheme %d\n", major, minor, scheme); 230 aprint_naive("\n"); 231 232 fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT)); 233 fifo = OMAP2_I2C_FIFOBYTES(fifodepth); 234 aprint_normal_dev(self, "%d-bytes FIFO\n", fifo); 235 sc->sc_rxthres = sc->sc_txthres = fifo >> 1; 236 237 ti_iic_reset(sc); 238 ti_iic_flush(sc); 239 240 fdtbus_register_i2c_controller(self, phandle, &ti_iic_funcs); 241 242 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 243 } 244 245 static int 246 ti_iic_intr(void *arg) 247 { 248 struct ti_iic_softc *sc = arg; 249 uint32_t stat; 250 251 mutex_enter(&sc->sc_mtx); 252 DPRINTF(("ti_iic_intr\n")); 253 stat = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS); 254 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op)); 255 ti_iic_handle_intr(sc, stat); 256 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat); 257 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) { 258 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op)); 259 cv_broadcast(&sc->sc_cv); 260 } 261 mutex_exit(&sc->sc_mtx); 262 DPRINTF(("ti_iic_intr status 0x%x\n", stat)); 263 return 1; 264 } 265 266 static int 267 ti_iic_acquire_bus(void *opaque, int flags) 268 { 269 struct ti_iic_softc *sc = opaque; 270 271 mutex_enter(&sc->sc_lock); 272 while (sc->sc_busy) 273 cv_wait(&sc->sc_cv, &sc->sc_lock); 274 sc->sc_busy = true; 275 mutex_exit(&sc->sc_lock); 276 277 return 0; 278 } 279 280 static void 281 ti_iic_release_bus(void *opaque, int flags) 282 { 283 struct ti_iic_softc *sc = opaque; 284 285 mutex_enter(&sc->sc_lock); 286 sc->sc_busy = false; 287 cv_broadcast(&sc->sc_cv); 288 mutex_exit(&sc->sc_lock); 289 } 290 291 static int 292 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr, 293 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 294 { 295 struct ti_iic_softc *sc = opaque; 296 int err; 297 298 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n", 299 op, cmdlen, len, flags)); 300 301 if (cmdlen > 0) { 302 err = ti_iic_op(sc, addr, TI_I2CWRITE, 303 __UNCONST(cmdbuf), cmdlen, 304 (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags); 305 if (err) 306 goto done; 307 } 308 309 if (I2C_OP_STOP_P(op)) 310 flags |= I2C_F_STOP; 311 312 /* 313 * I2C controller doesn't allow for zero-byte transfers. 314 */ 315 if (len == 0) { 316 err = EINVAL; 317 goto done; 318 } 319 320 if (I2C_OP_READ_P(op)) { 321 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags); 322 } else { 323 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags); 324 } 325 326 done: 327 if (err) 328 ti_iic_reset(sc); 329 330 ti_iic_flush(sc); 331 332 DPRINTF(("ti_iic_exec: done %d\n", err)); 333 return err; 334 } 335 336 static int 337 ti_iic_reset(struct ti_iic_softc *sc) 338 { 339 uint32_t psc, scll, sclh; 340 int i; 341 342 DPRINTF(("ti_iic_reset\n")); 343 344 /* Disable */ 345 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 346 /* Soft reset */ 347 I2C_WRITE_REG(sc, OMAP2_I2C_SYSC, I2C_SYSC_SRST); 348 delay(1000); 349 /* enable so that we can check for reset complete */ 350 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN); 351 delay(1000); 352 for (i = 0; i < 1000; i++) { /* 1s delay for reset */ 353 if (I2C_READ_REG(sc, OMAP2_I2C_SYSS) & I2C_SYSS_RDONE) 354 break; 355 } 356 /* Disable again */ 357 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 358 delay(50000); 359 360 if (i >= 1000) { 361 aprint_error_dev(sc->sc_dev, ": couldn't reset module\n"); 362 return 1; 363 } 364 365 366 /* XXX standard speed only */ 367 psc = 3; 368 scll = 53; 369 sclh = 55; 370 371 /* Clocks */ 372 I2C_WRITE_REG(sc, OMAP2_I2C_PSC, psc); 373 I2C_WRITE_REG(sc, OMAP2_I2C_SCLL, scll); 374 I2C_WRITE_REG(sc, OMAP2_I2C_SCLH, sclh); 375 376 /* Own I2C address */ 377 I2C_WRITE_REG(sc, OMAP2_I2C_OA, OMAP2_I2C_SLAVE_ADDR); 378 379 /* 5 bytes fifo */ 380 I2C_WRITE_REG(sc, OMAP2_I2C_BUF, 381 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres)); 382 383 /* Enable */ 384 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN); 385 386 return 0; 387 } 388 389 static int 390 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op, 391 uint8_t *buf, size_t buflen, int flags) 392 { 393 uint16_t con, stat, mask; 394 int err, retry; 395 396 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE); 397 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n", 398 addr, op, buf, (unsigned int) buflen, flags)); 399 400 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL; 401 if (op == TI_I2CREAD) { 402 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY; 403 } else { 404 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY; 405 } 406 407 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags); 408 if (err) { 409 DPRINTF(("ti_iic_op: wait error %d\n", err)); 410 return err; 411 } 412 413 con = I2C_CON_EN; 414 con |= I2C_CON_MST; 415 con |= I2C_CON_STT;; 416 if (flags & I2C_F_STOP) 417 con |= I2C_CON_STP; 418 if (addr & ~0x7f) 419 con |= I2C_CON_XSA; 420 if (op == TI_I2CWRITE) 421 con |= I2C_CON_TRX; 422 423 mutex_enter(&sc->sc_mtx); 424 sc->sc_op = op; 425 sc->sc_buf = buf; 426 sc->sc_buflen = buflen; 427 sc->sc_bufidx = 0; 428 429 I2C_WRITE_REG(sc, OMAP2_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP); 430 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con)); 431 I2C_WRITE_REG(sc, OMAP2_I2C_CNT, buflen); 432 I2C_WRITE_REG(sc, OMAP2_I2C_SA, (addr & I2C_SA_MASK)); 433 DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, OMAP2_I2C_SA), I2C_READ_REG(sc, OMAP2_I2C_CNT))); 434 435 if ((flags & I2C_F_POLL) == 0) { 436 /* clear any pending interrupt */ 437 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, 438 I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS)); 439 /* and enable */ 440 I2C_WRITE_REG(sc, OMAP2_I2C_IRQENABLE_SET, mask); 441 } 442 /* start transfer */ 443 I2C_WRITE_REG(sc, OMAP2_I2C_CON, con); 444 445 if ((flags & I2C_F_POLL) == 0) { 446 /* and wait for completion */ 447 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op)); 448 while (sc->sc_op == op) { 449 if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx, 450 mstohz(5000)) == EWOULDBLOCK) { 451 /* timeout */ 452 op = TI_I2CERROR; 453 } 454 } 455 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op)); 456 457 /* disable interrupts */ 458 I2C_WRITE_REG(sc, OMAP2_I2C_IRQENABLE_CLR, 0xffff); 459 } else { 460 /* poll for completion */ 461 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op)); 462 while (sc->sc_op == op) { 463 stat = ti_iic_stat(sc, mask); 464 DPRINTF(("ti_iic_op stat 0x%x\n", stat)); 465 if (stat == 0) { 466 /* timeout */ 467 sc->sc_op = TI_I2CERROR; 468 } else { 469 ti_iic_handle_intr(sc, stat); 470 } 471 I2C_WRITE_REG(sc, OMAP2_I2C_IRQSTATUS, stat); 472 } 473 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op)); 474 } 475 mutex_exit(&sc->sc_mtx); 476 retry = 10000; 477 I2C_WRITE_REG(sc, OMAP2_I2C_CON, 0); 478 while (I2C_READ_REG(sc, OMAP2_I2C_CON) & I2C_CON_MST) { 479 delay(100); 480 if (--retry == 0) 481 break; 482 } 483 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO; 484 } 485 486 static void 487 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat) 488 { 489 KASSERT(mutex_owned(&sc->sc_mtx)); 490 KASSERT(stat != 0); 491 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat)); 492 493 if (stat & 494 (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) { 495 sc->sc_op = TI_I2CERROR; 496 return; 497 } 498 if (stat & I2C_IRQSTATUS_ARDY) { 499 sc->sc_op = TI_I2CDONE; 500 return; 501 } 502 if (sc->sc_op == TI_I2CREAD) 503 ti_iic_do_read(sc, stat); 504 else if (sc->sc_op == TI_I2CWRITE) 505 ti_iic_do_write(sc, stat); 506 else 507 return; 508 } 509 void 510 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat) 511 { 512 int len = 0; 513 514 KASSERT(mutex_owned(&sc->sc_mtx)); 515 DPRINTF(("ti_iic_do_read stat %#x\n", stat)); 516 if (stat & I2C_IRQSTATUS_RDR) { 517 len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT); 518 len = I2C_BUFSTAT_RXSTAT(len); 519 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n", 520 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 521 } else if (stat & I2C_IRQSTATUS_RRDY) { 522 len = sc->sc_rxthres + 1; 523 DPRINTF(("ti_iic_do_read receive len %d left %d\n", 524 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 525 } 526 for (; 527 sc->sc_bufidx < sc->sc_buflen && len > 0; 528 sc->sc_bufidx++, len--) { 529 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc); 530 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx, 531 sc->sc_buf[sc->sc_bufidx])); 532 } 533 DPRINTF(("ti_iic_do_read done\n")); 534 } 535 536 void 537 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat) 538 { 539 int len = 0; 540 541 DPRINTF(("ti_iic_do_write stat %#x\n", stat)); 542 KASSERT(mutex_owned(&sc->sc_mtx)); 543 if (stat & I2C_IRQSTATUS_XDR) { 544 len = I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT); 545 len = I2C_BUFSTAT_TXSTAT(len); 546 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n", 547 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 548 } else if (stat & I2C_IRQSTATUS_XRDY) { 549 len = sc->sc_txthres + 1; 550 DPRINTF(("ti_iic_do_write xmit len %d left %d\n", 551 len, I2C_READ_REG(sc, OMAP2_I2C_CNT))); 552 } 553 for (; 554 sc->sc_bufidx < sc->sc_buflen && len > 0; 555 sc->sc_bufidx++, len--) { 556 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n", 557 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx])); 558 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]); 559 } 560 DPRINTF(("ti_iic_do_write done\n")); 561 } 562 563 static int 564 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags) 565 { 566 int retry = 10; 567 uint16_t v; 568 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags)); 569 570 while (((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & mask) != val) { 571 --retry; 572 if (retry == 0) { 573 aprint_error_dev(sc->sc_dev, ": wait timeout, " 574 "mask = %#x val = %#x stat = %#x\n", 575 mask, val, v); 576 return EBUSY; 577 } 578 if (flags & I2C_F_POLL) { 579 delay(50000); 580 } else { 581 kpause("tiiic", false, mstohz(50), NULL); 582 } 583 } 584 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 585 586 return 0; 587 } 588 589 static uint32_t 590 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask) 591 { 592 uint32_t v; 593 int retry = 500; 594 DPRINTF(("ti_iic_wait mask %#x\n", mask)); 595 while (--retry > 0) { 596 v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW) & mask; 597 if (v != 0) 598 break; 599 delay(100); 600 } 601 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 602 return v; 603 } 604 605 static int 606 ti_iic_flush(struct ti_iic_softc *sc) 607 { 608 DPRINTF(("ti_iic_flush\n")); 609 #if 0 610 int retry = 1000; 611 uint16_t v; 612 613 while ((v = I2C_READ_REG(sc, OMAP2_I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) { 614 if (--retry == 0) { 615 aprint_error_dev(sc->sc_dev, 616 ": flush timeout, stat = %#x\n", v); 617 return EBUSY; 618 } 619 (void)I2C_READ_DATA(sc); 620 delay(1000); 621 } 622 #endif 623 624 I2C_WRITE_REG(sc, OMAP2_I2C_CNT, 0); 625 return 0; 626 } 627 628 static i2c_tag_t 629 ti_iic_get_tag(device_t dev) 630 { 631 struct ti_iic_softc * const sc = device_private(dev); 632 633 return &sc->sc_ic; 634 } 635
Indexes created Tue Sep 30 17:09:57 GMT 2025