ti_iic.c revision 1.6
1 /* $NetBSD: ti_iic.c,v 1.6 2020/06/03 16:00:00 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2012 Jared D. McNeill <jmcneill (at) invisible.ca> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.6 2020/06/03 16:00:00 jmcneill Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/conf.h> 59 #include <sys/bus.h> 60 #include <sys/proc.h> 61 #include <sys/kernel.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 65 #include <dev/i2c/i2cvar.h> 66 67 #include <dev/fdt/fdtvar.h> 68 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_iicreg.h> 71 72 #ifndef OMAP2_I2C_SLAVE_ADDR 73 #define OMAP2_I2C_SLAVE_ADDR 0x01 74 #endif 75 76 #define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd)) 77 78 #ifdef I2CDEBUG 79 #define DPRINTF(args) printf args 80 #else 81 #define DPRINTF(args) 82 #endif 83 84 enum ti_iic_type { 85 TI_IIC_OMAP3, 86 TI_IIC_OMAP4, 87 TI_NTYPES 88 }; 89 90 enum { 91 I2C_SYSC, 92 I2C_IRQSTATUS_RAW, 93 I2C_IRQSTATUS, 94 I2C_IRQENABLE, /* OMAP3 */ 95 I2C_IRQENABLE_SET, /* OMAP4 */ 96 I2C_IRQENABLE_CLR, /* OMAP4 */ 97 I2C_SYSS, 98 I2C_BUF, 99 I2C_CNT, 100 I2C_DATA, 101 I2C_CON, 102 I2C_OA, 103 I2C_SA, 104 I2C_PSC, 105 I2C_SCLL, 106 I2C_SCLH, 107 I2C_BUFSTAT, 108 TI_NREGS 109 }; 110 111 static const u_int ti_iic_regmap[TI_NTYPES][TI_NREGS] = { 112 [TI_IIC_OMAP3] = { 113 [I2C_SYSC] = 0x20, 114 [I2C_IRQSTATUS_RAW] = 0x08, 115 [I2C_IRQSTATUS] = 0x08, 116 [I2C_IRQENABLE] = 0x04, 117 [I2C_SYSS] = 0x10, 118 [I2C_BUF] = 0x14, 119 [I2C_CNT] = 0x18, 120 [I2C_DATA] = 0x1c, 121 [I2C_CON] = 0x24, 122 [I2C_OA] = 0x28, 123 [I2C_SA] = 0x2c, 124 [I2C_PSC] = 0x30, 125 [I2C_SCLL] = 0x34, 126 [I2C_SCLH] = 0x38, 127 [I2C_BUFSTAT] = 0x40, 128 }, 129 [TI_IIC_OMAP4] = { 130 [I2C_SYSC] = 0x10, 131 [I2C_IRQSTATUS_RAW] = 0x24, 132 [I2C_IRQSTATUS] = 0x28, 133 [I2C_IRQENABLE_SET] = 0x2c, 134 [I2C_IRQENABLE_CLR] = 0x30, 135 [I2C_SYSS] = 0x90, 136 [I2C_BUF] = 0x94, 137 [I2C_CNT] = 0x98, 138 [I2C_DATA] = 0x9c, 139 [I2C_CON] = 0xa4, 140 [I2C_OA] = 0xa8, 141 [I2C_SA] = 0xac, 142 [I2C_PSC] = 0xb0, 143 [I2C_SCLL] = 0xb4, 144 [I2C_SCLH] = 0xb8, 145 [I2C_BUFSTAT] = 0xc0, 146 }, 147 }; 148 149 static const struct of_compat_data compat_data[] = { 150 /* compatible type */ 151 { "ti,omap3-i2c", TI_IIC_OMAP3 }, 152 { "ti,omap4-i2c", TI_IIC_OMAP4 }, 153 { NULL } 154 }; 155 156 /* operation in progress */ 157 typedef enum { 158 TI_I2CREAD, 159 TI_I2CWRITE, 160 TI_I2CDONE, 161 TI_I2CERROR 162 } ti_i2cop_t; 163 164 struct ti_iic_softc { 165 device_t sc_dev; 166 struct i2c_controller sc_ic; 167 kmutex_t sc_lock; 168 device_t sc_i2cdev; 169 170 bus_space_tag_t sc_iot; 171 bus_space_handle_t sc_ioh; 172 173 enum ti_iic_type sc_type; 174 175 void *sc_ih; 176 kmutex_t sc_mtx; 177 kcondvar_t sc_cv; 178 ti_i2cop_t sc_op; 179 int sc_opflags; 180 int sc_buflen; 181 int sc_bufidx; 182 char *sc_buf; 183 184 bool sc_busy; 185 186 int sc_rxthres; 187 int sc_txthres; 188 }; 189 190 #define I2C_READ_REG(sc, reg) \ 191 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)]) 192 #define I2C_READ_DATA(sc) \ 193 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA]) 194 #define I2C_WRITE_REG(sc, reg, val) \ 195 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)], (val)) 196 #define I2C_WRITE_DATA(sc, val) \ 197 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA], (val)) 198 199 static int ti_iic_match(device_t, cfdata_t, void *); 200 static void ti_iic_attach(device_t, device_t, void *); 201 202 static int ti_iic_intr(void *); 203 204 static int ti_iic_acquire_bus(void *, int); 205 static void ti_iic_release_bus(void *, int); 206 static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, 207 size_t, void *, size_t, int); 208 209 static int ti_iic_reset(struct ti_iic_softc *); 210 static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, 211 uint8_t *, size_t, int); 212 static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t); 213 static void ti_iic_do_read(struct ti_iic_softc *, uint32_t); 214 static void ti_iic_do_write(struct ti_iic_softc *, uint32_t); 215 216 static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int); 217 static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t); 218 static int ti_iic_flush(struct ti_iic_softc *); 219 220 static i2c_tag_t ti_iic_get_tag(device_t); 221 222 static const struct fdtbus_i2c_controller_func ti_iic_funcs = { 223 .get_tag = ti_iic_get_tag, 224 }; 225 226 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc), 227 ti_iic_match, ti_iic_attach, NULL, NULL); 228 229 static int 230 ti_iic_match(device_t parent, cfdata_t match, void *opaque) 231 { 232 struct fdt_attach_args * const faa = opaque; 233 234 return of_match_compat_data(faa->faa_phandle, compat_data); 235 } 236 237 static void 238 ti_iic_attach(device_t parent, device_t self, void *opaque) 239 { 240 struct ti_iic_softc *sc = device_private(self); 241 struct fdt_attach_args * const faa = opaque; 242 const int phandle = faa->faa_phandle; 243 int fifodepth, fifo; 244 const char *modname; 245 char intrstr[128]; 246 bus_addr_t addr; 247 bus_size_t size; 248 249 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 250 aprint_error(": couldn't get registers\n"); 251 return; 252 } 253 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 254 aprint_error(": couldn't decode interrupt\n"); 255 return; 256 } 257 258 if (ti_prcm_enable_hwmod(phandle, 0) != 0) { 259 aprint_error(": couldn't enable module\n"); 260 return; 261 } 262 263 sc->sc_dev = self; 264 sc->sc_iot = faa->faa_bst; 265 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 266 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 267 cv_init(&sc->sc_cv, "tiiic"); 268 sc->sc_ic.ic_cookie = sc; 269 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus; 270 sc->sc_ic.ic_release_bus = ti_iic_release_bus; 271 sc->sc_ic.ic_exec = ti_iic_exec; 272 273 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 274 aprint_error(": couldn't map registers\n"); 275 return; 276 } 277 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 278 279 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0, 280 ti_iic_intr, sc); 281 if (sc->sc_ih == NULL) { 282 aprint_error(": couldn't establish interrupt\n"); 283 return; 284 } 285 286 modname = fdtbus_get_string(phandle, "ti,hwmods"); 287 if (modname == NULL) 288 modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods"); 289 290 fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, I2C_BUFSTAT)); 291 fifo = OMAP2_I2C_FIFOBYTES(fifodepth); 292 sc->sc_rxthres = sc->sc_txthres = fifo >> 1; 293 294 aprint_naive("\n"); 295 if (modname != NULL) 296 aprint_normal(": I2C controller (%s), %d-bytes FIFO\n", modname, fifo); 297 else 298 aprint_normal(": I2C controller (i2c@%" PRIxBUSADDR "), %d-bytes FIFO\n", 299 addr, fifo); 300 301 ti_iic_reset(sc); 302 ti_iic_flush(sc); 303 304 fdtbus_register_i2c_controller(self, phandle, &ti_iic_funcs); 305 306 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 307 } 308 309 static int 310 ti_iic_intr(void *arg) 311 { 312 struct ti_iic_softc *sc = arg; 313 uint32_t stat; 314 315 mutex_enter(&sc->sc_mtx); 316 DPRINTF(("ti_iic_intr opflags=%#x\n", sc->sc_opflags)); 317 if ((sc->sc_opflags & I2C_F_POLL) == 0) { 318 stat = I2C_READ_REG(sc, I2C_IRQSTATUS); 319 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op)); 320 ti_iic_handle_intr(sc, stat); 321 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat); 322 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) { 323 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op)); 324 cv_broadcast(&sc->sc_cv); 325 } 326 } 327 mutex_exit(&sc->sc_mtx); 328 DPRINTF(("ti_iic_intr status 0x%x\n", stat)); 329 return 1; 330 } 331 332 static int 333 ti_iic_acquire_bus(void *opaque, int flags) 334 { 335 struct ti_iic_softc *sc = opaque; 336 337 mutex_enter(&sc->sc_lock); 338 while (sc->sc_busy) 339 cv_wait(&sc->sc_cv, &sc->sc_lock); 340 sc->sc_busy = true; 341 mutex_exit(&sc->sc_lock); 342 343 return 0; 344 } 345 346 static void 347 ti_iic_release_bus(void *opaque, int flags) 348 { 349 struct ti_iic_softc *sc = opaque; 350 351 mutex_enter(&sc->sc_lock); 352 sc->sc_busy = false; 353 cv_broadcast(&sc->sc_cv); 354 mutex_exit(&sc->sc_lock); 355 } 356 357 static int 358 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr, 359 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 360 { 361 struct ti_iic_softc *sc = opaque; 362 int err; 363 364 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n", 365 op, cmdlen, len, flags)); 366 367 if (cmdlen > 0) { 368 err = ti_iic_op(sc, addr, TI_I2CWRITE, 369 __UNCONST(cmdbuf), cmdlen, 370 (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags); 371 if (err) 372 goto done; 373 } 374 375 if (I2C_OP_STOP_P(op)) 376 flags |= I2C_F_STOP; 377 378 /* 379 * I2C controller doesn't allow for zero-byte transfers. 380 */ 381 if (len == 0) { 382 err = EINVAL; 383 goto done; 384 } 385 386 if (I2C_OP_READ_P(op)) { 387 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags); 388 } else { 389 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags); 390 } 391 392 done: 393 if (err) 394 ti_iic_reset(sc); 395 396 ti_iic_flush(sc); 397 398 DPRINTF(("ti_iic_exec: done %d\n", err)); 399 return err; 400 } 401 402 static int 403 ti_iic_reset(struct ti_iic_softc *sc) 404 { 405 uint32_t psc, scll, sclh; 406 int i; 407 408 DPRINTF(("ti_iic_reset\n")); 409 410 /* Disable */ 411 I2C_WRITE_REG(sc, I2C_CON, 0); 412 /* Soft reset */ 413 I2C_WRITE_REG(sc, I2C_SYSC, I2C_SYSC_SRST); 414 delay(1000); 415 /* enable so that we can check for reset complete */ 416 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN); 417 delay(1000); 418 for (i = 0; i < 1000; i++) { /* 1s delay for reset */ 419 if (I2C_READ_REG(sc, I2C_SYSS) & I2C_SYSS_RDONE) 420 break; 421 } 422 /* Disable again */ 423 I2C_WRITE_REG(sc, I2C_CON, 0); 424 delay(50000); 425 426 if (i >= 1000) { 427 aprint_error_dev(sc->sc_dev, ": couldn't reset module\n"); 428 return 1; 429 } 430 431 432 /* XXX standard speed only */ 433 if (sc->sc_type == TI_IIC_OMAP3) { 434 psc = (96000000 / 19200000) - 1; 435 scll = sclh = (19200000 / (2 * 100000)) - 6; 436 } else { 437 psc = 3; 438 scll = 53; 439 sclh = 55; 440 } 441 442 /* Clocks */ 443 I2C_WRITE_REG(sc, I2C_PSC, psc); 444 I2C_WRITE_REG(sc, I2C_SCLL, scll); 445 I2C_WRITE_REG(sc, I2C_SCLH, sclh); 446 447 /* Own I2C address */ 448 I2C_WRITE_REG(sc, I2C_OA, OMAP2_I2C_SLAVE_ADDR); 449 450 /* 5 bytes fifo */ 451 I2C_WRITE_REG(sc, I2C_BUF, 452 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres)); 453 454 /* Enable */ 455 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN); 456 457 return 0; 458 } 459 460 static int 461 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op, 462 uint8_t *buf, size_t buflen, int flags) 463 { 464 uint16_t con, stat, mask; 465 int err, retry; 466 467 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE); 468 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n", 469 addr, op, buf, (unsigned int) buflen, flags)); 470 471 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL; 472 if (op == TI_I2CREAD) { 473 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY; 474 } else { 475 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY; 476 } 477 478 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags); 479 if (err) { 480 DPRINTF(("ti_iic_op: wait error %d\n", err)); 481 return err; 482 } 483 484 con = I2C_CON_EN; 485 con |= I2C_CON_MST; 486 con |= I2C_CON_STT; 487 if (flags & I2C_F_STOP) 488 con |= I2C_CON_STP; 489 if (addr & ~0x7f) 490 con |= I2C_CON_XSA; 491 if (op == TI_I2CWRITE) 492 con |= I2C_CON_TRX; 493 494 mutex_enter(&sc->sc_mtx); 495 sc->sc_op = op; 496 sc->sc_opflags = flags; 497 sc->sc_buf = buf; 498 sc->sc_buflen = buflen; 499 sc->sc_bufidx = 0; 500 501 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP); 502 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con)); 503 I2C_WRITE_REG(sc, I2C_CNT, buflen); 504 I2C_WRITE_REG(sc, I2C_SA, (addr & I2C_SA_MASK)); 505 DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, I2C_SA), I2C_READ_REG(sc, I2C_CNT))); 506 507 if ((flags & I2C_F_POLL) == 0 || sc->sc_type == TI_IIC_OMAP3) { 508 /* clear any pending interrupt */ 509 I2C_WRITE_REG(sc, I2C_IRQSTATUS, 510 I2C_READ_REG(sc, I2C_IRQSTATUS)); 511 /* and enable */ 512 if (sc->sc_type == TI_IIC_OMAP4) { 513 I2C_WRITE_REG(sc, I2C_IRQENABLE_SET, mask); 514 } else { 515 I2C_WRITE_REG(sc, I2C_IRQENABLE, mask); 516 } 517 } 518 /* start transfer */ 519 I2C_WRITE_REG(sc, I2C_CON, con); 520 521 if ((flags & I2C_F_POLL) == 0) { 522 /* and wait for completion */ 523 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op)); 524 while (sc->sc_op == op) { 525 if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx, 526 mstohz(5000)) == EWOULDBLOCK) { 527 /* timeout */ 528 op = TI_I2CERROR; 529 } 530 } 531 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op)); 532 533 /* disable interrupts */ 534 if (sc->sc_type == TI_IIC_OMAP4) { 535 I2C_WRITE_REG(sc, I2C_IRQENABLE_CLR, 0xffff); 536 } else { 537 I2C_WRITE_REG(sc, I2C_IRQENABLE, 0); 538 } 539 } else { 540 /* poll for completion */ 541 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op)); 542 while (sc->sc_op == op) { 543 stat = ti_iic_stat(sc, mask); 544 DPRINTF(("ti_iic_op stat 0x%x\n", stat)); 545 if (stat == 0) { 546 /* timeout */ 547 sc->sc_op = TI_I2CERROR; 548 } else { 549 ti_iic_handle_intr(sc, stat); 550 } 551 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat); 552 } 553 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op)); 554 } 555 mutex_exit(&sc->sc_mtx); 556 retry = 10000; 557 I2C_WRITE_REG(sc, I2C_CON, 0); 558 while (I2C_READ_REG(sc, I2C_CON) & I2C_CON_MST) { 559 delay(100); 560 if (--retry == 0) 561 break; 562 } 563 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO; 564 } 565 566 static void 567 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat) 568 { 569 KASSERT(mutex_owned(&sc->sc_mtx)); 570 KASSERT(stat != 0); 571 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat)); 572 573 if (stat & 574 (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) { 575 sc->sc_op = TI_I2CERROR; 576 return; 577 } 578 if (stat & I2C_IRQSTATUS_ARDY) { 579 sc->sc_op = TI_I2CDONE; 580 return; 581 } 582 if (sc->sc_op == TI_I2CREAD) 583 ti_iic_do_read(sc, stat); 584 else if (sc->sc_op == TI_I2CWRITE) 585 ti_iic_do_write(sc, stat); 586 else 587 return; 588 } 589 void 590 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat) 591 { 592 int len = 0; 593 594 KASSERT(mutex_owned(&sc->sc_mtx)); 595 DPRINTF(("ti_iic_do_read stat %#x\n", stat)); 596 if (stat & I2C_IRQSTATUS_RDR) { 597 len = I2C_READ_REG(sc, I2C_BUFSTAT); 598 len = I2C_BUFSTAT_RXSTAT(len); 599 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n", 600 len, I2C_READ_REG(sc, I2C_CNT))); 601 } else if (stat & I2C_IRQSTATUS_RRDY) { 602 len = sc->sc_rxthres + 1; 603 DPRINTF(("ti_iic_do_read receive len %d left %d\n", 604 len, I2C_READ_REG(sc, I2C_CNT))); 605 } 606 for (; 607 sc->sc_bufidx < sc->sc_buflen && len > 0; 608 sc->sc_bufidx++, len--) { 609 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc); 610 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx, 611 sc->sc_buf[sc->sc_bufidx])); 612 } 613 DPRINTF(("ti_iic_do_read done\n")); 614 } 615 616 void 617 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat) 618 { 619 int len = 0; 620 621 DPRINTF(("ti_iic_do_write stat %#x\n", stat)); 622 KASSERT(mutex_owned(&sc->sc_mtx)); 623 if (stat & I2C_IRQSTATUS_XDR) { 624 len = I2C_READ_REG(sc, I2C_BUFSTAT); 625 len = I2C_BUFSTAT_TXSTAT(len); 626 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n", 627 len, I2C_READ_REG(sc, I2C_CNT))); 628 } else if (stat & I2C_IRQSTATUS_XRDY) { 629 len = sc->sc_txthres + 1; 630 DPRINTF(("ti_iic_do_write xmit len %d left %d\n", 631 len, I2C_READ_REG(sc, I2C_CNT))); 632 } 633 for (; 634 sc->sc_bufidx < sc->sc_buflen && len > 0; 635 sc->sc_bufidx++, len--) { 636 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n", 637 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx])); 638 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]); 639 } 640 DPRINTF(("ti_iic_do_write done\n")); 641 } 642 643 static int 644 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags) 645 { 646 int retry = 10; 647 uint16_t v; 648 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags)); 649 650 while (((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & mask) != val) { 651 --retry; 652 if (retry == 0) { 653 aprint_error_dev(sc->sc_dev, ": wait timeout, " 654 "mask = %#x val = %#x stat = %#x\n", 655 mask, val, v); 656 return EBUSY; 657 } 658 if (flags & I2C_F_POLL) { 659 delay(50000); 660 } else { 661 kpause("tiiic", false, mstohz(50), NULL); 662 } 663 } 664 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 665 666 return 0; 667 } 668 669 static uint32_t 670 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask) 671 { 672 uint32_t v; 673 int retry = 500; 674 DPRINTF(("ti_iic_wait mask %#x\n", mask)); 675 while (--retry > 0) { 676 v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW) & mask; 677 if (v != 0) 678 break; 679 delay(100); 680 } 681 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 682 return v; 683 } 684 685 static int 686 ti_iic_flush(struct ti_iic_softc *sc) 687 { 688 DPRINTF(("ti_iic_flush\n")); 689 #if 0 690 int retry = 1000; 691 uint16_t v; 692 693 while ((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) { 694 if (--retry == 0) { 695 aprint_error_dev(sc->sc_dev, 696 ": flush timeout, stat = %#x\n", v); 697 return EBUSY; 698 } 699 (void)I2C_READ_DATA(sc); 700 delay(1000); 701 } 702 #endif 703 704 I2C_WRITE_REG(sc, I2C_CNT, 0); 705 return 0; 706 } 707 708 static i2c_tag_t 709 ti_iic_get_tag(device_t dev) 710 { 711 struct ti_iic_softc * const sc = device_private(dev); 712 713 return &sc->sc_ic; 714 } 715
Indexes created Tue Sep 30 17:09:57 GMT 2025