11.1Sjmcneill/* $NetBSD: ti_otgreg.h,v 1.1 2019/10/27 16:31:26 jmcneill Exp $ */ 21.1Sjmcneill/* 31.1Sjmcneill * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 41.1Sjmcneill * 51.1Sjmcneill * Redistribution and use in source and binary forms, with or without 61.1Sjmcneill * modification, are permitted provided that the following conditions 71.1Sjmcneill * are met: 81.1Sjmcneill * 1. Redistributions of source code must retain the above copyright 91.1Sjmcneill * notice, this list of conditions and the following disclaimer. 101.1Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 111.1Sjmcneill * notice, this list of conditions and the following disclaimer in the 121.1Sjmcneill * documentation and/or other materials provided with the distribution. 131.1Sjmcneill * 141.1Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 151.1Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 161.1Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 171.1Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 181.1Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 191.1Sjmcneill * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 201.1Sjmcneill * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 211.1Sjmcneill * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 221.1Sjmcneill * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 231.1Sjmcneill * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 241.1Sjmcneill */ 251.1Sjmcneill 261.1Sjmcneill#define TI_OTG_NPORTS 2 271.1Sjmcneill/* USBSS registers */ 281.1Sjmcneill#define TIOTG_USBSS_OFFSET 0 291.1Sjmcneill#define TIOTG_USBSS_READ4(sc, reg) \ 301.1Sjmcneill bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET) 311.1Sjmcneill#define TIOTG_USBSS_WRITE4(sc, reg, val) \ 321.1Sjmcneill bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET, (val)) 331.1Sjmcneill 341.1Sjmcneill#define USBSS_REVREG 0x00 351.1Sjmcneill#define USBSS_SYSCONFIG 0x10 361.1Sjmcneill#define USBSS_SYSCONFIG_USB0_OCP_EN_N 0x800 371.1Sjmcneill#define USBSS_SYSCONFIG_PHY0_UTMI_EN_N 0x400 381.1Sjmcneill#define USBSS_SYSCONFIG_USB1_OCP_EN_N 0x200 391.1Sjmcneill#define USBSS_SYSCONFIG_PHY1_UTMI_EN_N 0x100 401.1Sjmcneill#define USBSS_SYSCONFIG_STBYMODE_SHIFT 4 411.1Sjmcneill#define USBSS_SYSCONFIG_IDLEMODE_SHIFT 2 421.1Sjmcneill#define USBSS_SYSCONFIG_FREEEMU 0x002 431.1Sjmcneill#define USBSS_SYSCONFIG_SRESET 0x001 441.1Sjmcneill 451.1Sjmcneill/* USB control registers */ 461.1Sjmcneill#define USB_CTRL_OFFSET(port) (0x1000 + (0x800 * (port))) 471.1Sjmcneill#define USB_PORT_SIZE 0x800 /* size of CTRL+PHY+CORE */ 481.1Sjmcneill#define TIOTG_USBC_READ4(sc, reg) \ 491.1Sjmcneill bus_space_read_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg)) 501.1Sjmcneill#define TIOTG_USBC_WRITE4(sc, reg, val) \ 511.1Sjmcneill bus_space_write_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg), (val)) 521.1Sjmcneill 531.1Sjmcneill#define USBCTRL_REV 0x00 541.1Sjmcneill#define USBCTRL_CTRL 0x14 551.1Sjmcneill#define USBCTRL_STAT 0x18 561.1Sjmcneill#define USBCTRL_IRQ_STAT0 0x30 571.1Sjmcneill#define USBCTRL_IRQ_STAT0_RXSHIFT 16 581.1Sjmcneill#define USBCTRL_IRQ_STAT0_TXSHIFT 0 591.1Sjmcneill#define USBCTRL_IRQ_STAT1 0x34 601.1Sjmcneill#define USBCTRL_IRQ_STAT1_DRVVBUS (1 << 8) 611.1Sjmcneill#define USBCTRL_INTEN_SET0 0x38 621.1Sjmcneill#define USBCTRL_INTEN_SET1 0x3C 631.1Sjmcneill#define USBCTRL_INTEN_USB_ALL 0x1ff 641.1Sjmcneill#define USBCTRL_INTEN_USB_SOF (1 << 3) 651.1Sjmcneill#define USBCTRL_INTEN_CLR0 0x40 661.1Sjmcneill#define USBCTRL_INTEN_CLR1 0x44 671.1Sjmcneill#define USBCTRL_UTMI 0xE0 681.1Sjmcneill#define USBCTRL_UTMI_FSDATAEXT (1 << 1) 691.1Sjmcneill#define USBCTRL_MODE 0xE8 701.1Sjmcneill#define USBCTRL_MODE_IDDIG (1 << 8) 711.1Sjmcneill#define USBCTRL_MODE_IDDIGMUX (1 << 7) 721.1Sjmcneill 731.1Sjmcneill#define USB_CORE_OFFSET 0x400 741.1Sjmcneill#define USB_CORE_SIZE 0x400 75