ti_sdhc.c revision 1.1
1 /* $NetBSD: ti_sdhc.c,v 1.1 2019/10/27 15:43:46 jmcneill Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ti_sdhc.c,v 1.1 2019/10/27 15:43:46 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 45 #include <arm/ti/ti_prcm.h> 46 #include <arm/ti/ti_edma.h> 47 #include <arm/ti/ti_sdhcreg.h> 48 49 #include <dev/sdmmc/sdhcreg.h> 50 #include <dev/sdmmc/sdhcvar.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 #define EDMA_MAX_PARAMS 32 56 57 #ifdef TISDHC_DEBUG 58 int tisdhcdebug = 1; 59 #define DPRINTF(n,s) do { if ((n) <= tisdhcdebug) device_printf s; } while (0) 60 #else 61 #define DPRINTF(n,s) do {} while (0) 62 #endif 63 64 65 #define CLKD(kz) (sc->sc.sc_clkbase / (kz)) 66 67 #define SDHC_READ(sc, reg) \ 68 bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg)) 69 #define SDHC_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val)) 71 72 struct ti_sdhc_config { 73 bus_size_t regoff; 74 uint32_t flags; 75 }; 76 77 static const struct ti_sdhc_config omap2_hsmmc_config = { 78 }; 79 80 static const struct ti_sdhc_config omap3_pre_es3_hsmmc_config = { 81 .flags = SDHC_FLAG_SINGLE_ONLY 82 }; 83 84 static const struct ti_sdhc_config omap4_hsmmc_config = { 85 .regoff = 0x100 86 }; 87 88 static const struct of_compat_data compat_data[] = { 89 { "ti,omap2-hsmmc", (uintptr_t)&omap2_hsmmc_config }, 90 { "ti,omap3-hsmmc", (uintptr_t)&omap2_hsmmc_config }, 91 { "ti,omap3-pre-es3-hsmmc", (uintptr_t)&omap3_pre_es3_hsmmc_config }, 92 { "ti,omap4-hsmmc", (uintptr_t)&omap4_hsmmc_config }, 93 { NULL } 94 }; 95 96 enum { 97 EDMA_CHAN_TX, 98 EDMA_CHAN_RX, 99 EDMA_NCHAN 100 }; 101 102 struct ti_sdhc_softc { 103 struct sdhc_softc sc; 104 int sc_phandle; 105 bus_addr_t sc_addr; 106 bus_space_tag_t sc_bst; 107 bus_space_handle_t sc_bsh; 108 bus_space_handle_t sc_hl_bsh; 109 bus_space_handle_t sc_sdhc_bsh; 110 struct sdhc_host *sc_hosts[1]; 111 void *sc_ih; /* interrupt vectoring */ 112 113 int sc_edma_chan[EDMA_NCHAN]; 114 struct edma_channel *sc_edma_tx; 115 struct edma_channel *sc_edma_rx; 116 uint16_t sc_edma_param_tx[EDMA_MAX_PARAMS]; 117 uint16_t sc_edma_param_rx[EDMA_MAX_PARAMS]; 118 kcondvar_t sc_edma_cv; 119 bus_addr_t sc_edma_fifo; 120 bool sc_edma_pending; 121 bus_dmamap_t sc_edma_dmamap; 122 bus_dma_segment_t sc_edma_segs[1]; 123 void *sc_edma_bbuf; 124 }; 125 126 static int ti_sdhc_match(device_t, cfdata_t, void *); 127 static void ti_sdhc_attach(device_t, device_t, void *); 128 129 static void ti_sdhc_init(struct ti_sdhc_softc *, const struct ti_sdhc_config *); 130 131 static int ti_sdhc_bus_width(struct sdhc_softc *, int); 132 static int ti_sdhc_rod(struct sdhc_softc *, int); 133 static int ti_sdhc_write_protect(struct sdhc_softc *); 134 static int ti_sdhc_card_detect(struct sdhc_softc *); 135 136 static int ti_sdhc_edma_init(struct ti_sdhc_softc *, u_int, u_int); 137 static int ti_sdhc_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *); 138 static void ti_sdhc_edma_done(void *); 139 static int ti_sdhc_edma_transfer(struct sdhc_softc *, struct sdmmc_command *); 140 141 CFATTACH_DECL_NEW(ti_sdhc, sizeof(struct ti_sdhc_softc), 142 ti_sdhc_match, ti_sdhc_attach, NULL, NULL); 143 144 static int 145 ti_sdhc_match(device_t parent, cfdata_t cf, void *aux) 146 { 147 struct fdt_attach_args * const faa = aux; 148 149 return of_match_compat_data(faa->faa_phandle, compat_data); 150 } 151 152 static void 153 ti_sdhc_attach(device_t parent, device_t self, void *aux) 154 { 155 struct ti_sdhc_softc * const sc = device_private(self); 156 struct fdt_attach_args * const faa = aux; 157 const int phandle = faa->faa_phandle; 158 const struct ti_sdhc_config *conf; 159 bus_addr_t addr; 160 bus_size_t size; 161 u_int bus_width; 162 163 conf = (const void *)of_search_compatible(phandle, compat_data)->data; 164 165 if (ti_prcm_enable_hwmod(OF_parent(phandle), 0) != 0) { 166 aprint_error(": couldn't enable module\n"); 167 return; 168 } 169 170 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 || size <= conf->regoff) { 171 aprint_error(": couldn't get registers\n"); 172 return; 173 } 174 addr += conf->regoff; 175 size -= conf->regoff; 176 177 sc->sc.sc_dmat = faa->faa_dmat; 178 sc->sc.sc_dev = self; 179 sc->sc_phandle = phandle; 180 sc->sc_addr = addr; 181 sc->sc_bst = faa->faa_bst; 182 183 #if notyet 184 /* XXX use fdtbus_dma API */ 185 int len; 186 const u_int *dmas = fdtbus_get_prop(phandle, "dmas", &len); 187 switch (len) { 188 case 24: 189 sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]); 190 sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[4]); 191 break; 192 case 32: 193 sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]); 194 sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[5]); 195 break; 196 default: 197 sc->sc_edma_chan[EDMA_CHAN_TX] = -1; 198 sc->sc_edma_chan[EDMA_CHAN_RX] = -1; 199 break; 200 } 201 #else 202 sc->sc_edma_chan[EDMA_CHAN_TX] = -1; 203 sc->sc_edma_chan[EDMA_CHAN_RX] = -1; 204 #endif 205 206 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 207 aprint_error(": couldn't map registers\n"); 208 return; 209 } 210 211 if (of_getprop_uint32(phandle, "bus-width", &bus_width) != 0) 212 bus_width = 4; 213 214 sc->sc.sc_flags |= conf->flags; 215 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 216 sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON; 217 sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC; 218 if (bus_width == 8) 219 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 220 if (of_hasprop(phandle, "ti,needs-special-reset")) 221 sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET; 222 if (of_hasprop(phandle, "ti,needs-special-hs-handling")) 223 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 224 if (of_hasprop(phandle, "ti,dual-volt")) 225 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_0V; 226 227 sc->sc.sc_host = sc->sc_hosts; 228 sc->sc.sc_clkbase = 96000; /* 96MHZ */ 229 sc->sc.sc_clkmsk = 0x0000ffc0; 230 sc->sc.sc_vendor_rod = ti_sdhc_rod; 231 sc->sc.sc_vendor_write_protect = ti_sdhc_write_protect; 232 sc->sc.sc_vendor_card_detect = ti_sdhc_card_detect; 233 sc->sc.sc_vendor_bus_width = ti_sdhc_bus_width; 234 235 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, 0x100, 0x100, 236 &sc->sc_sdhc_bsh) != 0) { 237 aprint_error(": couldn't map subregion\n"); 238 return; 239 } 240 241 aprint_naive("\n"); 242 aprint_normal(": MMCHS\n"); 243 244 ti_sdhc_init(sc, conf); 245 } 246 247 static void 248 ti_sdhc_init(struct ti_sdhc_softc *sc, const struct ti_sdhc_config *conf) 249 { 250 device_t dev = sc->sc.sc_dev; 251 uint32_t clkd, stat; 252 int error, timo, clksft, n; 253 char intrstr[128]; 254 255 const int tx_chan = sc->sc_edma_chan[EDMA_CHAN_TX]; 256 const int rx_chan = sc->sc_edma_chan[EDMA_CHAN_RX]; 257 258 if (tx_chan != -1 && rx_chan != -1) { 259 aprint_normal_dev(dev, 260 "EDMA tx channel %d, rx channel %d\n", 261 tx_chan, rx_chan); 262 263 if (ti_sdhc_edma_init(sc, tx_chan, rx_chan) != 0) { 264 aprint_error_dev(dev, "EDMA disabled\n"); 265 goto no_dma; 266 } 267 268 cv_init(&sc->sc_edma_cv, "sdhcedma"); 269 sc->sc_edma_fifo = sc->sc_addr + 0x100 + SDHC_DATA; 270 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 271 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 272 sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN; 273 sc->sc.sc_vendor_transfer_data_dma = ti_sdhc_edma_xfer_data; 274 } 275 no_dma: 276 277 /* XXXXXX: Turn-on regulator via I2C. */ 278 /* XXXXXX: And enable ICLOCK/FCLOCK. */ 279 280 SDHC_WRITE(sc, SDHC_CAPABILITIES, 281 SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_1_8V); 282 if (sc->sc.sc_caps & SDHC_VOLTAGE_SUPP_3_0V) 283 SDHC_WRITE(sc, SDHC_CAPABILITIES, 284 SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_3_0V); 285 286 /* MMCHS Soft reset */ 287 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG, 288 SYSCONFIG_SOFTRESET); 289 timo = 3000000; /* XXXX 3 sec. */ 290 while (timo--) { 291 if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) & 292 SYSSTATUS_RESETDONE) 293 break; 294 delay(1); 295 } 296 if (timo == 0) 297 aprint_error_dev(dev, "Soft reset timeout\n"); 298 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG, 299 SYSCONFIG_ENAWAKEUP | 300 SYSCONFIG_AUTOIDLE | 301 SYSCONFIG_SIDLEMODE_AUTO | 302 SYSCONFIG_CLOCKACTIVITY_FCLK | 303 SYSCONFIG_CLOCKACTIVITY_ICLK); 304 305 if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) { 306 aprint_error_dev(dev, "couldn't decode interrupt\n"); 307 return; 308 } 309 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, 310 0, sdhc_intr, &sc->sc); 311 if (sc->sc_ih == NULL) { 312 aprint_error_dev(dev, "couldn't establish interrupt\n"); 313 return; 314 } 315 aprint_normal_dev(dev, "interrupting on %s\n", intrstr); 316 317 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh, 0x100); 318 if (error != 0) { 319 aprint_error_dev(dev, "couldn't initialize host, error=%d\n", 320 error); 321 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 322 return; 323 } 324 325 clksft = ffs(sc->sc.sc_clkmsk) - 1; 326 327 /* Set SDVS 1.8v and DTW 1bit mode */ 328 SDHC_WRITE(sc, SDHC_HOST_CTL, 329 SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8)); 330 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 331 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE | 332 SDHC_SDCLK_ENABLE); 333 SDHC_WRITE(sc, SDHC_HOST_CTL, 334 SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8); 335 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 336 SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft); 337 338 /* 339 * 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start 340 * from 'OMAP35x Applications Processor Technical Reference Manual'. 341 * 342 * During the INIT procedure, the MMCHS controller generates 80 clock 343 * periods. In order to keep the 1ms gap, the MMCHS controller should 344 * be configured to generate a clock whose frequency is smaller or 345 * equal to 80 KHz. 346 */ 347 348 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 349 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE); 350 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 351 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk); 352 clkd = CLKD(80); 353 n = 1; 354 while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) { 355 clkd >>= 1; 356 n <<= 1; 357 } 358 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 359 SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft)); 360 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 361 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE); 362 363 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 364 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT); 365 SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000); 366 delay(1000); 367 stat = SDHC_READ(sc, SDHC_NINTR_STATUS); 368 SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat | SDHC_COMMAND_COMPLETE); 369 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 370 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT); 371 SDHC_WRITE(sc, SDHC_NINTR_STATUS, 0xffffffff); 372 373 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 374 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE); 375 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 376 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk); 377 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 378 SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft); 379 timo = 3000000; /* XXXX 3 sec. */ 380 while (--timo) { 381 if (SDHC_READ(sc, SDHC_CLOCK_CTL) & SDHC_INTCLK_STABLE) 382 break; 383 delay(1); 384 } 385 if (timo == 0) 386 aprint_error_dev(dev, "ICS timeout\n"); 387 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 388 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE); 389 390 if (sc->sc.sc_flags & SDHC_FLAG_USE_ADMA2) 391 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 392 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | 393 CON_MNS); 394 } 395 396 static int 397 ti_sdhc_rod(struct sdhc_softc *sc, int on) 398 { 399 struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc; 400 uint32_t con; 401 402 con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON); 403 if (on) 404 con |= CON_OD; 405 else 406 con &= ~CON_OD; 407 bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con); 408 409 return 0; 410 } 411 412 static int 413 ti_sdhc_write_protect(struct sdhc_softc *sc) 414 { 415 416 /* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */ 417 return 0; /* XXXXXXX */ 418 } 419 420 static int 421 ti_sdhc_card_detect(struct sdhc_softc *sc) 422 { 423 424 /* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */ 425 return 1; /* XXXXXXXX */ 426 } 427 428 static int 429 ti_sdhc_bus_width(struct sdhc_softc *sc, int width) 430 { 431 struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc; 432 uint32_t con; 433 434 con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON); 435 if (width == 8) { 436 con |= CON_DW8; 437 } else { 438 con &= ~CON_DW8; 439 } 440 bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con); 441 442 return 0; 443 } 444 445 static int 446 ti_sdhc_edma_init(struct ti_sdhc_softc *sc, u_int tx_chan, u_int rx_chan) 447 { 448 int i, error, rseg; 449 450 /* Request tx and rx DMA channels */ 451 sc->sc_edma_tx = edma_channel_alloc(EDMA_TYPE_DMA, tx_chan, 452 ti_sdhc_edma_done, sc); 453 KASSERT(sc->sc_edma_tx != NULL); 454 sc->sc_edma_rx = edma_channel_alloc(EDMA_TYPE_DMA, rx_chan, 455 ti_sdhc_edma_done, sc); 456 KASSERT(sc->sc_edma_rx != NULL); 457 458 /* Allocate some PaRAM pages */ 459 for (i = 0; i < __arraycount(sc->sc_edma_param_tx); i++) { 460 sc->sc_edma_param_tx[i] = edma_param_alloc(sc->sc_edma_tx); 461 KASSERT(sc->sc_edma_param_tx[i] != 0xffff); 462 } 463 for (i = 0; i < __arraycount(sc->sc_edma_param_rx); i++) { 464 sc->sc_edma_param_rx[i] = edma_param_alloc(sc->sc_edma_rx); 465 KASSERT(sc->sc_edma_param_rx[i] != 0xffff); 466 } 467 468 /* Setup bounce buffer */ 469 error = bus_dmamem_alloc(sc->sc.sc_dmat, MAXPHYS, 32, MAXPHYS, 470 sc->sc_edma_segs, 1, &rseg, BUS_DMA_WAITOK); 471 if (error) { 472 aprint_error_dev(sc->sc.sc_dev, 473 "couldn't allocate dmamem: %d\n", error); 474 return error; 475 } 476 KASSERT(rseg == 1); 477 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_edma_segs, rseg, MAXPHYS, 478 &sc->sc_edma_bbuf, BUS_DMA_WAITOK); 479 if (error) { 480 aprint_error_dev(sc->sc.sc_dev, "couldn't map dmamem: %d\n", 481 error); 482 return error; 483 } 484 error = bus_dmamap_create(sc->sc.sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 485 BUS_DMA_WAITOK, &sc->sc_edma_dmamap); 486 if (error) { 487 aprint_error_dev(sc->sc.sc_dev, "couldn't create dmamap: %d\n", 488 error); 489 return error; 490 } 491 492 return error; 493 } 494 495 static int 496 ti_sdhc_edma_xfer_data(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 497 { 498 struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev); 499 const bus_dmamap_t map = cmd->c_dmamap; 500 int seg, error; 501 bool bounce; 502 503 for (bounce = false, seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 504 if ((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) != 0) { 505 bounce = true; 506 break; 507 } 508 } 509 510 if (bounce) { 511 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_edma_dmamap, 512 sc->sc_edma_bbuf, MAXPHYS, NULL, BUS_DMA_WAITOK); 513 if (error) { 514 device_printf(sc->sc.sc_dev, 515 "[bounce] bus_dmamap_load failed: %d\n", error); 516 return error; 517 } 518 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 519 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 520 MAXPHYS, BUS_DMASYNC_PREREAD); 521 } else { 522 memcpy(sc->sc_edma_bbuf, cmd->c_data, cmd->c_datalen); 523 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 524 MAXPHYS, BUS_DMASYNC_PREWRITE); 525 } 526 527 cmd->c_dmamap = sc->sc_edma_dmamap; 528 } 529 530 error = ti_sdhc_edma_transfer(sdhc_sc, cmd); 531 532 if (bounce) { 533 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 534 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 535 MAXPHYS, BUS_DMASYNC_POSTREAD); 536 } else { 537 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 538 MAXPHYS, BUS_DMASYNC_POSTWRITE); 539 } 540 bus_dmamap_unload(sc->sc.sc_dmat, sc->sc_edma_dmamap); 541 if (ISSET(cmd->c_flags, SCF_CMD_READ) && error == 0) { 542 memcpy(cmd->c_data, sc->sc_edma_bbuf, cmd->c_datalen); 543 } 544 545 cmd->c_dmamap = map; 546 } 547 548 return error; 549 } 550 551 static int 552 ti_sdhc_edma_transfer(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 553 { 554 struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev); 555 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 556 struct edma_channel *edma; 557 uint16_t *edma_param; 558 struct edma_param ep; 559 size_t seg; 560 int error, resid = cmd->c_datalen; 561 int blksize = MIN(cmd->c_datalen, cmd->c_blklen); 562 563 KASSERT(mutex_owned(plock)); 564 565 edma = ISSET(cmd->c_flags, SCF_CMD_READ) ? 566 sc->sc_edma_rx : sc->sc_edma_tx; 567 edma_param = ISSET(cmd->c_flags, SCF_CMD_READ) ? 568 sc->sc_edma_param_rx : sc->sc_edma_param_tx; 569 570 DPRINTF(1, (sc->sc.sc_dev, "edma xfer: nsegs=%d ch# %d\n", 571 cmd->c_dmamap->dm_nsegs, edma_channel_index(edma))); 572 573 if (cmd->c_dmamap->dm_nsegs > EDMA_MAX_PARAMS) { 574 return ENOMEM; 575 } 576 577 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 578 KASSERT(resid > 0); 579 const int xferlen = uimin(resid, 580 cmd->c_dmamap->dm_segs[seg].ds_len); 581 KASSERT(xferlen == cmd->c_dmamap->dm_segs[seg].ds_len || 582 seg == cmd->c_dmamap->dm_nsegs - 1); 583 resid -= xferlen; 584 KASSERT((xferlen & 0x3) == 0); 585 ep.ep_opt = __SHIFTIN(2, EDMA_PARAM_OPT_FWID) /* 32-bit */; 586 ep.ep_opt |= __SHIFTIN(edma_channel_index(edma), 587 EDMA_PARAM_OPT_TCC); 588 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 589 ep.ep_opt |= EDMA_PARAM_OPT_TCINTEN; 590 ep.ep_link = 0xffff; 591 } else { 592 ep.ep_link = EDMA_PARAM_BASE(edma_param[seg+1]); 593 } 594 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 595 ep.ep_opt |= EDMA_PARAM_OPT_SAM; 596 ep.ep_src = sc->sc_edma_fifo; 597 ep.ep_dst = cmd->c_dmamap->dm_segs[seg].ds_addr; 598 } else { 599 ep.ep_opt |= EDMA_PARAM_OPT_DAM; 600 ep.ep_src = cmd->c_dmamap->dm_segs[seg].ds_addr; 601 ep.ep_dst = sc->sc_edma_fifo; 602 } 603 604 KASSERT(xferlen <= 65536 * 4); 605 606 /* 607 * In constant addressing mode, the address must be aligned 608 * to 256-bits. 609 */ 610 KASSERT((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) == 0); 611 612 /* 613 * For unknown reason, the A-DMA transfers never completes for 614 * transfers larger than 64 butes. So use a AB transfer, 615 * with a 64 bytes A len 616 */ 617 ep.ep_bcntrld = 0; /* not used for AB-synchronous mode */ 618 ep.ep_opt |= EDMA_PARAM_OPT_SYNCDIM; 619 ep.ep_acnt = uimin(xferlen, 64); 620 ep.ep_bcnt = uimin(xferlen, blksize) / ep.ep_acnt; 621 ep.ep_ccnt = xferlen / (ep.ep_acnt * ep.ep_bcnt); 622 ep.ep_srcbidx = ep.ep_dstbidx = 0; 623 ep.ep_srccidx = ep.ep_dstcidx = 0; 624 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 625 ep.ep_dstbidx = ep.ep_acnt; 626 ep.ep_dstcidx = ep.ep_acnt * ep.ep_bcnt; 627 } else { 628 ep.ep_srcbidx = ep.ep_acnt; 629 ep.ep_srccidx = ep.ep_acnt * ep.ep_bcnt; 630 } 631 632 edma_set_param(edma, edma_param[seg], &ep); 633 #ifdef TISDHC_DEBUG 634 if (tisdhcdebug >= 1) { 635 printf("target OPT: %08x\n", ep.ep_opt); 636 edma_dump_param(edma, edma_param[seg]); 637 } 638 #endif 639 } 640 641 error = 0; 642 sc->sc_edma_pending = true; 643 edma_transfer_enable(edma, edma_param[0]); 644 while (sc->sc_edma_pending) { 645 error = cv_timedwait(&sc->sc_edma_cv, plock, hz*10); 646 if (error == EWOULDBLOCK) { 647 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 648 edma_dump(edma); 649 edma_dump_param(edma, edma_param[0]); 650 edma_halt(edma); 651 sc->sc_edma_pending = false; 652 error = ETIMEDOUT; 653 break; 654 } 655 } 656 edma_halt(edma); 657 658 return error; 659 } 660 661 static void 662 ti_sdhc_edma_done(void *priv) 663 { 664 struct ti_sdhc_softc *sc = priv; 665 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 666 667 mutex_enter(plock); 668 KASSERT(sc->sc_edma_pending == true); 669 sc->sc_edma_pending = false; 670 cv_broadcast(&sc->sc_edma_cv); 671 mutex_exit(plock); 672 } 673
Indexes created Mon Oct 20 16:09:52 GMT 2025