ti_sdhc.c revision 1.10
1 /* $NetBSD: ti_sdhc.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ti_sdhc.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 45 #include <arm/ti/ti_prcm.h> 46 #include <arm/ti/ti_edma.h> 47 #include <arm/ti/ti_sdhcreg.h> 48 49 #include <dev/sdmmc/sdhcreg.h> 50 #include <dev/sdmmc/sdhcvar.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 #define EDMA_MAX_PARAMS 32 56 57 #ifdef TISDHC_DEBUG 58 int tisdhcdebug = 1; 59 #define DPRINTF(n,s) do { if ((n) <= tisdhcdebug) device_printf s; } while (0) 60 #else 61 #define DPRINTF(n,s) do {} while (0) 62 #endif 63 64 65 #define CLKD(kz) (sc->sc.sc_clkbase / (kz)) 66 67 #define SDHC_READ(sc, reg) \ 68 bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg)) 69 #define SDHC_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val)) 71 72 struct ti_sdhc_config { 73 bus_size_t regoff; 74 uint32_t flags; 75 }; 76 77 static const struct ti_sdhc_config omap2_hsmmc_config = { 78 }; 79 80 static const struct ti_sdhc_config omap3_pre_es3_hsmmc_config = { 81 .flags = SDHC_FLAG_SINGLE_ONLY 82 }; 83 84 static const struct ti_sdhc_config omap4_hsmmc_config = { 85 .regoff = 0x100 86 }; 87 88 static const struct device_compatible_entry compat_data[] = { 89 { .compat = "ti,omap2-hsmmc", 90 .data = &omap2_hsmmc_config }, 91 { .compat = "ti,omap3-hsmmc", 92 .data = &omap2_hsmmc_config }, 93 { .compat = "ti,omap3-pre-es3-hsmmc", 94 .data = &omap3_pre_es3_hsmmc_config }, 95 { .compat = "ti,omap4-hsmmc", 96 .data = &omap4_hsmmc_config }, 97 98 DEVICE_COMPAT_EOL 99 }; 100 101 enum { 102 EDMA_CHAN_TX, 103 EDMA_CHAN_RX, 104 EDMA_NCHAN 105 }; 106 107 struct ti_sdhc_softc { 108 struct sdhc_softc sc; 109 int sc_phandle; 110 bus_addr_t sc_addr; 111 bus_space_tag_t sc_bst; 112 bus_space_handle_t sc_bsh; 113 bus_space_handle_t sc_hl_bsh; 114 bus_space_handle_t sc_sdhc_bsh; 115 struct sdhc_host *sc_hosts[1]; 116 void *sc_ih; /* interrupt vectoring */ 117 118 int sc_edma_chan[EDMA_NCHAN]; 119 struct edma_channel *sc_edma_tx; 120 struct edma_channel *sc_edma_rx; 121 uint16_t sc_edma_param_tx[EDMA_MAX_PARAMS]; 122 uint16_t sc_edma_param_rx[EDMA_MAX_PARAMS]; 123 kcondvar_t sc_edma_cv; 124 bus_addr_t sc_edma_fifo; 125 bool sc_edma_pending; 126 bus_dmamap_t sc_edma_dmamap; 127 bus_dma_segment_t sc_edma_segs[1]; 128 void *sc_edma_bbuf; 129 }; 130 131 static int ti_sdhc_match(device_t, cfdata_t, void *); 132 static void ti_sdhc_attach(device_t, device_t, void *); 133 134 static void ti_sdhc_init(struct ti_sdhc_softc *, const struct ti_sdhc_config *); 135 136 static int ti_sdhc_bus_width(struct sdhc_softc *, int); 137 static int ti_sdhc_rod(struct sdhc_softc *, int); 138 static int ti_sdhc_write_protect(struct sdhc_softc *); 139 static int ti_sdhc_card_detect(struct sdhc_softc *); 140 141 static int ti_sdhc_edma_init(struct ti_sdhc_softc *, u_int, u_int); 142 static int ti_sdhc_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *); 143 static void ti_sdhc_edma_done(void *); 144 static int ti_sdhc_edma_transfer(struct sdhc_softc *, struct sdmmc_command *); 145 146 CFATTACH_DECL_NEW(ti_sdhc, sizeof(struct ti_sdhc_softc), 147 ti_sdhc_match, ti_sdhc_attach, NULL, NULL); 148 149 static int 150 ti_sdhc_match(device_t parent, cfdata_t cf, void *aux) 151 { 152 struct fdt_attach_args * const faa = aux; 153 154 return of_compatible_match(faa->faa_phandle, compat_data); 155 } 156 157 static void 158 ti_sdhc_attach(device_t parent, device_t self, void *aux) 159 { 160 struct ti_sdhc_softc * const sc = device_private(self); 161 struct fdt_attach_args * const faa = aux; 162 const int phandle = faa->faa_phandle; 163 const struct ti_sdhc_config *conf; 164 bus_addr_t addr; 165 bus_size_t size; 166 u_int bus_width; 167 168 conf = of_compatible_lookup(phandle, compat_data)->data; 169 170 if (ti_prcm_enable_hwmod(phandle, 0) != 0) { 171 aprint_error(": couldn't enable module\n"); 172 return; 173 } 174 175 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 || size <= conf->regoff) { 176 aprint_error(": couldn't get registers\n"); 177 return; 178 } 179 addr += conf->regoff; 180 size -= conf->regoff; 181 182 sc->sc.sc_dmat = faa->faa_dmat; 183 sc->sc.sc_dev = self; 184 sc->sc_phandle = phandle; 185 sc->sc_addr = addr; 186 sc->sc_bst = faa->faa_bst; 187 188 /* XXX use fdtbus_dma API */ 189 int len; 190 const u_int *dmas = fdtbus_get_prop(phandle, "dmas", &len); 191 switch (len) { 192 case 24: 193 sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]); 194 sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[4]); 195 break; 196 case 32: 197 sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]); 198 sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[5]); 199 break; 200 default: 201 sc->sc_edma_chan[EDMA_CHAN_TX] = -1; 202 sc->sc_edma_chan[EDMA_CHAN_RX] = -1; 203 break; 204 } 205 206 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 207 aprint_error(": couldn't map registers\n"); 208 return; 209 } 210 211 if (of_getprop_uint32(phandle, "bus-width", &bus_width) != 0) 212 bus_width = 4; 213 214 sc->sc.sc_flags |= conf->flags; 215 sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS; 216 sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON; 217 sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC; 218 if (bus_width == 8) 219 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 220 if (of_hasprop(phandle, "ti,needs-special-reset")) 221 sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET; 222 if (!of_hasprop(phandle, "ti,needs-special-hs-handling")) 223 sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT; 224 if (of_hasprop(phandle, "ti,dual-volt")) 225 sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_0V; 226 227 sc->sc.sc_host = sc->sc_hosts; 228 sc->sc.sc_clkbase = 96000; /* 96MHZ */ 229 sc->sc.sc_clkmsk = 0x0000ffc0; 230 sc->sc.sc_vendor_rod = ti_sdhc_rod; 231 sc->sc.sc_vendor_write_protect = ti_sdhc_write_protect; 232 sc->sc.sc_vendor_card_detect = ti_sdhc_card_detect; 233 sc->sc.sc_vendor_bus_width = ti_sdhc_bus_width; 234 235 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, 0x100, 0x100, 236 &sc->sc_sdhc_bsh) != 0) { 237 aprint_error(": couldn't map subregion\n"); 238 return; 239 } 240 241 aprint_naive("\n"); 242 aprint_normal(": MMCHS\n"); 243 244 ti_sdhc_init(sc, conf); 245 } 246 247 static void 248 ti_sdhc_init(struct ti_sdhc_softc *sc, const struct ti_sdhc_config *conf) 249 { 250 device_t dev = sc->sc.sc_dev; 251 uint32_t clkd, stat; 252 int error, timo, clksft, n; 253 char intrstr[128]; 254 255 const int tx_chan = sc->sc_edma_chan[EDMA_CHAN_TX]; 256 const int rx_chan = sc->sc_edma_chan[EDMA_CHAN_RX]; 257 258 if (tx_chan != -1 && rx_chan != -1) { 259 aprint_normal_dev(dev, 260 "EDMA tx channel %d, rx channel %d\n", 261 tx_chan, rx_chan); 262 263 if (ti_sdhc_edma_init(sc, tx_chan, rx_chan) != 0) { 264 aprint_error_dev(dev, "EDMA disabled\n"); 265 goto no_dma; 266 } 267 268 cv_init(&sc->sc_edma_cv, "sdhcedma"); 269 sc->sc_edma_fifo = sc->sc_addr + 0x100 + SDHC_DATA; 270 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 271 sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA; 272 sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN; 273 sc->sc.sc_vendor_transfer_data_dma = ti_sdhc_edma_xfer_data; 274 } 275 no_dma: 276 277 /* XXXXXX: Turn-on regulator via I2C. */ 278 /* XXXXXX: And enable ICLOCK/FCLOCK. */ 279 280 SDHC_WRITE(sc, SDHC_CAPABILITIES, 281 SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_1_8V); 282 if (sc->sc.sc_caps & SDHC_VOLTAGE_SUPP_3_0V) 283 SDHC_WRITE(sc, SDHC_CAPABILITIES, 284 SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_3_0V); 285 286 /* MMCHS Soft reset */ 287 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG, 288 SYSCONFIG_SOFTRESET); 289 timo = 3000000; /* XXXX 3 sec. */ 290 while (timo--) { 291 if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) & 292 SYSSTATUS_RESETDONE) 293 break; 294 delay(1); 295 } 296 if (timo == 0) 297 aprint_error_dev(dev, "Soft reset timeout\n"); 298 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG, 299 SYSCONFIG_ENAWAKEUP | 300 #if notyet 301 SYSCONFIG_AUTOIDLE | 302 SYSCONFIG_SIDLEMODE_AUTO | 303 #else 304 SYSCONFIG_SIDLEMODE_IGNORE | 305 #endif 306 SYSCONFIG_CLOCKACTIVITY_FCLK | 307 SYSCONFIG_CLOCKACTIVITY_ICLK); 308 309 if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) { 310 aprint_error_dev(dev, "couldn't decode interrupt\n"); 311 return; 312 } 313 sc->sc_ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_VM, 314 0, sdhc_intr, &sc->sc, device_xname(dev)); 315 if (sc->sc_ih == NULL) { 316 aprint_error_dev(dev, "couldn't establish interrupt\n"); 317 return; 318 } 319 aprint_normal_dev(dev, "interrupting on %s\n", intrstr); 320 321 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh, 0x100); 322 if (error != 0) { 323 aprint_error_dev(dev, "couldn't initialize host, error=%d\n", 324 error); 325 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 326 return; 327 } 328 329 clksft = ffs(sc->sc.sc_clkmsk) - 1; 330 331 /* Set SDVS 1.8v and DTW 1bit mode */ 332 SDHC_WRITE(sc, SDHC_HOST_CTL, 333 SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8)); 334 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 335 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE | 336 SDHC_SDCLK_ENABLE); 337 SDHC_WRITE(sc, SDHC_HOST_CTL, 338 SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8); 339 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 340 SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft); 341 342 /* 343 * 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start 344 * from 'OMAP35x Applications Processor Technical Reference Manual'. 345 * 346 * During the INIT procedure, the MMCHS controller generates 80 clock 347 * periods. In order to keep the 1ms gap, the MMCHS controller should 348 * be configured to generate a clock whose frequency is smaller or 349 * equal to 80 KHz. 350 */ 351 352 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 353 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE); 354 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 355 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk); 356 clkd = CLKD(80); 357 n = 1; 358 while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) { 359 clkd >>= 1; 360 n <<= 1; 361 } 362 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 363 SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft)); 364 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 365 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE); 366 367 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 368 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT); 369 SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000); 370 delay(1000); 371 stat = SDHC_READ(sc, SDHC_NINTR_STATUS); 372 SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat | SDHC_COMMAND_COMPLETE); 373 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 374 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT); 375 SDHC_WRITE(sc, SDHC_NINTR_STATUS, 0xffffffff); 376 377 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 378 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE); 379 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 380 SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk); 381 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 382 SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft); 383 timo = 3000000; /* XXXX 3 sec. */ 384 while (--timo) { 385 if (SDHC_READ(sc, SDHC_CLOCK_CTL) & SDHC_INTCLK_STABLE) 386 break; 387 delay(1); 388 } 389 if (timo == 0) 390 aprint_error_dev(dev, "ICS timeout\n"); 391 SDHC_WRITE(sc, SDHC_CLOCK_CTL, 392 SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE); 393 394 if (sc->sc.sc_flags & SDHC_FLAG_USE_ADMA2) 395 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON, 396 bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | 397 CON_MNS); 398 } 399 400 static int 401 ti_sdhc_rod(struct sdhc_softc *sc, int on) 402 { 403 struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc; 404 uint32_t con; 405 406 con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON); 407 if (on) 408 con |= CON_OD; 409 else 410 con &= ~CON_OD; 411 bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con); 412 413 return 0; 414 } 415 416 static int 417 ti_sdhc_write_protect(struct sdhc_softc *sc) 418 { 419 420 /* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */ 421 return 0; /* XXXXXXX */ 422 } 423 424 static int 425 ti_sdhc_card_detect(struct sdhc_softc *sc) 426 { 427 428 /* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */ 429 return 1; /* XXXXXXXX */ 430 } 431 432 static int 433 ti_sdhc_bus_width(struct sdhc_softc *sc, int width) 434 { 435 struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc; 436 uint32_t con, hctl; 437 438 con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON); 439 hctl = SDHC_READ(hmsc, SDHC_HOST_CTL); 440 if (width == 8) { 441 con |= CON_DW8; 442 } else if (width == 4) { 443 con &= ~CON_DW8; 444 hctl |= SDHC_4BIT_MODE; 445 } else { 446 con &= ~CON_DW8; 447 hctl &= ~SDHC_4BIT_MODE; 448 } 449 bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con); 450 SDHC_WRITE(hmsc, SDHC_HOST_CTL, hctl); 451 452 return 0; 453 } 454 455 static int 456 ti_sdhc_edma_init(struct ti_sdhc_softc *sc, u_int tx_chan, u_int rx_chan) 457 { 458 int i, error, rseg; 459 460 /* Request tx and rx DMA channels */ 461 sc->sc_edma_tx = edma_channel_alloc(EDMA_TYPE_DMA, tx_chan, 462 ti_sdhc_edma_done, sc); 463 KASSERT(sc->sc_edma_tx != NULL); 464 sc->sc_edma_rx = edma_channel_alloc(EDMA_TYPE_DMA, rx_chan, 465 ti_sdhc_edma_done, sc); 466 KASSERT(sc->sc_edma_rx != NULL); 467 468 /* Allocate some PaRAM pages */ 469 for (i = 0; i < __arraycount(sc->sc_edma_param_tx); i++) { 470 sc->sc_edma_param_tx[i] = edma_param_alloc(sc->sc_edma_tx); 471 KASSERT(sc->sc_edma_param_tx[i] != 0xffff); 472 } 473 for (i = 0; i < __arraycount(sc->sc_edma_param_rx); i++) { 474 sc->sc_edma_param_rx[i] = edma_param_alloc(sc->sc_edma_rx); 475 KASSERT(sc->sc_edma_param_rx[i] != 0xffff); 476 } 477 478 /* Setup bounce buffer */ 479 error = bus_dmamem_alloc(sc->sc.sc_dmat, MAXPHYS, 32, MAXPHYS, 480 sc->sc_edma_segs, 1, &rseg, BUS_DMA_WAITOK); 481 if (error) { 482 aprint_error_dev(sc->sc.sc_dev, 483 "couldn't allocate dmamem: %d\n", error); 484 return error; 485 } 486 KASSERT(rseg == 1); 487 error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_edma_segs, rseg, MAXPHYS, 488 &sc->sc_edma_bbuf, BUS_DMA_WAITOK); 489 if (error) { 490 aprint_error_dev(sc->sc.sc_dev, "couldn't map dmamem: %d\n", 491 error); 492 return error; 493 } 494 error = bus_dmamap_create(sc->sc.sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 495 BUS_DMA_WAITOK, &sc->sc_edma_dmamap); 496 if (error) { 497 aprint_error_dev(sc->sc.sc_dev, "couldn't create dmamap: %d\n", 498 error); 499 return error; 500 } 501 error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_edma_dmamap, 502 sc->sc_edma_bbuf, MAXPHYS, NULL, BUS_DMA_WAITOK); 503 if (error) { 504 device_printf(sc->sc.sc_dev, "couldn't load dmamap: %d\n", 505 error); 506 return error; 507 } 508 509 return error; 510 } 511 512 static int 513 ti_sdhc_edma_xfer_data(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 514 { 515 struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev); 516 const bus_dmamap_t map = cmd->c_dmamap; 517 bool bounce; 518 int error; 519 520 #if notyet 521 bounce = false; 522 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 523 if ((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) != 0 || 524 (cmd->c_dmamap->dm_segs[seg].ds_len & 3) != 0) { 525 bounce = true; 526 break; 527 } 528 } 529 #else 530 bounce = true; 531 #endif 532 533 if (bounce) { 534 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 535 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 536 MAXPHYS, BUS_DMASYNC_PREREAD); 537 } else { 538 memcpy(sc->sc_edma_bbuf, cmd->c_data, cmd->c_datalen); 539 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 540 MAXPHYS, BUS_DMASYNC_PREWRITE); 541 } 542 543 cmd->c_dmamap = sc->sc_edma_dmamap; 544 } 545 546 error = ti_sdhc_edma_transfer(sdhc_sc, cmd); 547 548 if (bounce) { 549 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 550 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 551 MAXPHYS, BUS_DMASYNC_POSTREAD); 552 } else { 553 bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0, 554 MAXPHYS, BUS_DMASYNC_POSTWRITE); 555 } 556 if (ISSET(cmd->c_flags, SCF_CMD_READ) && error == 0) { 557 memcpy(cmd->c_data, sc->sc_edma_bbuf, cmd->c_datalen); 558 } 559 560 cmd->c_dmamap = map; 561 } 562 563 return error; 564 } 565 566 static int 567 ti_sdhc_edma_transfer(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd) 568 { 569 struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev); 570 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 571 struct edma_channel *edma; 572 uint16_t *edma_param; 573 struct edma_param ep; 574 size_t seg; 575 int error, resid = cmd->c_datalen; 576 int blksize = MIN(cmd->c_datalen, cmd->c_blklen); 577 578 KASSERT(mutex_owned(plock)); 579 580 edma = ISSET(cmd->c_flags, SCF_CMD_READ) ? 581 sc->sc_edma_rx : sc->sc_edma_tx; 582 edma_param = ISSET(cmd->c_flags, SCF_CMD_READ) ? 583 sc->sc_edma_param_rx : sc->sc_edma_param_tx; 584 585 DPRINTF(1, (sc->sc.sc_dev, "edma xfer: nsegs=%d ch# %d\n", 586 cmd->c_dmamap->dm_nsegs, edma_channel_index(edma))); 587 588 if (cmd->c_dmamap->dm_nsegs > EDMA_MAX_PARAMS) { 589 return ENOMEM; 590 } 591 592 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 593 KASSERT(resid > 0); 594 const int xferlen = uimin(resid, 595 cmd->c_dmamap->dm_segs[seg].ds_len); 596 KASSERT(xferlen == cmd->c_dmamap->dm_segs[seg].ds_len || 597 seg == cmd->c_dmamap->dm_nsegs - 1); 598 resid -= xferlen; 599 KASSERT((xferlen & 0x3) == 0); 600 ep.ep_opt = __SHIFTIN(2, EDMA_PARAM_OPT_FWID) /* 32-bit */; 601 ep.ep_opt |= __SHIFTIN(edma_channel_index(edma), 602 EDMA_PARAM_OPT_TCC); 603 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 604 ep.ep_opt |= EDMA_PARAM_OPT_TCINTEN; 605 ep.ep_link = 0xffff; 606 } else { 607 ep.ep_link = EDMA_PARAM_BASE(edma_param[seg+1]); 608 } 609 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 610 ep.ep_opt |= EDMA_PARAM_OPT_SAM; 611 ep.ep_src = sc->sc_edma_fifo; 612 ep.ep_dst = cmd->c_dmamap->dm_segs[seg].ds_addr; 613 } else { 614 ep.ep_opt |= EDMA_PARAM_OPT_DAM; 615 ep.ep_src = cmd->c_dmamap->dm_segs[seg].ds_addr; 616 ep.ep_dst = sc->sc_edma_fifo; 617 } 618 619 KASSERT(xferlen <= 65536 * 4); 620 621 /* 622 * In constant addressing mode, the address must be aligned 623 * to 256-bits. 624 */ 625 KASSERT((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) == 0); 626 627 /* 628 * For unknown reason, the A-DMA transfers never completes for 629 * transfers larger than 64 butes. So use a AB transfer, 630 * with a 64 bytes A len 631 */ 632 ep.ep_bcntrld = 0; /* not used for AB-synchronous mode */ 633 ep.ep_opt |= EDMA_PARAM_OPT_SYNCDIM; 634 ep.ep_acnt = uimin(xferlen, 64); 635 ep.ep_bcnt = uimin(xferlen, blksize) / ep.ep_acnt; 636 ep.ep_ccnt = xferlen / (ep.ep_acnt * ep.ep_bcnt); 637 ep.ep_srcbidx = ep.ep_dstbidx = 0; 638 ep.ep_srccidx = ep.ep_dstcidx = 0; 639 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 640 ep.ep_dstbidx = ep.ep_acnt; 641 ep.ep_dstcidx = ep.ep_acnt * ep.ep_bcnt; 642 } else { 643 ep.ep_srcbidx = ep.ep_acnt; 644 ep.ep_srccidx = ep.ep_acnt * ep.ep_bcnt; 645 } 646 647 edma_set_param(edma, edma_param[seg], &ep); 648 #ifdef TISDHC_DEBUG 649 if (tisdhcdebug >= 1) { 650 printf("target OPT: %08x\n", ep.ep_opt); 651 edma_dump_param(edma, edma_param[seg]); 652 } 653 #endif 654 } 655 656 error = 0; 657 sc->sc_edma_pending = true; 658 edma_transfer_enable(edma, edma_param[0]); 659 while (sc->sc_edma_pending) { 660 error = cv_timedwait(&sc->sc_edma_cv, plock, hz*10); 661 if (error == EWOULDBLOCK) { 662 device_printf(sc->sc.sc_dev, "transfer timeout!\n"); 663 edma_dump(edma); 664 edma_dump_param(edma, edma_param[0]); 665 edma_halt(edma); 666 sc->sc_edma_pending = false; 667 error = ETIMEDOUT; 668 break; 669 } 670 } 671 edma_halt(edma); 672 673 return error; 674 } 675 676 static void 677 ti_sdhc_edma_done(void *priv) 678 { 679 struct ti_sdhc_softc *sc = priv; 680 kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]); 681 682 mutex_enter(plock); 683 KASSERT(sc->sc_edma_pending == true); 684 sc->sc_edma_pending = false; 685 cv_broadcast(&sc->sc_edma_cv); 686 mutex_exit(plock); 687 } 688
Indexes created Sun Oct 19 19:09:49 GMT 2025