vexpress_platform.c revision 1.14 
1/* $NetBSD: vexpress_platform.c,v 1.14 2019/01/31 13:16:31 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "opt_multiprocessor.h"
30#include "opt_console.h"
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.14 2019/01/31 13:16:31 skrll Exp $");
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/cpu.h>
38#include <sys/device.h>
39#include <sys/termios.h>
40
41#include <dev/fdt/fdtvar.h>
42
43#include <uvm/uvm_extern.h>
44
45#include <machine/bootconfig.h>
46#include <arm/cpufunc.h>
47
48#include <arm/fdt/arm_fdtvar.h>
49
50#include <arm/cortex/gtmr_var.h>
51
52#include <arm/cortex/gic_reg.h>
53
54#include <evbarm/dev/plcomreg.h>
55#include <evbarm/fdt/machdep.h>
56
57#include <arm/vexpress/vexpress_platform.h>
58
59#include <libfdt.h>
60
61#define	VEXPRESS_CLCD_NODE_PATH	\
62	"/smb@8000000/motherboard/iofpga@3,00000000/clcd@1f0000"
63#define	VEXPRESS_REF_FREQ	24000000
64
65extern struct bus_space armv7_generic_bs_tag;
66extern struct bus_space armv7_generic_a4x_bs_tag;
67extern struct arm32_bus_dma_tag arm_generic_dma_tag;
68
69#define	SYSREG_BASE		0x1c010000
70#define	SYSREG_SIZE		0x1000
71
72#define	SYS_FLAGS		0x0030
73#define	SYS_FLAGSCLR		0x0034
74#define	SYS_CFGDATA		0x00a0
75#define	SYS_CFGCTRL		0x00a4
76#define	 SYS_CFGCTRL_START	__BIT(31)
77#define	 SYS_CFGCTRL_WRITE	__BIT(30)
78#define	 SYS_CFGCTRL_DCC	__BITS(29,26)
79#define	 SYS_CFGCTRL_FUNCTION	__BITS(25,20)
80#define	  SYS_CFGCTRL_FUNCTION_SHUTDOWN	8
81#define	  SYS_CFGCTRL_FUNCTION_REBOOT	9
82#define	 SYS_CFGCTRL_SITE	__BITS(17,16)
83#define	 SYS_CFGCTRL_POSITION	__BITS(15,12)
84#define	 SYS_CFGCTRL_DEVICE	__BITS(11,0)
85#define	SYS_CFGSTAT		0x00a8
86#define	 SYS_CFGSTAT_ERROR	__BIT(1)
87#define	 SYS_CFGSTAT_COMPLETE	__BIT(0)
88
89static bus_space_tag_t sysreg_bst = &armv7_generic_bs_tag;
90static bus_space_handle_t sysreg_bsh;
91
92#define	SYSREG_WRITE(o, v)	\
93	bus_space_write_4(sysreg_bst, sysreg_bsh, (o), (v))
94
95void vexpress_platform_early_putchar(char);
96
97void
98vexpress_platform_early_putchar(char c)
99{
100#ifdef CONSADDR
101#define CONSADDR_VA ((CONSADDR - VEXPRESS_CORE_PBASE) + VEXPRESS_CORE_VBASE)
102	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
103	    (volatile uint32_t *)CONSADDR_VA :
104	    (volatile uint32_t *)CONSADDR;
105
106	while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0)
107		continue;
108
109	uartaddr[PL01XCOM_DR / 4] = htole32(c);
110	arm_dsb();
111
112	while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
113		continue;
114#endif
115}
116
117
118static int
119vexpress_a15_smp_init(void)
120{
121	int ret = 0;
122#ifdef MULTIPROCESSOR
123	bus_space_tag_t gicd_bst = &armv7_generic_bs_tag;
124	bus_space_handle_t gicd_bsh;
125	int started = 0;
126
127	/* Bitmask of CPUs (non-BSP) to start */
128	for (int i = 1; i < arm_cpu_max; i++)
129		started |= __BIT(i);
130
131	/* Write init vec to SYS_FLAGS register */
132	SYSREG_WRITE(SYS_FLAGSCLR, 0xffffffff);
133	SYSREG_WRITE(SYS_FLAGS, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
134
135	/* Map GIC distributor */
136	bus_space_map(gicd_bst, VEXPRESS_GIC_PBASE + GICD_BASE,
137	    0x1000, 0, &gicd_bsh);
138
139	/* Enable GIC distributor */
140	bus_space_write_4(gicd_bst, gicd_bsh,
141	    GICD_CTRL, GICD_CTRL_Enable);
142
143	/* Send sw interrupt to APs */
144	const uint32_t sgir = GICD_SGIR_TargetListFilter_NotMe;
145	bus_space_write_4(gicd_bst, gicd_bsh, GICD_SGIR, sgir);
146
147	/* Wait for APs to start */
148	u_int i;
149	for (i = 0x10000000; i > 0; i--) {
150		arm_dmb();
151		if (arm_cpu_hatched == started)
152			break;
153	}
154	if (i == 0) {
155		aprint_error("WARNING: AP failed to start\n");
156		ret++;
157	}
158
159	/* Disable GIC distributor */
160	bus_space_write_4(gicd_bst, gicd_bsh, GICD_CTRL, 0);
161#endif
162	return ret;
163}
164
165
166static const struct pmap_devmap *
167vexpress_platform_devmap(void)
168{
169	static const struct pmap_devmap devmap[] = {
170		DEVMAP_ENTRY(VEXPRESS_CORE_VBASE,
171			     VEXPRESS_CORE_PBASE,
172			     VEXPRESS_CORE_SIZE),
173		DEVMAP_ENTRY(VEXPRESS_GIC_VBASE,
174			     VEXPRESS_GIC_PBASE,
175			     VEXPRESS_GIC_SIZE),
176		DEVMAP_ENTRY_END
177	};
178
179	return devmap;
180}
181
182static void
183vexpress_platform_bootstrap(void)
184{
185	bus_space_map(sysreg_bst, SYSREG_BASE, SYSREG_SIZE, 0,
186	    &sysreg_bsh);
187
188#ifdef MULTIPROCESSOR
189	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
190#endif
191
192	if (match_bootconf_option(boot_args, "console", "fb")) {
193		void *fdt_data = __UNCONST(fdtbus_get_data());
194		const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
195		if (chosen_off >= 0)
196			fdt_setprop_string(fdt_data, chosen_off, "stdout-path",
197			    VEXPRESS_CLCD_NODE_PATH);
198	}
199}
200
201static void
202vexpress_platform_init_attach_args(struct fdt_attach_args *faa)
203{
204	faa->faa_bst = &armv7_generic_bs_tag;
205	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
206	faa->faa_dmat = &arm_generic_dma_tag;
207}
208
209static void
210vexpress_platform_device_register(device_t self, void *aux)
211{
212}
213
214static void
215vexpress_platform_reset(void)
216{
217	SYSREG_WRITE(SYS_CFGSTAT, 0);
218	SYSREG_WRITE(SYS_CFGDATA, 0);
219	SYSREG_WRITE(SYS_CFGCTRL,
220	    SYS_CFGCTRL_START |
221	    SYS_CFGCTRL_WRITE |
222	    __SHIFTIN(SYS_CFGCTRL_FUNCTION_REBOOT,
223		      SYS_CFGCTRL_FUNCTION));
224}
225
226static u_int
227vexpress_platform_uart_freq(void)
228{
229	return VEXPRESS_REF_FREQ;
230}
231
232static const struct arm_platform vexpress_platform = {
233	.ap_devmap = vexpress_platform_devmap,
234	.ap_bootstrap = vexpress_platform_bootstrap,
235	.ap_mpstart = vexpress_a15_smp_init,
236	.ap_init_attach_args = vexpress_platform_init_attach_args,
237	.ap_device_register = vexpress_platform_device_register,
238	.ap_reset = vexpress_platform_reset,
239	.ap_delay = gtmr_delay,
240	.ap_uart_freq = vexpress_platform_uart_freq,
241};
242
243ARM_PLATFORM(vexpress, "arm,vexpress", &vexpress_platform);
244