zynq7000_clkc.c revision 1.4
1 /* $NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/kmem.h> 40 41 #include <dev/clk/clk_backend.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/fdt/syscon.h> 45 46 #define ARM_PLL_CTRL 0x100 47 #define DDR_PLL_CTRL 0x104 48 #define IO_PLL_CTRL 0x108 49 #define PLL_FDIV __BITS(18,12) 50 #define ARM_CLK_CTRL 0x120 51 #define ARM_CLK_CTRL_CPU_1XCLKACT __BIT(27) 52 #define ARM_CLK_CTRL_CPU_2XCLKACT __BIT(26) 53 #define ARM_CLK_CTRL_CPU_3OR2XCLKACT __BIT(25) 54 #define ARM_CLK_CTRL_CPU_6OR4XCLKACT __BIT(24) 55 #define ARM_CLK_CTRL_DIVISOR __BITS(13,8) 56 #define APER_CLK_CTRL 0x12c 57 #define UART1_CPU_1XCLKACT __BIT(21) 58 #define UART0_CPU_1XCLKACT __BIT(20) 59 #define I2C1_CPU_1XCLKACT __BIT(19) 60 #define I2C0_CPU_1XCLKACT __BIT(18) 61 #define SDI1_CPU_1XCLKACT __BIT(11) 62 #define SDI0_CPU_1XCLKACT __BIT(10) 63 #define SDIO_CLK_CTRL 0x150 64 #define UART_CLK_CTRL 0x154 65 #define CLK_CTRL_DIVISOR __BITS(13,8) 66 #define CLK_CTRL_SRCSEL __BITS(5,4) 67 #define CLK_CTRL_CLKACT1 __BIT(1) 68 #define CLK_CTRL_CLKACT0 __BIT(0) 69 #define CLK_621_TRUE 0x1C4 70 #define CLK_621_TRUE_EN __BIT(0) 71 72 enum xynq7000_clkid { 73 clkid_armpll, 74 clkid_ddrpll, 75 clkid_iopll, 76 clkid_cpu_6or4x, 77 clkid_cpu_3or2x, 78 clkid_cpu_2x, 79 clkid_cpu_1x, 80 clkid_ddr2x, 81 clkid_ddr3x, 82 clkid_dci, 83 clkid_lqspi, 84 clkid_smc, 85 clkid_pcap, 86 clkid_gem0, 87 clkid_gem1, 88 clkid_fclk0, 89 clkid_fclk1, 90 clkid_fclk2, 91 clkid_fclk3, 92 clkid_can0, 93 clkid_can1, 94 clkid_sdio0, 95 clkid_sdio1, 96 clkid_uart0, 97 clkid_uart1, 98 clkid_spi0, 99 clkid_spi1, 100 clkid_dma, 101 clkid_usb0_aper, 102 clkid_usb1_aper, 103 clkid_gem0_aper, 104 clkid_gem1_aper, 105 clkid_sdio0_aper, 106 clkid_sdio1_aper, 107 clkid_spi0_aper, 108 clkid_spi1_aper, 109 clkid_can0_aper, 110 clkid_can1_aper, 111 clkid_i2c0_aper, 112 clkid_i2c1_aper, 113 clkid_uart0_aper, 114 clkid_uart1_aper, 115 clkid_gpio_aper, 116 clkid_lqspi_aper, 117 clkid_smc_aper, 118 clkid_swdt, 119 clkid_dbg_trc, 120 clkid_dbg_apb, 121 num_clkid 122 }; 123 CTASSERT(clkid_dbg_apb == 47); 124 125 static int zynq7000_clkc_match(device_t, cfdata_t, void *); 126 static void zynq7000_clkc_attach(device_t, device_t, void *); 127 128 static u_int zynq7000_clkc_clk_get_rate(void *, struct clk *); 129 130 static const struct device_compatible_entry compat_data[] = { 131 { .compat = "xlnx,ps7-clkc" }, 132 DEVICE_COMPAT_EOL 133 }; 134 135 struct zynq7000_clkc_softc { 136 device_t sc_dev; 137 struct clk_domain sc_clkdom; 138 struct clk sc_clk[num_clkid]; 139 140 u_int sc_ps_clk_frequency; 141 struct syscon *sc_syscon; 142 }; 143 144 CFATTACH_DECL_NEW(zynq7000_clkc, sizeof(struct zynq7000_clkc_softc), 145 zynq7000_clkc_match, zynq7000_clkc_attach, NULL, NULL); 146 147 static struct clk * 148 zynq7000_clkc_clk_get(void *priv, const char *name) 149 { 150 struct zynq7000_clkc_softc * const sc = priv; 151 u_int clkid; 152 153 for (clkid = 0; clkid < num_clkid; clkid++) { 154 if (strcmp(name, sc->sc_clk[clkid].name) == 0) { 155 return &sc->sc_clk[clkid]; 156 } 157 } 158 159 return NULL; 160 } 161 162 static void 163 zynq7000_clkc_clk_put(void *priv, struct clk *clk) 164 { 165 } 166 167 static u_int 168 zynq7000_clkc_get_rate_pll(struct zynq7000_clkc_softc *sc, 169 bus_addr_t reg) 170 { 171 uint32_t val; 172 173 syscon_lock(sc->sc_syscon); 174 val = syscon_read_4(sc->sc_syscon, reg); 175 syscon_unlock(sc->sc_syscon); 176 177 return sc->sc_ps_clk_frequency * __SHIFTOUT(val, PLL_FDIV); 178 } 179 180 static u_int 181 zynq7000_clkc_get_rate_iop(struct zynq7000_clkc_softc *sc, 182 bus_addr_t reg) 183 { 184 uint32_t val; 185 u_int prate, sel; 186 187 syscon_lock(sc->sc_syscon); 188 val = syscon_read_4(sc->sc_syscon, reg); 189 syscon_unlock(sc->sc_syscon); 190 191 sel = __SHIFTOUT(val, CLK_CTRL_SRCSEL); 192 if (sel == 2) { 193 prate = zynq7000_clkc_clk_get_rate(sc, 194 &sc->sc_clk[clkid_armpll]); 195 } else if (sel == 3) { 196 prate = zynq7000_clkc_clk_get_rate(sc, 197 &sc->sc_clk[clkid_ddrpll]); 198 } else { 199 prate = zynq7000_clkc_clk_get_rate(sc, 200 &sc->sc_clk[clkid_iopll]); 201 } 202 203 return prate / __SHIFTOUT(val, CLK_CTRL_DIVISOR); 204 } 205 206 static u_int 207 zynq7000_clkc_clk_get_rate(void *priv, struct clk *clk) 208 { 209 struct zynq7000_clkc_softc * const sc = priv; 210 uint32_t val; 211 u_int prate; 212 213 if (clk == &sc->sc_clk[clkid_armpll]) { 214 return zynq7000_clkc_get_rate_pll(sc, ARM_PLL_CTRL); 215 } else if (clk == &sc->sc_clk[clkid_iopll]) { 216 return zynq7000_clkc_get_rate_pll(sc, IO_PLL_CTRL); 217 } else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) { 218 prate = zynq7000_clkc_clk_get_rate(sc, 219 &sc->sc_clk[clkid_cpu_1x]); 220 syscon_lock(sc->sc_syscon); 221 val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE); 222 syscon_unlock(sc->sc_syscon); 223 return (val & CLK_621_TRUE_EN) != 0 ? 224 prate * 6 : prate * 4; 225 } else if (clk == &sc->sc_clk[clkid_cpu_3or2x]) { 226 prate = zynq7000_clkc_clk_get_rate(sc, 227 &sc->sc_clk[clkid_cpu_1x]); 228 syscon_lock(sc->sc_syscon); 229 val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE); 230 syscon_unlock(sc->sc_syscon); 231 return (val & CLK_621_TRUE_EN) != 0 ? 232 prate * 3 : prate * 2; 233 } else if (clk == &sc->sc_clk[clkid_cpu_2x]) { 234 prate = zynq7000_clkc_clk_get_rate(sc, 235 &sc->sc_clk[clkid_cpu_1x]); 236 return prate * 2; 237 } else if (clk == &sc->sc_clk[clkid_cpu_1x]) { 238 prate = zynq7000_clkc_clk_get_rate(sc, 239 &sc->sc_clk[clkid_armpll]); 240 syscon_lock(sc->sc_syscon); 241 val = syscon_read_4(sc->sc_syscon, ARM_CLK_CTRL); 242 syscon_unlock(sc->sc_syscon); 243 return prate / __SHIFTOUT(val, ARM_CLK_CTRL_DIVISOR) / 6; 244 } else if (clk == &sc->sc_clk[clkid_sdio0] || 245 clk == &sc->sc_clk[clkid_sdio1]) { 246 return zynq7000_clkc_get_rate_iop(sc, SDIO_CLK_CTRL); 247 } else if (clk == &sc->sc_clk[clkid_uart0] || 248 clk == &sc->sc_clk[clkid_uart1]) { 249 return zynq7000_clkc_get_rate_iop(sc, UART_CLK_CTRL); 250 } else if (clk == &sc->sc_clk[clkid_uart0_aper] || 251 clk == &sc->sc_clk[clkid_uart1_aper] || 252 clk == &sc->sc_clk[clkid_i2c0_aper] || 253 clk == &sc->sc_clk[clkid_i2c1_aper]) { 254 return zynq7000_clkc_clk_get_rate(sc, 255 &sc->sc_clk[clkid_cpu_1x]); 256 } else { 257 /* Not implemented. */ 258 return 0; 259 } 260 } 261 262 static int 263 zynq7000_clkc_clk_enable(void *priv, struct clk *clk) 264 { 265 struct zynq7000_clkc_softc * const sc = priv; 266 uint32_t val, mask; 267 bus_addr_t reg; 268 269 if (clk == &sc->sc_clk[clkid_cpu_1x]) { 270 reg = ARM_CLK_CTRL; 271 mask = ARM_CLK_CTRL_CPU_1XCLKACT; 272 } else if (clk == &sc->sc_clk[clkid_cpu_2x]) { 273 reg = ARM_CLK_CTRL; 274 mask = ARM_CLK_CTRL_CPU_2XCLKACT; 275 } else if (clk == &sc->sc_clk[clkid_cpu_3or2x]) { 276 reg = ARM_CLK_CTRL; 277 mask = ARM_CLK_CTRL_CPU_3OR2XCLKACT; 278 } else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) { 279 reg = ARM_CLK_CTRL; 280 mask = ARM_CLK_CTRL_CPU_6OR4XCLKACT; 281 } else if (clk == &sc->sc_clk[clkid_sdio0]) { 282 reg = SDIO_CLK_CTRL; 283 mask = CLK_CTRL_CLKACT0; 284 } else if (clk == &sc->sc_clk[clkid_sdio1]) { 285 reg = SDIO_CLK_CTRL; 286 mask = CLK_CTRL_CLKACT1; 287 } else if (clk == &sc->sc_clk[clkid_uart0]) { 288 reg = UART_CLK_CTRL; 289 mask = CLK_CTRL_CLKACT0; 290 } else if (clk == &sc->sc_clk[clkid_uart1]) { 291 reg = UART_CLK_CTRL; 292 mask = CLK_CTRL_CLKACT1; 293 } else if (clk == &sc->sc_clk[clkid_sdio0_aper]) { 294 reg = APER_CLK_CTRL; 295 mask = SDI0_CPU_1XCLKACT; 296 } else if (clk == &sc->sc_clk[clkid_sdio1_aper]) { 297 reg = APER_CLK_CTRL; 298 mask = SDI1_CPU_1XCLKACT; 299 } else if (clk == &sc->sc_clk[clkid_uart0_aper]) { 300 reg = APER_CLK_CTRL; 301 mask = UART0_CPU_1XCLKACT; 302 } else if (clk == &sc->sc_clk[clkid_uart1_aper]) { 303 reg = APER_CLK_CTRL; 304 mask = UART1_CPU_1XCLKACT; 305 } else if (clk == &sc->sc_clk[clkid_i2c0_aper]) { 306 reg = APER_CLK_CTRL; 307 mask = I2C0_CPU_1XCLKACT; 308 } else if (clk == &sc->sc_clk[clkid_i2c1_aper]) { 309 reg = APER_CLK_CTRL; 310 mask = I2C1_CPU_1XCLKACT; 311 } else { 312 return ENXIO; 313 } 314 315 syscon_lock(sc->sc_syscon); 316 val = syscon_read_4(sc->sc_syscon, reg); 317 syscon_write_4(sc->sc_syscon, reg, val | mask); 318 syscon_unlock(sc->sc_syscon); 319 320 return 0; 321 } 322 323 static int 324 zynq7000_clkc_clk_disable(void *priv, struct clk *clk) 325 { 326 return ENXIO; 327 } 328 329 static const struct clk_funcs zynq7000_clkc_clk_funcs = { 330 .get = zynq7000_clkc_clk_get, 331 .put = zynq7000_clkc_clk_put, 332 .get_rate = zynq7000_clkc_clk_get_rate, 333 .enable = zynq7000_clkc_clk_enable, 334 .disable = zynq7000_clkc_clk_disable, 335 }; 336 337 static struct clk * 338 zynq7000_clkc_fdt_decode(device_t dev, int cc_phandle, const void *data, size_t len) 339 { 340 struct zynq7000_clkc_softc * const sc = device_private(dev); 341 u_int clkid; 342 343 if (len != 4) { 344 return NULL; 345 } 346 347 clkid = be32dec(data); 348 if (clkid >= num_clkid) { 349 return NULL; 350 } 351 352 return &sc->sc_clk[clkid]; 353 } 354 355 static const struct fdtbus_clock_controller_func zynq7000_clkc_fdt_funcs = { 356 .decode = zynq7000_clkc_fdt_decode 357 }; 358 359 static int 360 zynq7000_clkc_match(device_t parent, cfdata_t cf, void *aux) 361 { 362 struct fdt_attach_args * const faa = aux; 363 364 return of_compatible_match(faa->faa_phandle, compat_data); 365 } 366 367 static void 368 zynq7000_clkc_attach(device_t parent, device_t self, void *aux) 369 { 370 struct zynq7000_clkc_softc * const sc = device_private(self); 371 struct fdt_attach_args * const faa = aux; 372 const int phandle = faa->faa_phandle; 373 const char *clkname; 374 bus_addr_t addr; 375 bus_size_t size; 376 u_int clkid; 377 int error; 378 379 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 380 aprint_error(": couldn't get registers\n"); 381 return; 382 } 383 384 sc->sc_dev = self; 385 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle)); 386 if (sc->sc_syscon == NULL) { 387 aprint_error(": couldn't get syscon registers\n"); 388 return; 389 } 390 391 error = of_getprop_uint32(phandle, "ps-clk-frequency", 392 &sc->sc_ps_clk_frequency); 393 if (error != 0) { 394 aprint_error(": couldn't get ps-clk-frequency\n"); 395 return; 396 } 397 398 sc->sc_clkdom.name = device_xname(self); 399 sc->sc_clkdom.funcs = &zynq7000_clkc_clk_funcs; 400 sc->sc_clkdom.priv = sc; 401 for (clkid = 0; clkid < num_clkid; clkid++) { 402 clkname = fdtbus_get_string_index(phandle, 403 "clock-output-names", clkid); 404 sc->sc_clk[clkid].domain = &sc->sc_clkdom; 405 if (clkname != NULL) { 406 sc->sc_clk[clkid].name = kmem_asprintf("%s", clkname); 407 } 408 clk_attach(&sc->sc_clk[clkid]); 409 } 410 411 aprint_naive("\n"); 412 aprint_normal(": Zynq-7000 PS clock subsystem (PS_CLK %u Hz)\n", 413 sc->sc_ps_clk_frequency); 414 415 for (clkid = 0; clkid < num_clkid; clkid++) { 416 aprint_debug_dev(self, "clkid %u [%s]: %u Hz\n", clkid, 417 sc->sc_clk[clkid].name ? sc->sc_clk[clkid].name : "<none>", 418 clk_get_rate(&sc->sc_clk[clkid])); 419 } 420 421 fdtbus_register_clock_controller(self, phandle, &zynq7000_clkc_fdt_funcs); 422 } 423
Indexes created Thu Oct 02 14:10:14 GMT 2025