zynq_uart.c revision 1.2.10.1
1 /* $NetBSD: zynq_uart.c,v 1.2.10.1 2020/12/14 14:37:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho, Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in Zynq-7000. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.2.10.1 2020/12/14 14:37:50 thorpej Exp $"); 100 101 #include "opt_soc.h" 102 #include "opt_console.h" 103 #include "opt_com.h" 104 #include "opt_ddb.h" 105 #include "opt_kgdb.h" 106 #include "opt_ntp.h" 107 108 /* 109 * Override cnmagic(9) macro before including <sys/systm.h>. 110 * We need to know if cn_check_magic triggered debugger, so set a flag. 111 * Callers of cn_check_magic must declare int cn_trapped = 0; 112 * XXX: this is *ugly*! 113 */ 114 #define cn_trap() \ 115 do { \ 116 console_debugger(); \ 117 cn_trapped = 1; \ 118 } while (/* CONSTCOND */ 0) 119 120 #include <sys/param.h> 121 122 #include <sys/bus.h> 123 #include <sys/conf.h> 124 #include <dev/cons.h> 125 #include <sys/device.h> 126 #include <sys/file.h> 127 #include <sys/kauth.h> 128 #include <sys/kernel.h> 129 #include <sys/kmem.h> 130 #include <sys/poll.h> 131 #include <sys/proc.h> 132 #include <sys/systm.h> 133 #include <sys/tty.h> 134 135 #ifdef RND_COM 136 #include <sys/rndsource.h> 137 #endif 138 139 #include <arm/xilinx/zynq_uartreg.h> 140 #include <arm/xilinx/zynq_uartvar.h> 141 142 #ifndef ZYNQUART_RING_SIZE 143 #define ZYNQUART_RING_SIZE 2048 144 #endif 145 146 #define UART_SIZE 0x00000048 147 148 typedef struct zynquart_softc { 149 device_t sc_dev; 150 151 struct zynquart_regs { 152 bus_space_tag_t ur_iot; 153 bus_space_handle_t ur_ioh; 154 bus_addr_t ur_iobase; 155 } sc_regs; 156 157 #define sc_bt sc_regs.ur_iot 158 #define sc_bh sc_regs.ur_ioh 159 160 uint32_t sc_intrspec_enb; 161 uint32_t sc_cr; 162 uint32_t sc_mcr; 163 uint32_t sc_msr; 164 165 uint sc_init_cnt; 166 167 bus_addr_t sc_addr; 168 bus_size_t sc_size; 169 170 u_char sc_hwflags; 171 /* Hardware flag masks */ 172 #define ZYNQUART_HW_FLOW __BIT(0) 173 #define ZYNQUART_HW_DEV_OK __BIT(1) 174 #define ZYNQUART_HW_CONSOLE __BIT(2) 175 #define ZYNQUART_HW_KGDB __BIT(3) 176 177 bool enabled; 178 179 u_char sc_swflags; 180 181 u_char sc_rx_flags; 182 #define ZYNQUART_RX_TTY_BLOCKED __BIT(0) 183 #define ZYNQUART_RX_TTY_OVERFLOWED __BIT(1) 184 #define ZYNQUART_RX_IBUF_BLOCKED __BIT(2) 185 #define ZYNQUART_RX_IBUF_OVERFLOWED __BIT(3) 186 #define ZYNQUART_RX_ANY_BLOCK \ 187 (ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_TTY_OVERFLOWED| \ 188 ZYNQUART_RX_IBUF_BLOCKED|ZYNQUART_RX_IBUF_OVERFLOWED) 189 190 bool sc_tx_busy, sc_tx_done, sc_tx_stopped; 191 bool sc_rx_ready,sc_st_check; 192 u_short sc_txfifo_len, sc_txfifo_thresh; 193 194 uint16_t *sc_rbuf; 195 u_int sc_rbuf_size; 196 u_int sc_rbuf_in; 197 u_int sc_rbuf_out; 198 #define ZYNQUART_RBUF_AVAIL(sc) \ 199 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \ 200 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \ 201 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in))) 202 203 #define ZYNQUART_RBUF_SPACE(sc) \ 204 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \ 205 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \ 206 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1) 207 /* increment ringbuffer pointer */ 208 #define ZYNQUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1)) 209 u_int sc_r_lowat; 210 u_int sc_r_hiwat; 211 212 /* output chunk */ 213 u_char *sc_tba; 214 u_int sc_tbc; 215 u_int sc_heldtbc; 216 /* pending parameter changes */ 217 u_char sc_pending; 218 #define ZYNQUART_PEND_PARAM __BIT(0) 219 #define ZYNQUART_PEND_SPEED __BIT(1) 220 221 222 struct callout sc_diag_callout; 223 kmutex_t sc_lock; 224 void *sc_ih; /* interrupt handler */ 225 void *sc_si; /* soft interrupt */ 226 struct tty *sc_tty; 227 228 /* power management hooks */ 229 int (*enable)(struct zynquart_softc *); 230 void (*disable)(struct zynquart_softc *); 231 232 struct { 233 ulong err; 234 ulong brk; 235 ulong prerr; 236 ulong frmerr; 237 ulong ovrrun; 238 } sc_errors; 239 240 struct zynquart_baudrate_ratio { 241 uint16_t numerator; /* UBIR */ 242 uint16_t modulator; /* UBMR */ 243 } sc_ratio; 244 245 } zynquart_softc_t; 246 247 248 int zynquartspeed(long, struct zynquart_baudrate_ratio *); 249 int zynquartparam(struct tty *, struct termios *); 250 void zynquartstart(struct tty *); 251 int zynquarthwiflow(struct tty *, int); 252 253 void zynquart_shutdown(struct zynquart_softc *); 254 void zynquart_loadchannelregs(struct zynquart_softc *); 255 void zynquart_hwiflow(struct zynquart_softc *); 256 void zynquart_break(struct zynquart_softc *, bool); 257 void zynquart_modem(struct zynquart_softc *, int); 258 void tiocm_to_zynquart(struct zynquart_softc *, u_long, int); 259 int zynquart_to_tiocm(struct zynquart_softc *); 260 void zynquart_iflush(struct zynquart_softc *); 261 262 int zynquart_common_getc(dev_t, struct zynquart_regs *); 263 void zynquart_common_putc(dev_t, struct zynquart_regs *, int); 264 265 266 int zynquart_init(struct zynquart_regs *, int, tcflag_t); 267 268 int zynquartcngetc(dev_t); 269 void zynquartcnputc(dev_t, int); 270 271 static void zynquartintr_read(struct zynquart_softc *); 272 static void zynquartintr_send(struct zynquart_softc *); 273 274 static void zynquart_enable_debugport(struct zynquart_softc *); 275 static void zynquart_disable_all_interrupts(struct zynquart_softc *); 276 static void zynquart_control_rxint(struct zynquart_softc *, bool); 277 static void zynquart_control_txint(struct zynquart_softc *, bool); 278 279 static uint32_t cflag_to_zynquart(tcflag_t, uint32_t); 280 281 #define integrate static inline 282 void zynquartsoft(void *); 283 integrate void zynquart_rxsoft(struct zynquart_softc *, struct tty *); 284 integrate void zynquart_txsoft(struct zynquart_softc *, struct tty *); 285 integrate void zynquart_stsoft(struct zynquart_softc *, struct tty *); 286 integrate void zynquart_schedrx(struct zynquart_softc *); 287 void zynquartdiag(void *); 288 static void zynquart_load_speed(struct zynquart_softc *); 289 static void zynquart_load_params(struct zynquart_softc *); 290 integrate void zynquart_load_pendings(struct zynquart_softc *); 291 292 293 extern struct cfdriver zynquart_cd; 294 295 dev_type_open(zynquartopen); 296 dev_type_close(zynquartclose); 297 dev_type_read(zynquartread); 298 dev_type_write(zynquartwrite); 299 dev_type_ioctl(zynquartioctl); 300 dev_type_stop(zynquartstop); 301 dev_type_tty(zynquarttty); 302 dev_type_poll(zynquartpoll); 303 304 const struct cdevsw zynquart_cdevsw = { 305 .d_open = zynquartopen, 306 .d_close = zynquartclose, 307 .d_read = zynquartread, 308 .d_write = zynquartwrite, 309 .d_ioctl = zynquartioctl, 310 .d_stop = zynquartstop, 311 .d_tty = zynquarttty, 312 .d_poll = zynquartpoll, 313 .d_mmap = nommap, 314 .d_kqfilter = ttykqfilter, 315 .d_discard = nodiscard, 316 .d_flag = D_TTY 317 }; 318 319 /* 320 * Make this an option variable one can patch. 321 * But be warned: this must be a power of 2! 322 */ 323 u_int zynquart_rbuf_size = ZYNQUART_RING_SIZE; 324 325 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 326 u_int zynquart_rbuf_hiwat = (ZYNQUART_RING_SIZE * 1) / 4; 327 u_int zynquart_rbuf_lowat = (ZYNQUART_RING_SIZE * 3) / 4; 328 329 static struct zynquart_regs zynquartconsregs; 330 static int zynquartconsattached; 331 static int zynquartconsrate; 332 static tcflag_t zynquartconscflag; 333 static struct cnm_state zynquart_cnm_state; 334 335 u_int zynquart_freq; 336 u_int zynquart_freqdiv; 337 338 #ifdef KGDB 339 #include <sys/kgdb.h> 340 341 static struct zynquart_regs zynquart_kgdb_regs; 342 static int zynquart_kgdb_attached; 343 344 int zynquart_kgdb_getc(void *); 345 void zynquart_kgdb_putc(void *, int); 346 #endif /* KGDB */ 347 348 #define ZYNQUART_UNIT_MASK 0x7ffff 349 #define ZYNQUART_DIALOUT_MASK 0x80000 350 351 #define ZYNQUART_UNIT(x) (minor(x) & ZYNQUART_UNIT_MASK) 352 #define ZYNQUART_DIALOUT(x) (minor(x) & ZYNQUART_DIALOUT_MASK) 353 354 #define ZYNQUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 355 device_is_active((sc)->sc_dev)) 356 357 #define BR BUS_SPACE_BARRIER_READ 358 #define BW BUS_SPACE_BARRIER_WRITE 359 #define ZYNQUART_BARRIER(r, f) \ 360 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, UART_SIZE, (f)) 361 362 CFATTACH_DECL_NEW(zynquart, sizeof(struct zynquart_softc), 363 zynquart_match, zynquart_attach, NULL, NULL); 364 365 void 366 zynquart_attach_common(device_t parent, device_t self, 367 bus_space_tag_t iot, paddr_t iobase, size_t size, int flags) 368 { 369 zynquart_softc_t *sc = device_private(self); 370 struct zynquart_regs *regsp = &sc->sc_regs; 371 struct tty *tp; 372 bus_space_handle_t ioh; 373 374 aprint_naive("\n"); 375 aprint_normal("\n"); 376 377 sc->sc_dev = self; 378 379 if (size <= 0) 380 size = UART_SIZE; 381 382 regsp->ur_iot = iot; 383 regsp->ur_iobase = iobase; 384 385 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 386 return; 387 } 388 regsp->ur_ioh = ioh; 389 390 callout_init(&sc->sc_diag_callout, 0); 391 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 392 393 sc->sc_cr = bus_space_read_4(iot, ioh, UART_CONTROL); 394 sc->sc_cr |= CR_TXEN | CR_RXEN; 395 sc->sc_cr &= ~(CR_TXDIS | CR_RXDIS); 396 bus_space_write_4(iot, ioh, UART_CONTROL, sc->sc_cr); 397 398 /* Disable interrupts before configuring the device. */ 399 zynquart_disable_all_interrupts(sc); 400 401 if (regsp->ur_iobase == zynquartconsregs.ur_iobase) { 402 zynquartconsattached = 1; 403 404 /* Make sure the console is always "hardwired". */ 405 SET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE); 406 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 407 } 408 409 tp = tty_alloc(); 410 tp->t_oproc = zynquartstart; 411 tp->t_param = zynquartparam; 412 tp->t_hwiflow = zynquarthwiflow; 413 414 sc->sc_tty = tp; 415 sc->sc_rbuf = kmem_alloc(sizeof (*sc->sc_rbuf) * zynquart_rbuf_size, 416 KM_SLEEP); 417 sc->sc_rbuf_size = zynquart_rbuf_size; 418 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 419 sc->sc_txfifo_len = 64; 420 sc->sc_txfifo_thresh = 32; 421 422 tty_attach(tp); 423 424 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) { 425 int maj; 426 427 /* locate the major number */ 428 maj = cdevsw_lookup_major(&zynquart_cdevsw); 429 430 if (maj != NODEVMAJOR) { 431 tp->t_dev = cn_tab->cn_dev = makedev(maj, 432 device_unit(sc->sc_dev)); 433 434 aprint_normal_dev(sc->sc_dev, "console\n"); 435 } 436 } 437 438 /* reset receive time out */ 439 bus_space_write_4(iot, ioh, UART_RCVR_TIMEOUT, 0); 440 bus_space_write_4(iot, ioh, UART_RCVR_FIFO_TRIGGER, 1); 441 442 #ifdef KGDB 443 /* 444 * Allow kgdb to "take over" this port. If this is 445 * not the console and is the kgdb device, it has 446 * exclusive use. If it's the console _and_ the 447 * kgdb device, it doesn't. 448 */ 449 if (regsp->ur_iobase == zynquart_kgdb_regs.ur_iobase) { 450 if (!ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) { 451 zynquart_kgdb_attached = 1; 452 453 SET(sc->sc_hwflags, ZYNQUART_HW_KGDB); 454 } 455 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 456 } 457 #endif 458 459 sc->sc_si = softint_establish(SOFTINT_SERIAL, zynquartsoft, sc); 460 461 #ifdef RND_COM 462 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 463 RND_TYPE_TTY, 0); 464 #endif 465 466 /* if there are no enable/disable functions, assume the device 467 is always enabled */ 468 if (!sc->enable) 469 sc->enabled = 1; 470 471 zynquart_enable_debugport(sc); 472 473 SET(sc->sc_hwflags, ZYNQUART_HW_DEV_OK); 474 } 475 476 int 477 zynquartspeed(long speed, struct zynquart_baudrate_ratio *ratio) 478 { 479 return 0; 480 } 481 482 #ifdef ZYNQUART_DEBUG 483 int zynquart_debug = 0; 484 485 void zynquartstatus(struct zynquart_softc *, const char *); 486 void 487 zynquartstatus(struct zynquart_softc *sc, const char *str) 488 { 489 struct tty *tp = sc->sc_tty; 490 491 aprint_normal_dev(sc->sc_dev, 492 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 493 str, 494 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 495 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 496 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 497 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 498 sc->sc_tx_stopped ? '+' : '-'); 499 500 aprint_normal_dev(sc->sc_dev, 501 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 502 str, 503 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 504 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 505 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 506 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 507 sc->sc_rx_flags); 508 } 509 #endif 510 511 #if 0 512 int 513 zynquart_detach(device_t self, int flags) 514 { 515 struct zynquart_softc *sc = device_private(self); 516 int maj, mn; 517 518 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) 519 return EBUSY; 520 521 /* locate the major number */ 522 maj = cdevsw_lookup_major(&zynquart_cdevsw); 523 524 /* Nuke the vnodes for any open instances. */ 525 mn = device_unit(self); 526 vdevgone(maj, mn, mn, VCHR); 527 528 mn |= ZYNQUART_DIALOUT_MASK; 529 vdevgone(maj, mn, mn, VCHR); 530 531 if (sc->sc_rbuf == NULL) { 532 /* 533 * Ring buffer allocation failed in the zynquart_attach_subr, 534 * only the tty is allocated, and nothing else. 535 */ 536 tty_free(sc->sc_tty); 537 return 0; 538 } 539 540 /* Free the receive buffer. */ 541 kmem_free(sc->sc_rbuf, sizeof(*sc->sc_rbuf) * sc->sc_rbuf_size); 542 543 /* Detach and free the tty. */ 544 tty_detach(sc->sc_tty); 545 tty_free(sc->sc_tty); 546 547 /* Unhook the soft interrupt handler. */ 548 softint_disestablish(sc->sc_si); 549 550 #ifdef RND_COM 551 /* Unhook the entropy source. */ 552 rnd_detach_source(&sc->rnd_source); 553 #endif 554 callout_destroy(&sc->sc_diag_callout); 555 556 /* Destroy the lock. */ 557 mutex_destroy(&sc->sc_lock); 558 559 return (0); 560 } 561 #endif 562 563 #ifdef notyet 564 int 565 zynquart_activate(device_t self, enum devact act) 566 { 567 struct zynquart_softc *sc = device_private(self); 568 int rv = 0; 569 570 switch (act) { 571 case DVACT_ACTIVATE: 572 rv = EOPNOTSUPP; 573 break; 574 575 case DVACT_DEACTIVATE: 576 if (sc->sc_hwflags & (ZYNQUART_HW_CONSOLE|ZYNQUART_HW_KGDB)) { 577 rv = EBUSY; 578 break; 579 } 580 581 if (sc->disable != NULL && sc->enabled != 0) { 582 (*sc->disable)(sc); 583 sc->enabled = 0; 584 } 585 break; 586 } 587 588 return (rv); 589 } 590 #endif 591 592 void 593 zynquart_shutdown(struct zynquart_softc *sc) 594 { 595 struct tty *tp = sc->sc_tty; 596 597 mutex_spin_enter(&sc->sc_lock); 598 599 /* If we were asserting flow control, then deassert it. */ 600 SET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED); 601 zynquart_hwiflow(sc); 602 603 /* Clear any break condition set with TIOCSBRK. */ 604 zynquart_break(sc, false); 605 606 /* 607 * Hang up if necessary. Wait a bit, so the other side has time to 608 * notice even if we immediately open the port again. 609 * Avoid tsleeping above splhigh(). 610 */ 611 if (ISSET(tp->t_cflag, HUPCL)) { 612 zynquart_modem(sc, 0); 613 mutex_spin_exit(&sc->sc_lock); 614 /* XXX will only timeout */ 615 (void) kpause(ttclos, false, hz, NULL); 616 mutex_spin_enter(&sc->sc_lock); 617 } 618 619 /* Turn off interrupts. */ 620 zynquart_disable_all_interrupts(sc); 621 /* re-enable recv interrupt for console or kgdb port */ 622 zynquart_enable_debugport(sc); 623 624 mutex_spin_exit(&sc->sc_lock); 625 626 #ifdef notyet 627 if (sc->disable) { 628 #ifdef DIAGNOSTIC 629 if (!sc->enabled) 630 panic("zynquart_shutdown: not enabled?"); 631 #endif 632 (*sc->disable)(sc); 633 sc->enabled = 0; 634 } 635 #endif 636 } 637 638 int 639 zynquartopen(dev_t dev, int flag, int mode, struct lwp *l) 640 { 641 struct zynquart_softc *sc; 642 struct tty *tp; 643 int s; 644 int error; 645 646 sc = device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 647 if (sc == NULL || !ISSET(sc->sc_hwflags, ZYNQUART_HW_DEV_OK) || 648 sc->sc_rbuf == NULL) 649 return (ENXIO); 650 651 if (!device_is_active(sc->sc_dev)) 652 return (ENXIO); 653 654 #ifdef KGDB 655 /* 656 * If this is the kgdb port, no other use is permitted. 657 */ 658 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_KGDB)) 659 return (EBUSY); 660 #endif 661 662 tp = sc->sc_tty; 663 664 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 665 return (EBUSY); 666 667 s = spltty(); 668 669 /* 670 * Do the following iff this is a first open. 671 */ 672 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 673 struct termios t; 674 675 tp->t_dev = dev; 676 677 678 #ifdef notyet 679 if (sc->enable) { 680 if ((*sc->enable)(sc)) { 681 splx(s); 682 aprint_error_dev(sc->sc_dev, 683 "device enable failed\n"); 684 return (EIO); 685 } 686 sc->enabled = 1; 687 } 688 #endif 689 690 mutex_spin_enter(&sc->sc_lock); 691 692 zynquart_disable_all_interrupts(sc); 693 694 /* Fetch the current modem control status, needed later. */ 695 696 #ifdef ZYNQUART_PPS 697 /* Clear PPS capture state on first open. */ 698 mutex_spin_enter(&timecounter_lock); 699 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 700 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 701 pps_init(&sc->sc_pps_state); 702 mutex_spin_exit(&timecounter_lock); 703 #endif 704 705 mutex_spin_exit(&sc->sc_lock); 706 707 /* 708 * Initialize the termios status to the defaults. Add in the 709 * sticky bits from TIOCSFLAGS. 710 */ 711 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) { 712 t.c_ospeed = zynquartconsrate; 713 t.c_cflag = zynquartconscflag; 714 } else { 715 t.c_ospeed = TTYDEF_SPEED; 716 t.c_cflag = TTYDEF_CFLAG; 717 } 718 t.c_ispeed = t.c_ospeed; 719 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 720 SET(t.c_cflag, CLOCAL); 721 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 722 SET(t.c_cflag, CRTSCTS); 723 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 724 SET(t.c_cflag, MDMBUF); 725 /* Make sure zynquartparam() will do something. */ 726 tp->t_ospeed = 0; 727 (void) zynquartparam(tp, &t); 728 tp->t_iflag = TTYDEF_IFLAG; 729 tp->t_oflag = TTYDEF_OFLAG; 730 tp->t_lflag = TTYDEF_LFLAG; 731 ttychars(tp); 732 ttsetwater(tp); 733 734 mutex_spin_enter(&sc->sc_lock); 735 736 /* 737 * Turn on DTR. We must always do this, even if carrier is not 738 * present, because otherwise we'd have to use TIOCSDTR 739 * immediately after setting CLOCAL, which applications do not 740 * expect. We always assert DTR while the device is open 741 * unless explicitly requested to deassert it. 742 */ 743 zynquart_modem(sc, 1); 744 745 /* Clear the input ring, and unblock. */ 746 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 747 zynquart_iflush(sc); 748 CLR(sc->sc_rx_flags, ZYNQUART_RX_ANY_BLOCK); 749 zynquart_hwiflow(sc); 750 751 /* Turn on interrupts. */ 752 zynquart_control_rxint(sc, true); 753 754 #ifdef ZYNQUART_DEBUG 755 if (zynquart_debug) 756 zynquartstatus(sc, "zynquartopen "); 757 #endif 758 759 mutex_spin_exit(&sc->sc_lock); 760 } 761 762 splx(s); 763 764 #if 0 765 error = ttyopen(tp, ZYNQUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 766 #else 767 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 768 #endif 769 if (error) 770 goto bad; 771 772 error = (*tp->t_linesw->l_open)(dev, tp); 773 if (error) 774 goto bad; 775 776 return (0); 777 778 bad: 779 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 780 /* 781 * We failed to open the device, and nobody else had it opened. 782 * Clean up the state as appropriate. 783 */ 784 zynquart_shutdown(sc); 785 } 786 787 return (error); 788 } 789 790 int 791 zynquartclose(dev_t dev, int flag, int mode, struct lwp *l) 792 { 793 struct zynquart_softc *sc = 794 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 795 struct tty *tp = sc->sc_tty; 796 797 /* XXX This is for cons.c. */ 798 if (!ISSET(tp->t_state, TS_ISOPEN)) 799 return (0); 800 801 (*tp->t_linesw->l_close)(tp, flag); 802 ttyclose(tp); 803 804 if (ZYNQUART_ISALIVE(sc) == 0) 805 return (0); 806 807 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 808 /* 809 * Although we got a last close, the device may still be in 810 * use; e.g. if this was the dialout node, and there are still 811 * processes waiting for carrier on the non-dialout node. 812 */ 813 zynquart_shutdown(sc); 814 } 815 816 return (0); 817 } 818 819 int 820 zynquartread(dev_t dev, struct uio *uio, int flag) 821 { 822 struct zynquart_softc *sc = 823 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 824 struct tty *tp = sc->sc_tty; 825 826 if (ZYNQUART_ISALIVE(sc) == 0) 827 return (EIO); 828 829 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 830 } 831 832 int 833 zynquartwrite(dev_t dev, struct uio *uio, int flag) 834 { 835 struct zynquart_softc *sc = 836 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 837 struct tty *tp = sc->sc_tty; 838 839 if (ZYNQUART_ISALIVE(sc) == 0) 840 return (EIO); 841 842 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 843 } 844 845 int 846 zynquartpoll(dev_t dev, int events, struct lwp *l) 847 { 848 struct zynquart_softc *sc = 849 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 850 struct tty *tp = sc->sc_tty; 851 852 if (ZYNQUART_ISALIVE(sc) == 0) 853 return (POLLHUP); 854 855 return ((*tp->t_linesw->l_poll)(tp, events, l)); 856 } 857 858 struct tty * 859 zynquarttty(dev_t dev) 860 { 861 struct zynquart_softc *sc = 862 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 863 struct tty *tp = sc->sc_tty; 864 865 return (tp); 866 } 867 868 int 869 zynquartioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 870 { 871 struct zynquart_softc *sc; 872 struct tty *tp; 873 int error; 874 875 sc = device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev)); 876 if (sc == NULL) 877 return ENXIO; 878 if (ZYNQUART_ISALIVE(sc) == 0) 879 return (EIO); 880 881 tp = sc->sc_tty; 882 883 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 884 if (error != EPASSTHROUGH) 885 return (error); 886 887 error = ttioctl(tp, cmd, data, flag, l); 888 if (error != EPASSTHROUGH) 889 return (error); 890 891 error = 0; 892 switch (cmd) { 893 case TIOCSFLAGS: 894 error = kauth_authorize_device_tty(l->l_cred, 895 KAUTH_DEVICE_TTY_PRIVSET, tp); 896 break; 897 default: 898 /* nothing */ 899 break; 900 } 901 if (error) { 902 return error; 903 } 904 905 mutex_spin_enter(&sc->sc_lock); 906 907 switch (cmd) { 908 case TIOCSBRK: 909 zynquart_break(sc, true); 910 break; 911 912 case TIOCCBRK: 913 zynquart_break(sc, false); 914 break; 915 916 case TIOCSDTR: 917 zynquart_modem(sc, 1); 918 break; 919 920 case TIOCCDTR: 921 zynquart_modem(sc, 0); 922 break; 923 924 case TIOCGFLAGS: 925 *(int *)data = sc->sc_swflags; 926 break; 927 928 case TIOCSFLAGS: 929 sc->sc_swflags = *(int *)data; 930 break; 931 932 case TIOCMSET: 933 case TIOCMBIS: 934 case TIOCMBIC: 935 tiocm_to_zynquart(sc, cmd, *(int *)data); 936 break; 937 938 case TIOCMGET: 939 *(int *)data = zynquart_to_tiocm(sc); 940 break; 941 942 #ifdef notyet 943 case PPS_IOC_CREATE: 944 case PPS_IOC_DESTROY: 945 case PPS_IOC_GETPARAMS: 946 case PPS_IOC_SETPARAMS: 947 case PPS_IOC_GETCAP: 948 case PPS_IOC_FETCH: 949 #ifdef PPS_SYNC 950 case PPS_IOC_KCBIND: 951 #endif 952 mutex_spin_enter(&timecounter_lock); 953 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 954 mutex_spin_exit(&timecounter_lock); 955 break; 956 957 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 958 mutex_spin_enter(&timecounter_lock); 959 #ifndef PPS_TRAILING_EDGE 960 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 961 &sc->sc_pps_state.ppsinfo.assert_timestamp); 962 #else 963 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 964 &sc->sc_pps_state.ppsinfo.clear_timestamp); 965 #endif 966 mutex_spin_exit(&timecounter_lock); 967 break; 968 #endif 969 970 default: 971 error = EPASSTHROUGH; 972 break; 973 } 974 975 mutex_spin_exit(&sc->sc_lock); 976 977 #ifdef ZYNQUART_DEBUG 978 if (zynquart_debug) 979 zynquartstatus(sc, "zynquartioctl "); 980 #endif 981 982 return (error); 983 } 984 985 integrate void 986 zynquart_schedrx(struct zynquart_softc *sc) 987 { 988 sc->sc_rx_ready = 1; 989 990 /* Wake up the poller. */ 991 softint_schedule(sc->sc_si); 992 } 993 994 void 995 zynquart_break(struct zynquart_softc *sc, bool onoff) 996 { 997 bus_space_tag_t iot = sc->sc_regs.ur_iot; 998 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 999 1000 if (onoff) 1001 SET(sc->sc_cr, CR_STPBRK); 1002 else 1003 CLR(sc->sc_cr, CR_STPBRK); 1004 1005 bus_space_write_4(iot, ioh, UART_CONTROL, sc->sc_cr); 1006 } 1007 1008 void 1009 zynquart_modem(struct zynquart_softc *sc, int onoff) 1010 { 1011 #ifdef notyet 1012 if (sc->sc_mcr_dtr == 0) 1013 return; 1014 1015 if (onoff) 1016 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1017 else 1018 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1019 1020 if (!sc->sc_heldchange) { 1021 if (sc->sc_tx_busy) { 1022 sc->sc_heldtbc = sc->sc_tbc; 1023 sc->sc_tbc = 0; 1024 sc->sc_heldchange = 1; 1025 } else 1026 zynquart_loadchannelregs(sc); 1027 } 1028 #endif 1029 } 1030 1031 void 1032 tiocm_to_zynquart(struct zynquart_softc *sc, u_long how, int ttybits) 1033 { 1034 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1035 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1036 1037 u_char combits; 1038 1039 combits = 0; 1040 if (ISSET(ttybits, TIOCM_DTR)) 1041 SET(combits, MODEMCR_DTR); 1042 if (ISSET(ttybits, TIOCM_RTS)) 1043 SET(combits, MODEMCR_RTS); 1044 1045 switch (how) { 1046 case TIOCMBIC: 1047 CLR(sc->sc_mcr, combits); 1048 break; 1049 1050 case TIOCMBIS: 1051 SET(sc->sc_mcr, combits); 1052 break; 1053 1054 case TIOCMSET: 1055 CLR(sc->sc_mcr, MODEMCR_DTR | MODEMCR_RTS); 1056 SET(sc->sc_mcr, combits); 1057 break; 1058 } 1059 1060 bus_space_write_4(iot, ioh, UART_MODEM_CTRL, sc->sc_mcr); 1061 } 1062 1063 int 1064 zynquart_to_tiocm(struct zynquart_softc *sc) 1065 { 1066 #ifdef notyet 1067 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1068 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1069 #endif 1070 uint32_t combits; 1071 int ttybits = 0; 1072 1073 combits = sc->sc_mcr; 1074 if (ISSET(combits, MODEMCR_DTR)) 1075 SET(ttybits, TIOCM_DTR); 1076 if (ISSET(combits, MODEMCR_RTS)) 1077 SET(ttybits, TIOCM_RTS); 1078 1079 combits = sc->sc_msr; 1080 if (ISSET(combits, MODEMSR_DCD)) 1081 SET(ttybits, TIOCM_CD); 1082 if (ISSET(combits, MODEMSR_CTS)) 1083 SET(ttybits, TIOCM_CTS); 1084 if (ISSET(combits, MODEMSR_DSR)) 1085 SET(ttybits, TIOCM_DSR); 1086 if (ISSET(combits, MODEMSR_RI | MODEMSR_TERI)) 1087 SET(ttybits, TIOCM_RI); 1088 1089 #ifdef notyet 1090 combits = bus_space_read_4(iot, ioh, UART_INTRPT_MASK); 1091 if (ISSET(sc->sc_imr, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1092 SET(ttybits, TIOCM_LE); 1093 #endif 1094 1095 return (ttybits); 1096 } 1097 1098 static uint32_t 1099 cflag_to_zynquart(tcflag_t cflag, uint32_t oldval) 1100 { 1101 uint32_t val = oldval; 1102 1103 CLR(val, MR_CHMODE | MR_NBSTOP | MR_PAR | MR_CHRL | MR_CLKS); 1104 1105 switch (cflag & CSIZE) { 1106 case CS5: 1107 /* not suppreted. use 7-bits */ 1108 case CS6: 1109 SET(val, CHRL_6BIT); 1110 break; 1111 case CS7: 1112 SET(val, CHRL_7BIT); 1113 break; 1114 case CS8: 1115 SET(val, CHRL_8BIT); 1116 break; 1117 } 1118 1119 if (ISSET(cflag, PARENB)) { 1120 /* odd parity */ 1121 if (!ISSET(cflag, PARODD)) 1122 SET(val, PAR_ODD); 1123 else 1124 SET(val, PAR_EVEN); 1125 } else { 1126 SET(val, PAR_NONE); 1127 } 1128 1129 if (ISSET(cflag, CSTOPB)) 1130 SET(val, NBSTOP_2); 1131 1132 return val; 1133 } 1134 1135 int 1136 zynquartparam(struct tty *tp, struct termios *t) 1137 { 1138 struct zynquart_softc *sc = 1139 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev)); 1140 struct zynquart_baudrate_ratio ratio; 1141 uint32_t mcr; 1142 bool change_speed = tp->t_ospeed != t->c_ospeed; 1143 1144 if (ZYNQUART_ISALIVE(sc) == 0) 1145 return (EIO); 1146 1147 /* Check requested parameters. */ 1148 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1149 return (EINVAL); 1150 1151 /* 1152 * For the console, always force CLOCAL and !HUPCL, so that the port 1153 * is always active. 1154 */ 1155 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1156 ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) { 1157 SET(t->c_cflag, CLOCAL); 1158 CLR(t->c_cflag, HUPCL); 1159 } 1160 1161 /* 1162 * If there were no changes, don't do anything. This avoids dropping 1163 * input and improves performance when all we did was frob things like 1164 * VMIN and VTIME. 1165 */ 1166 if ( !change_speed && tp->t_cflag == t->c_cflag) 1167 return (0); 1168 1169 if (change_speed) { 1170 /* calculate baudrate modulator value */ 1171 if (zynquartspeed(t->c_ospeed, &ratio) < 0) 1172 return (EINVAL); 1173 sc->sc_ratio = ratio; 1174 } 1175 1176 mcr = cflag_to_zynquart(t->c_cflag, sc->sc_mcr); 1177 1178 mutex_spin_enter(&sc->sc_lock); 1179 1180 #if 0 1181 /* flow control stuff. not yet */ 1182 /* 1183 * If we're not in a mode that assumes a connection is present, then 1184 * ignore carrier changes. 1185 */ 1186 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1187 sc->sc_msr_dcd = 0; 1188 else 1189 sc->sc_msr_dcd = MSR_DCD; 1190 /* 1191 * Set the flow control pins depending on the current flow control 1192 * mode. 1193 */ 1194 if (ISSET(t->c_cflag, CRTSCTS)) { 1195 sc->sc_mcr_dtr = MCR_DTR; 1196 sc->sc_mcr_rts = MCR_RTS; 1197 sc->sc_msr_cts = MSR_CTS; 1198 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1199 } else if (ISSET(t->c_cflag, MDMBUF)) { 1200 /* 1201 * For DTR/DCD flow control, make sure we don't toggle DTR for 1202 * carrier detection. 1203 */ 1204 sc->sc_mcr_dtr = 0; 1205 sc->sc_mcr_rts = MCR_DTR; 1206 sc->sc_msr_cts = MSR_DCD; 1207 sc->sc_efr = 0; 1208 } else { 1209 /* 1210 * If no flow control, then always set RTS. This will make 1211 * the other side happy if it mistakenly thinks we're doing 1212 * RTS/CTS flow control. 1213 */ 1214 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1215 sc->sc_mcr_rts = 0; 1216 sc->sc_msr_cts = 0; 1217 sc->sc_efr = 0; 1218 if (ISSET(sc->sc_mcr, MCR_DTR)) 1219 SET(sc->sc_mcr, MCR_RTS); 1220 else 1221 CLR(sc->sc_mcr, MCR_RTS); 1222 } 1223 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1224 #endif 1225 1226 /* And copy to tty. */ 1227 tp->t_ispeed = t->c_ospeed; 1228 tp->t_ospeed = t->c_ospeed; 1229 tp->t_cflag = t->c_cflag; 1230 1231 if (!change_speed && mcr == sc->sc_mcr) { 1232 /* noop */ 1233 } else if (!sc->sc_pending && !sc->sc_tx_busy) { 1234 if (mcr != sc->sc_mcr) { 1235 sc->sc_mcr = mcr; 1236 zynquart_load_params(sc); 1237 } 1238 if (change_speed) 1239 zynquart_load_speed(sc); 1240 } else { 1241 if (!sc->sc_pending) { 1242 sc->sc_heldtbc = sc->sc_tbc; 1243 sc->sc_tbc = 0; 1244 } 1245 sc->sc_pending |= 1246 (mcr == sc->sc_mcr ? 0 : ZYNQUART_PEND_PARAM) | 1247 (change_speed ? 0 : ZYNQUART_PEND_SPEED); 1248 sc->sc_mcr = mcr; 1249 } 1250 1251 if (!ISSET(t->c_cflag, CHWFLOW)) { 1252 /* Disable the high water mark. */ 1253 sc->sc_r_hiwat = 0; 1254 sc->sc_r_lowat = 0; 1255 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED)) { 1256 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED); 1257 zynquart_schedrx(sc); 1258 } 1259 if (ISSET(sc->sc_rx_flags, 1260 ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_IBUF_BLOCKED)) { 1261 CLR(sc->sc_rx_flags, 1262 ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_IBUF_BLOCKED); 1263 zynquart_hwiflow(sc); 1264 } 1265 } else { 1266 sc->sc_r_hiwat = zynquart_rbuf_hiwat; 1267 sc->sc_r_lowat = zynquart_rbuf_lowat; 1268 } 1269 1270 mutex_spin_exit(&sc->sc_lock); 1271 1272 /* 1273 * Update the tty layer's idea of the carrier bit, in case we changed 1274 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1275 * explicit request. 1276 */ 1277 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MODEMSR_DCD)); 1278 1279 #ifdef ZYNQUART_DEBUG 1280 if (zynquart_debug) 1281 zynquartstatus(sc, "zynquartparam "); 1282 #endif 1283 1284 if (!ISSET(t->c_cflag, CHWFLOW)) { 1285 if (sc->sc_tx_stopped) { 1286 sc->sc_tx_stopped = 0; 1287 zynquartstart(tp); 1288 } 1289 } 1290 1291 return (0); 1292 } 1293 1294 void 1295 zynquart_iflush(struct zynquart_softc *sc) 1296 { 1297 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1298 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1299 #ifdef DIAGNOSTIC 1300 uint32_t reg = 0xffff; 1301 #endif 1302 int timo; 1303 1304 timo = 50000; 1305 /* flush any pending I/O */ 1306 while (!ISSET(bus_space_read_4(iot, ioh, UART_CHANNEL_STS), STS_REMPTY) && 1307 --timo) 1308 #ifdef DIAGNOSTIC 1309 reg = 1310 #else 1311 (void) 1312 #endif 1313 bus_space_read_4(iot, ioh, UART_TX_RX_FIFO); 1314 1315 #ifdef DIAGNOSTIC 1316 if (!timo) 1317 aprint_error_dev(sc->sc_dev, "zynquart_iflush timeout %02x\n", reg); 1318 #endif 1319 } 1320 1321 int 1322 zynquarthwiflow(struct tty *tp, int block) 1323 { 1324 struct zynquart_softc *sc = 1325 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev)); 1326 1327 if (ZYNQUART_ISALIVE(sc) == 0) 1328 return (0); 1329 1330 #ifdef notyet 1331 if (sc->sc_mcr_rts == 0) 1332 return (0); 1333 #endif 1334 1335 mutex_spin_enter(&sc->sc_lock); 1336 1337 if (block) { 1338 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) { 1339 SET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED); 1340 zynquart_hwiflow(sc); 1341 } 1342 } else { 1343 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED)) { 1344 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED); 1345 zynquart_schedrx(sc); 1346 } 1347 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) { 1348 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED); 1349 zynquart_hwiflow(sc); 1350 } 1351 } 1352 1353 mutex_spin_exit(&sc->sc_lock); 1354 return (1); 1355 } 1356 1357 /* 1358 * (un)block input via hw flowcontrol 1359 */ 1360 void 1361 zynquart_hwiflow(struct zynquart_softc *sc) 1362 { 1363 #ifdef notyet 1364 struct zynquart_regs *regsp= &sc->sc_regs; 1365 1366 if (sc->sc_mcr_rts == 0) 1367 return; 1368 1369 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1370 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1371 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1372 } else { 1373 SET(sc->sc_mcr, sc->sc_mcr_rts); 1374 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1375 } 1376 UR_WRITE_1(regsp, ZYNQUART_REG_MCR, sc->sc_mcr_active); 1377 #endif 1378 } 1379 1380 1381 void 1382 zynquartstart(struct tty *tp) 1383 { 1384 struct zynquart_softc *sc = 1385 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev)); 1386 int s; 1387 u_char *tba; 1388 int tbc; 1389 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1390 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1391 1392 if (ZYNQUART_ISALIVE(sc) == 0) 1393 return; 1394 1395 s = spltty(); 1396 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1397 goto out; 1398 if (sc->sc_tx_stopped) 1399 goto out; 1400 if (!ttypull(tp)) 1401 goto out; 1402 1403 /* Grab the first contiguous region of buffer space. */ 1404 tba = tp->t_outq.c_cf; 1405 tbc = ndqb(&tp->t_outq, 0); 1406 1407 mutex_spin_enter(&sc->sc_lock); 1408 1409 sc->sc_tba = tba; 1410 sc->sc_tbc = tbc; 1411 1412 SET(tp->t_state, TS_BUSY); 1413 sc->sc_tx_busy = 1; 1414 1415 while (sc->sc_tbc > 0 && 1416 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) { 1417 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, *sc->sc_tba); 1418 sc->sc_tbc--; 1419 sc->sc_tba++; 1420 } 1421 1422 /* Enable transmit completion interrupts */ 1423 zynquart_control_txint(sc, true); 1424 1425 mutex_spin_exit(&sc->sc_lock); 1426 out: 1427 splx(s); 1428 return; 1429 } 1430 1431 /* 1432 * Stop output on a line. 1433 */ 1434 void 1435 zynquartstop(struct tty *tp, int flag) 1436 { 1437 struct zynquart_softc *sc = 1438 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev)); 1439 1440 mutex_spin_enter(&sc->sc_lock); 1441 if (ISSET(tp->t_state, TS_BUSY)) { 1442 /* Stop transmitting at the next chunk. */ 1443 sc->sc_tbc = 0; 1444 sc->sc_heldtbc = 0; 1445 if (!ISSET(tp->t_state, TS_TTSTOP)) 1446 SET(tp->t_state, TS_FLUSH); 1447 } 1448 mutex_spin_exit(&sc->sc_lock); 1449 } 1450 1451 void 1452 zynquartdiag(void *arg) 1453 { 1454 #ifdef notyet 1455 struct zynquart_softc *sc = arg; 1456 int overflows, floods; 1457 1458 mutex_spin_enter(&sc->sc_lock); 1459 overflows = sc->sc_overflows; 1460 sc->sc_overflows = 0; 1461 floods = sc->sc_floods; 1462 sc->sc_floods = 0; 1463 sc->sc_errors = 0; 1464 mutex_spin_exit(&sc->sc_lock); 1465 1466 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1467 device_xname(sc->sc_dev), 1468 overflows, overflows == 1 ? "" : "s", 1469 floods, floods == 1 ? "" : "s"); 1470 #endif 1471 } 1472 1473 integrate void 1474 zynquart_rxsoft(struct zynquart_softc *sc, struct tty *tp) 1475 { 1476 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1477 u_int cc, scc, outp; 1478 uint16_t data; 1479 u_int code; 1480 1481 scc = cc = ZYNQUART_RBUF_AVAIL(sc); 1482 1483 #if 0 1484 if (cc == zynquart_rbuf_size-1) { 1485 sc->sc_floods++; 1486 if (sc->sc_errors++ == 0) 1487 callout_reset(&sc->sc_diag_callout, 60 * hz, 1488 zynquartdiag, sc); 1489 } 1490 #endif 1491 1492 /* If not yet open, drop the entire buffer content here */ 1493 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1494 sc->sc_rbuf_out = sc->sc_rbuf_in; 1495 cc = 0; 1496 } 1497 1498 outp = sc->sc_rbuf_out; 1499 1500 #define ERRBITS (INT_PARE|INT_FRAME|INT_ROVR) 1501 1502 while (cc) { 1503 data = sc->sc_rbuf[outp]; 1504 code = data & 0xff; 1505 if (ISSET(__SHIFTOUT(data, ERROR_BITS), ERRBITS)) { 1506 if (sc->sc_errors.err == 0) 1507 callout_reset(&sc->sc_diag_callout, 1508 60 * hz, zynquartdiag, sc); 1509 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_ROVR)) 1510 sc->sc_errors.ovrrun++; 1511 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_FRAME)) { 1512 sc->sc_errors.frmerr++; 1513 SET(code, TTY_FE); 1514 } 1515 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_PARE)) { 1516 sc->sc_errors.prerr++; 1517 SET(code, TTY_PE); 1518 } 1519 } 1520 if ((*rint)(code, tp) == -1) { 1521 /* 1522 * The line discipline's buffer is out of space. 1523 */ 1524 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) { 1525 /* 1526 * We're either not using flow control, or the 1527 * line discipline didn't tell us to block for 1528 * some reason. Either way, we have no way to 1529 * know when there's more space available, so 1530 * just drop the rest of the data. 1531 */ 1532 sc->sc_rbuf_out = sc->sc_rbuf_in; 1533 cc = 0; 1534 } else { 1535 /* 1536 * Don't schedule any more receive processing 1537 * until the line discipline tells us there's 1538 * space available (through zynquarthwiflow()). 1539 * Leave the rest of the data in the input 1540 * buffer. 1541 */ 1542 SET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED); 1543 } 1544 break; 1545 } 1546 outp = ZYNQUART_RBUF_INC(sc, outp, 1); 1547 cc--; 1548 } 1549 1550 if (cc != scc) { 1551 sc->sc_rbuf_out = outp; 1552 mutex_spin_enter(&sc->sc_lock); 1553 1554 cc = ZYNQUART_RBUF_SPACE(sc); 1555 1556 /* Buffers should be ok again, release possible block. */ 1557 if (cc >= sc->sc_r_lowat) { 1558 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_OVERFLOWED)) { 1559 CLR(sc->sc_rx_flags, ZYNQUART_RX_IBUF_OVERFLOWED); 1560 zynquart_control_rxint(sc, true); 1561 } 1562 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED)) { 1563 CLR(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED); 1564 zynquart_hwiflow(sc); 1565 } 1566 } 1567 mutex_spin_exit(&sc->sc_lock); 1568 } 1569 } 1570 1571 integrate void 1572 zynquart_txsoft(struct zynquart_softc *sc, struct tty *tp) 1573 { 1574 1575 CLR(tp->t_state, TS_BUSY); 1576 if (ISSET(tp->t_state, TS_FLUSH)) 1577 CLR(tp->t_state, TS_FLUSH); 1578 else 1579 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1580 (*tp->t_linesw->l_start)(tp); 1581 } 1582 1583 integrate void 1584 zynquart_stsoft(struct zynquart_softc *sc, struct tty *tp) 1585 { 1586 #ifdef notyet 1587 u_char msr, delta; 1588 1589 mutex_spin_enter(&sc->sc_lock); 1590 msr = sc->sc_msr; 1591 delta = sc->sc_msr_delta; 1592 sc->sc_msr_delta = 0; 1593 mutex_spin_exit(&sc->sc_lock); 1594 1595 if (ISSET(delta, sc->sc_msr_dcd)) { 1596 /* 1597 * Inform the tty layer that carrier detect changed. 1598 */ 1599 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1600 } 1601 1602 if (ISSET(delta, sc->sc_msr_cts)) { 1603 /* Block or unblock output according to flow control. */ 1604 if (ISSET(msr, sc->sc_msr_cts)) { 1605 sc->sc_tx_stopped = 0; 1606 (*tp->t_linesw->l_start)(tp); 1607 } else { 1608 sc->sc_tx_stopped = 1; 1609 } 1610 } 1611 1612 #endif 1613 #ifdef ZYNQUART_DEBUG 1614 if (zynquart_debug) 1615 zynquartstatus(sc, "zynquart_stsoft"); 1616 #endif 1617 } 1618 1619 void 1620 zynquartsoft(void *arg) 1621 { 1622 struct zynquart_softc *sc = arg; 1623 struct tty *tp; 1624 1625 if (ZYNQUART_ISALIVE(sc) == 0) 1626 return; 1627 1628 tp = sc->sc_tty; 1629 1630 if (sc->sc_rx_ready) { 1631 sc->sc_rx_ready = 0; 1632 zynquart_rxsoft(sc, tp); 1633 } 1634 1635 if (sc->sc_st_check) { 1636 sc->sc_st_check = 0; 1637 zynquart_stsoft(sc, tp); 1638 } 1639 1640 if (sc->sc_tx_done) { 1641 sc->sc_tx_done = 0; 1642 zynquart_txsoft(sc, tp); 1643 } 1644 } 1645 1646 int 1647 zynquartintr(void *arg) 1648 { 1649 struct zynquart_softc *sc = arg; 1650 uint32_t sts; 1651 uint32_t int_sts; 1652 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1653 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1654 1655 if (ZYNQUART_ISALIVE(sc) == 0) 1656 return (0); 1657 1658 mutex_spin_enter(&sc->sc_lock); 1659 1660 int_sts = bus_space_read_4(iot, ioh, UART_CHNL_INT_STS); 1661 do { 1662 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS); 1663 if (!(sts & STS_REMPTY)) 1664 zynquartintr_read(sc); 1665 } while (!(sts & STS_REMPTY)); 1666 1667 if (sts & STS_TEMPTY) 1668 zynquartintr_send(sc); 1669 1670 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, int_sts); 1671 1672 mutex_spin_exit(&sc->sc_lock); 1673 1674 /* Wake up the poller. */ 1675 softint_schedule(sc->sc_si); 1676 1677 #ifdef RND_COM 1678 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1679 #endif 1680 1681 return (1); 1682 } 1683 1684 1685 /* 1686 * called when there is least one character in rxfifo 1687 * 1688 */ 1689 1690 static void 1691 zynquartintr_read(struct zynquart_softc *sc) 1692 { 1693 int cc; 1694 uint16_t rd; 1695 uint32_t sts; 1696 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1697 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1698 1699 cc = ZYNQUART_RBUF_SPACE(sc); 1700 1701 /* clear aging timer interrupt */ 1702 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, INT_TIMEOUT); 1703 1704 while (cc > 0) { 1705 int cn_trapped = 0; 1706 1707 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1708 bus_space_read_4(iot, ioh, UART_TX_RX_FIFO); 1709 1710 cn_check_magic(sc->sc_tty->t_dev, 1711 rd & 0xff, zynquart_cnm_state); 1712 1713 if (!cn_trapped) { 1714 sc->sc_rbuf_in = ZYNQUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1715 cc--; 1716 } 1717 1718 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS); 1719 if (sts & STS_REMPTY) 1720 break; 1721 } 1722 1723 /* 1724 * Current string of incoming characters ended because 1725 * no more data was available or we ran out of space. 1726 * Schedule a receive event if any data was received. 1727 * If we're out of space, turn off receive interrupts. 1728 */ 1729 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED)) 1730 sc->sc_rx_ready = 1; 1731 /* 1732 * See if we are in danger of overflowing a buffer. If 1733 * so, use hardware flow control to ease the pressure. 1734 */ 1735 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED) && 1736 cc < sc->sc_r_hiwat) { 1737 sc->sc_rx_flags |= ZYNQUART_RX_IBUF_BLOCKED; 1738 zynquart_hwiflow(sc); 1739 } 1740 1741 /* 1742 * If we're out of space, disable receive interrupts 1743 * until the queue has drained a bit. 1744 */ 1745 if (!cc) { 1746 sc->sc_rx_flags |= ZYNQUART_RX_IBUF_OVERFLOWED; 1747 zynquart_control_rxint(sc, false); 1748 } 1749 } 1750 1751 void 1752 zynquartintr_send(struct zynquart_softc *sc) 1753 { 1754 uint32_t sts; 1755 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1756 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1757 1758 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS); 1759 1760 if (sc->sc_pending) { 1761 if (sts & STS_TEMPTY) { 1762 zynquart_load_pendings(sc); 1763 sc->sc_tbc = sc->sc_heldtbc; 1764 sc->sc_heldtbc = 0; 1765 } else { 1766 /* wait for TX fifo empty */ 1767 zynquart_control_txint(sc, true); 1768 return; 1769 } 1770 } 1771 1772 while (sc->sc_tbc > 0 && 1773 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) { 1774 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, *sc->sc_tba); 1775 sc->sc_tbc--; 1776 sc->sc_tba++; 1777 } 1778 1779 if (sc->sc_tbc > 0) 1780 zynquart_control_txint(sc, true); 1781 else { 1782 /* no more chars to send. 1783 we don't need tx interrupt any more. */ 1784 zynquart_control_txint(sc, false); 1785 if (sc->sc_tx_busy) { 1786 sc->sc_tx_busy = 0; 1787 sc->sc_tx_done = 1; 1788 } 1789 } 1790 } 1791 1792 static void 1793 zynquart_disable_all_interrupts(struct zynquart_softc *sc) 1794 { 1795 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1796 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1797 1798 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, 0xffffffff); 1799 } 1800 1801 static void 1802 zynquart_control_rxint(struct zynquart_softc *sc, bool enable) 1803 { 1804 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1805 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1806 uint32_t mask = INT_TIMEOUT | INT_PARE | INT_FRAME | INT_ROVR | INT_RFUL | INT_RTRIG; 1807 uint32_t sts; 1808 1809 /* clear */ 1810 sts = bus_space_read_4(iot, ioh, UART_CHNL_INT_STS); 1811 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, sts); 1812 1813 if (enable) 1814 bus_space_write_4(iot, ioh, UART_INTRPT_EN, mask); 1815 else 1816 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, mask); 1817 } 1818 1819 static void 1820 zynquart_control_txint(struct zynquart_softc *sc, bool enable) 1821 { 1822 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1823 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1824 uint32_t mask = INT_TEMPTY; 1825 1826 if (enable) 1827 bus_space_write_4(iot, ioh, UART_INTRPT_EN, mask); 1828 else 1829 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, mask); 1830 } 1831 1832 1833 static void 1834 zynquart_load_params(struct zynquart_softc *sc) 1835 { 1836 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1837 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1838 1839 bus_space_write_4(iot, ioh, UART_MODE, sc->sc_mcr); 1840 } 1841 1842 static void 1843 zynquart_load_speed(struct zynquart_softc *sc) 1844 { 1845 /* bus_space_tag_t iot = sc->sc_regs.ur_iot; */ 1846 /* bus_space_handle_t ioh = sc->sc_regs.ur_ioh; */ 1847 1848 /* XXX */ 1849 } 1850 1851 1852 static void 1853 zynquart_load_pendings(struct zynquart_softc *sc) 1854 { 1855 if (sc->sc_pending & ZYNQUART_PEND_PARAM) 1856 zynquart_load_params(sc); 1857 if (sc->sc_pending & ZYNQUART_PEND_SPEED) 1858 zynquart_load_speed(sc); 1859 sc->sc_pending = 0; 1860 } 1861 1862 /* 1863 * The following functions are polled getc and putc routines, shared 1864 * by the console and kgdb glue. 1865 * 1866 * The read-ahead code is so that you can detect pending in-band 1867 * cn_magic in polled mode while doing output rather than having to 1868 * wait until the kernel decides it needs input. 1869 */ 1870 1871 #define READAHEAD_RING_LEN 16 1872 static int zynquart_readahead[READAHEAD_RING_LEN]; 1873 static int zynquart_readahead_in = 0; 1874 static int zynquart_readahead_out = 0; 1875 #define READAHEAD_IS_EMPTY() (zynquart_readahead_in==zynquart_readahead_out) 1876 #define READAHEAD_IS_FULL() \ 1877 (((zynquart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==zynquart_readahead_out) 1878 1879 int 1880 zynquart_common_getc(dev_t dev, struct zynquart_regs *regsp) 1881 { 1882 int s = splserial(); 1883 u_char c; 1884 bus_space_tag_t iot = regsp->ur_iot; 1885 bus_space_handle_t ioh = regsp->ur_ioh; 1886 uint32_t sts; 1887 1888 /* got a character from reading things earlier */ 1889 if (zynquart_readahead_in != zynquart_readahead_out) { 1890 1891 c = zynquart_readahead[zynquart_readahead_out]; 1892 zynquart_readahead_out = (zynquart_readahead_out + 1) & 1893 (READAHEAD_RING_LEN-1); 1894 splx(s); 1895 return (c); 1896 } 1897 1898 /* block until a character becomes available */ 1899 while ((sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS)) & STS_REMPTY) 1900 ; 1901 1902 c = 0xff & bus_space_read_4(iot, ioh, UART_TX_RX_FIFO); 1903 1904 { 1905 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 1906 #ifdef DDB 1907 extern int db_active; 1908 if (!db_active) 1909 #endif 1910 cn_check_magic(dev, c, zynquart_cnm_state); 1911 } 1912 splx(s); 1913 return (c); 1914 } 1915 1916 void 1917 zynquart_common_putc(dev_t dev, struct zynquart_regs *regsp, int c) 1918 { 1919 int s = splserial(); 1920 int cin, timo; 1921 bus_space_tag_t iot = regsp->ur_iot; 1922 bus_space_handle_t ioh = regsp->ur_ioh; 1923 1924 if (!READAHEAD_IS_FULL() && 1925 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_REMPTY)) { 1926 1927 int __attribute__((__unused__))cn_trapped = 0; 1928 cin = bus_space_read_4(iot, ioh, UART_TX_RX_FIFO); 1929 cn_check_magic(dev, cin & 0xff, zynquart_cnm_state); 1930 zynquart_readahead_in = (zynquart_readahead_in + 1) & 1931 (READAHEAD_RING_LEN-1); 1932 } 1933 1934 /* wait for any pending transmission to finish */ 1935 timo = 150000; 1936 do { 1937 if (!(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) { 1938 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, c); 1939 break; 1940 } 1941 } while(--timo > 0); 1942 1943 ZYNQUART_BARRIER(regsp, BR | BW); 1944 1945 splx(s); 1946 } 1947 1948 /* 1949 * Initialize UART for use as console or KGDB line. 1950 */ 1951 int 1952 zynquart_init(struct zynquart_regs *regsp, int rate, tcflag_t cflag) 1953 { 1954 struct zynquart_baudrate_ratio ratio; 1955 1956 if (bus_space_map(regsp->ur_iot, regsp->ur_iobase, UART_SIZE, 0, 1957 ®sp->ur_ioh)) 1958 return ENOMEM; /* ??? */ 1959 1960 if (zynquartspeed(rate, &ratio) < 0) 1961 return EINVAL; 1962 1963 /* clear status registers */ 1964 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, UART_CHNL_INT_STS, 0xffff); 1965 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, UART_CHANNEL_STS, 0xffff); 1966 1967 return (0); 1968 } 1969 1970 1971 1972 /* 1973 * Following are all routines needed for UART to act as console 1974 */ 1975 struct consdev zynquartcons = { 1976 .cn_getc = zynquartcngetc, 1977 .cn_putc = zynquartcnputc, 1978 .cn_pollc = nullcnpollc 1979 }; 1980 1981 1982 int 1983 zynquart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 1984 tcflag_t cflag) 1985 { 1986 struct zynquart_regs regs; 1987 int res; 1988 1989 regs.ur_iot = iot; 1990 regs.ur_iobase = iobase; 1991 1992 res = zynquart_init(®s, rate, cflag); 1993 if (res) 1994 return (res); 1995 1996 cn_tab = &zynquartcons; 1997 cn_init_magic(&zynquart_cnm_state); 1998 cn_set_magic("\047\001"); /* default magic is BREAK */ 1999 2000 zynquartconsrate = rate; 2001 zynquartconscflag = cflag; 2002 2003 zynquartconsregs = regs; 2004 2005 return 0; 2006 } 2007 2008 int 2009 zynquartcngetc(dev_t dev) 2010 { 2011 return (zynquart_common_getc(dev, &zynquartconsregs)); 2012 } 2013 2014 /* 2015 * Console kernel output character routine. 2016 */ 2017 void 2018 zynquartcnputc(dev_t dev, int c) 2019 { 2020 zynquart_common_putc(dev, &zynquartconsregs, c); 2021 } 2022 2023 #ifdef KGDB 2024 int 2025 zynquart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2026 tcflag_t cflag) 2027 { 2028 int res; 2029 2030 if (iot == zynquartconsregs.ur_iot && 2031 iobase == zynquartconsregs.ur_iobase) { 2032 #if !defined(DDB) 2033 return (EBUSY); /* cannot share with console */ 2034 #else 2035 zynquart_kgdb_regs.ur_iot = iot; 2036 zynquart_kgdb_regs.ur_ioh = zynquartconsregs.ur_ioh; 2037 zynquart_kgdb_regs.ur_iobase = iobase; 2038 #endif 2039 } else { 2040 zynquart_kgdb_regs.ur_iot = iot; 2041 zynquart_kgdb_regs.ur_iobase = iobase; 2042 2043 res = zynquart_init(&zynquart_kgdb_regs, rate, cflag); 2044 if (res) 2045 return (res); 2046 2047 /* 2048 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2049 * expects this to be initialized 2050 */ 2051 cn_init_magic(&zynquart_cnm_state); 2052 cn_set_magic("\047\001"); 2053 } 2054 2055 kgdb_attach(zynquart_kgdb_getc, zynquart_kgdb_putc, &zynquart_kgdb_regs); 2056 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2057 2058 return (0); 2059 } 2060 2061 /* ARGSUSED */ 2062 int 2063 zynquart_kgdb_getc(void *arg) 2064 { 2065 struct zynquart_regs *regs = arg; 2066 2067 return (zynquart_common_getc(NODEV, regs)); 2068 } 2069 2070 /* ARGSUSED */ 2071 void 2072 zynquart_kgdb_putc(void *arg, int c) 2073 { 2074 struct zynquart_regs *regs = arg; 2075 2076 zynquart_common_putc(NODEV, regs, c); 2077 } 2078 #endif /* KGDB */ 2079 2080 /* helper function to identify the zynquart ports used by 2081 console or KGDB (and not yet autoconf attached) */ 2082 int 2083 zynquart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2084 { 2085 bus_space_handle_t help; 2086 2087 if (!zynquartconsattached && 2088 iot == zynquartconsregs.ur_iot && iobase == zynquartconsregs.ur_iobase) 2089 help = zynquartconsregs.ur_ioh; 2090 #ifdef KGDB 2091 else if (!zynquart_kgdb_attached && 2092 iot == zynquart_kgdb_regs.ur_iot && iobase == zynquart_kgdb_regs.ur_iobase) 2093 help = zynquart_kgdb_regs.ur_ioh; 2094 #endif 2095 else 2096 return (0); 2097 2098 if (ioh) 2099 *ioh = help; 2100 return (1); 2101 } 2102 2103 #ifdef notyet 2104 2105 bool 2106 zynquart_cleanup(device_t self, int how) 2107 { 2108 /* 2109 * this routine exists to serve as a shutdown hook for systems that 2110 * have firmware which doesn't interact properly with a zynquart device in 2111 * FIFO mode. 2112 */ 2113 struct zynquart_softc *sc = device_private(self); 2114 2115 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_FIFO)) 2116 UR_WRITE_1(&sc->sc_regs, ZYNQUART_REG_FIFO, 0); 2117 2118 return true; 2119 } 2120 #endif 2121 2122 #ifdef notyet 2123 bool 2124 zynquart_suspend(device_t self PMF_FN_ARGS) 2125 { 2126 struct zynquart_softc *sc = device_private(self); 2127 2128 UR_WRITE_1(&sc->sc_regs, ZYNQUART_REG_IER, 0); 2129 (void)CSR_READ_1(&sc->sc_regs, ZYNQUART_REG_IIR); 2130 2131 return true; 2132 } 2133 #endif 2134 2135 #ifdef notyet 2136 bool 2137 zynquart_resume(device_t self PMF_FN_ARGS) 2138 { 2139 struct zynquart_softc *sc = device_private(self); 2140 2141 mutex_spin_enter(&sc->sc_lock); 2142 zynquart_loadchannelregs(sc); 2143 mutex_spin_exit(&sc->sc_lock); 2144 2145 return true; 2146 } 2147 #endif 2148 2149 static void 2150 zynquart_enable_debugport(struct zynquart_softc *sc) 2151 { 2152 /* bus_space_tag_t iot = sc->sc_regs.ur_iot; */ 2153 /* bus_space_handle_t ioh = sc->sc_regs.ur_ioh; */ 2154 } 2155 2156 2157 void 2158 zynquart_set_frequency(u_int freq, u_int div) 2159 { 2160 zynquart_freq = freq; 2161 zynquart_freqdiv = div; 2162 } 2163
Indexes created Thu Oct 02 14:10:14 GMT 2025