becc.c revision 1.1
1 /* $NetBSD: becc.c,v 1.1 2003/01/25 01:57:17 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the ADI Engineering Big Endian 40 * Companion Chip. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #define _ARM32_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 50 #include <arm/xscale/i80200reg.h> 51 #include <arm/xscale/beccreg.h> 52 #include <arm/xscale/beccvar.h> 53 54 /* 55 * Virtual address at which the BECC is mapped. This is filled in 56 * by machine-dependent code. 57 */ 58 vaddr_t becc_vaddr; 59 60 /* 61 * BECC revision number. This is initialized by early bootstrap code. 62 */ 63 int becc_rev; 64 const char *becc_revisions[] = { 65 "<= 7", 66 "8", 67 ">= 9", 68 }; 69 70 /* 71 * There can be only one BECC, so we keep a global pointer to 72 * the softc, so board-specific code can use features of the 73 * BECC without having to have a handle on the softc itself. 74 */ 75 struct becc_softc *becc_softc; 76 77 static int becc_pcibus_print(void *, const char *); 78 79 static void becc_pci_dma_init(struct becc_softc *); 80 81 /* 82 * becc_attach: 83 * 84 * Board-independent attach routine for the BECC. 85 */ 86 void 87 becc_attach(struct becc_softc *sc) 88 { 89 struct pcibus_attach_args pba; 90 uint32_t reg; 91 92 becc_softc = sc; 93 94 /* 95 * Set the AF bit in the BCUMOD since the BECC will honor it. 96 * This allows the BECC to return the requested 4-byte word 97 * first when filling a cache line. 98 */ 99 __asm __volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg) ); 100 __asm __volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF)); 101 102 /* 103 * Program the address windows of the PCI core. Note 104 * that PCI master and target cycles must be disabled 105 * while we configure the windows. 106 */ 107 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 108 reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 109 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 110 111 /* 112 * Program the two inbound PCI memory windows. 113 */ 114 becc_pcicore_write(sc, PCI_MAPREG_START + 0, 115 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 116 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 117 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0); 118 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK); 119 120 becc_pcicore_write(sc, PCI_MAPREG_START + 4, 121 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 122 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 123 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4); 124 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK); 125 126 /* 127 * ...and the third on v8 and later. 128 */ 129 if (becc_rev >= BECC_REV_V8) { 130 becc_pcicore_write(sc, PCI_MAPREG_START + 8, 131 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 132 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 133 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8); 134 BECC_CSR_WRITE(BECC_PSTR1, 135 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK); 136 } 137 138 /* 139 * Program the two outbound PCI memory windows. On a 140 * big-endian system, we byte-swap the first window. 141 * The second window is used for STREAM transfers. 142 * 143 * There's a third window on v9 and later, but we don't 144 * use it for anything; program it anyway, just to be 145 * safe. 146 */ 147 #ifdef __ARMEB__ 148 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */ | 149 POMRx_BEE); 150 #else 151 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */); 152 #endif 153 BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */); 154 155 if (becc_rev >= BECC_REV_V9) 156 BECC_CSR_WRITE(BECC_POMR3, 157 sc->sc_owin_xlate[2] /* | POMRx_F32 */); 158 159 /* 160 * Program the PCI I/O window. On a big-endian system, 161 * we do byte-swapping. 162 * 163 * XXX What about STREAM transfers? 164 */ 165 #ifdef __ARMEB__ 166 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate | POIR_BEE); 167 #else 168 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate); 169 #endif 170 171 /* 172 * Configure PCI configuration cycle access. 173 */ 174 BECC_CSR_WRITE(BECC_POCR, 0); 175 176 /* 177 * ...and now reenable PCI access. 178 */ 179 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 180 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 181 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 182 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 183 184 /* Initialize the bus space tags. */ 185 becc_io_bs_init(&sc->sc_pci_iot, sc); 186 becc_mem_bs_init(&sc->sc_pci_memt, sc); 187 188 /* Initialize the PCI chipset tag. */ 189 becc_pci_init(&sc->sc_pci_chipset, sc); 190 191 /* Initialize the DMA tags. */ 192 becc_pci_dma_init(sc); 193 194 /* 195 * Attach the PCI bus. 196 */ 197 pba.pba_busname = "pci"; 198 pba.pba_iot = &sc->sc_pci_iot; 199 pba.pba_memt = &sc->sc_pci_memt; 200 pba.pba_dmat = &sc->sc_pci_dmat; 201 pba.pba_pc = &sc->sc_pci_chipset; 202 pba.pba_bus = 0; 203 pba.pba_bridgetag = NULL; 204 pba.pba_intrswiz = 0; 205 pba.pba_intrtag = 0; 206 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 207 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 208 (void) config_found(&sc->sc_dev, &pba, becc_pcibus_print); 209 } 210 211 /* 212 * becc_pcibus_print: 213 * 214 * Autoconfiguration cfprint routine when attaching 215 * to the "pcibus" attribute. 216 */ 217 static int 218 becc_pcibus_print(void *aux, const char *pnp) 219 { 220 struct pcibus_attach_args *pba = aux; 221 222 if (pnp) 223 printf("%s at %s", pba->pba_busname, pnp); 224 225 printf(" bus %d", pba->pba_bus); 226 227 return (UNCONF); 228 } 229 230 /* 231 * becc_pci_dma_init: 232 * 233 * Initialize the PCI DMA tag. 234 */ 235 static void 236 becc_pci_dma_init(struct becc_softc *sc) 237 { 238 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 239 struct arm32_dma_range *dr = sc->sc_pci_dma_range; 240 int i = 0; 241 242 /* 243 * If we have the 128MB window, put it first, since it 244 * will always cover the entire memory range. 245 */ 246 if (becc_rev >= BECC_REV_V8) { 247 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate; 248 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base; 249 dr[i].dr_len = (128U * 1024 * 1024); 250 i++; 251 } 252 253 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate; 254 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base; 255 dr[i].dr_len = (32U * 1024 * 1024); 256 i++; 257 258 dr[i].dr_sysbase = sc->sc_iwin[1].iwin_xlate; 259 dr[i].dr_busbase = sc->sc_iwin[1].iwin_base; 260 dr[i].dr_len = (32U * 1024 * 1024); 261 i++; 262 263 dmat->_ranges = dr; 264 dmat->_nranges = i; 265 266 dmat->_dmamap_create = _bus_dmamap_create; 267 dmat->_dmamap_destroy = _bus_dmamap_destroy; 268 dmat->_dmamap_load = _bus_dmamap_load; 269 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 270 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 271 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 272 dmat->_dmamap_unload = _bus_dmamap_unload; 273 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 274 dmat->_dmamap_sync_post = NULL; 275 276 dmat->_dmamem_alloc = _bus_dmamem_alloc; 277 dmat->_dmamem_free = _bus_dmamem_free; 278 dmat->_dmamem_map = _bus_dmamem_map; 279 dmat->_dmamem_unmap = _bus_dmamem_unmap; 280 dmat->_dmamem_mmap = _bus_dmamem_mmap; 281 } 282 283 uint32_t 284 becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg) 285 { 286 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 287 288 return (*(__volatile uint32_t *) va); 289 } 290 291 void 292 becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val) 293 { 294 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 295 296 *(__volatile uint32_t *) va = val; 297 } 298
Indexes created Thu Sep 25 06:09:39 GMT 2025