becc.c revision 1.17
1 /* $NetBSD: becc.c,v 1.17 2021/04/24 23:36:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the ADI Engineering Big Endian 40 * Companion Chip. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: becc.c,v 1.17 2021/04/24 23:36:29 thorpej Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #define _ARM32_BUS_DMA_PRIVATE 51 #include <sys/bus.h> 52 53 #include <arm/xscale/i80200reg.h> 54 #include <arm/xscale/beccreg.h> 55 #include <arm/xscale/beccvar.h> 56 57 /* 58 * Virtual address at which the BECC is mapped. This is filled in 59 * by machine-dependent code. 60 */ 61 vaddr_t becc_vaddr; 62 63 /* 64 * BECC revision number. This is initialized by early bootstrap code. 65 */ 66 int becc_rev; 67 const char *becc_revisions[] = { 68 "<= 7", 69 "8", 70 ">= 9", 71 }; 72 73 /* 74 * There can be only one BECC, so we keep a global pointer to 75 * the softc, so board-specific code can use features of the 76 * BECC without having to have a handle on the softc itself. 77 */ 78 struct becc_softc *becc_softc; 79 80 static int becc_search(device_t, cfdata_t, const int *, void *); 81 static int becc_print(void *, const char *); 82 83 static void becc_pci_dma_init(struct becc_softc *); 84 static void becc_local_dma_init(struct becc_softc *); 85 86 /* 87 * becc_attach: 88 * 89 * Board-independent attach routine for the BECC. 90 */ 91 void 92 becc_attach(struct becc_softc *sc) 93 { 94 struct pcibus_attach_args pba; 95 uint32_t reg; 96 97 becc_softc = sc; 98 99 /* 100 * Set the AF bit in the BCUMOD since the BECC will honor it. 101 * This allows the BECC to return the requested 4-byte word 102 * first when filling a cache line. 103 */ 104 __asm volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg)); 105 __asm volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF)); 106 107 /* 108 * Program the address windows of the PCI core. Note 109 * that PCI master and target cycles must be disabled 110 * while we configure the windows. 111 */ 112 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 113 reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 114 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 115 116 /* 117 * Program the two inbound PCI memory windows. 118 */ 119 becc_pcicore_write(sc, PCI_MAPREG_START + 0, 120 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 121 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 122 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0); 123 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK); 124 125 becc_pcicore_write(sc, PCI_MAPREG_START + 4, 126 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 127 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 128 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4); 129 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK); 130 131 /* 132 * ...and the third on v8 and later. 133 */ 134 if (becc_rev >= BECC_REV_V8) { 135 becc_pcicore_write(sc, PCI_MAPREG_START + 8, 136 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 137 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 138 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8); 139 BECC_CSR_WRITE(BECC_PSTR2, 140 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK); 141 } 142 143 /* 144 * Program the two outbound PCI memory windows. 145 * NOTE: WE DO NOT BYTE-SWAP OUTBOUND WINDOWS IN BIG-ENDIAN 146 * MODE. I know this seems counter-intuitive, but that's 147 * how it is. 148 * 149 * There's a third window on v9 and later, but we don't 150 * use it for anything; program it anyway, just to be 151 * safe. 152 */ 153 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */); 154 BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */); 155 156 if (becc_rev >= BECC_REV_V9) 157 BECC_CSR_WRITE(BECC_POMR3, 158 sc->sc_owin_xlate[2] /* | POMRx_F32 */); 159 160 /* 161 * Program the PCI I/O window. See note above about byte-swapping. 162 * 163 * XXX What about STREAM transfers? 164 */ 165 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate); 166 167 /* 168 * Configure PCI configuration cycle access. 169 */ 170 BECC_CSR_WRITE(BECC_POCR, 0); 171 172 /* 173 * ...and now reenable PCI access. 174 */ 175 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 176 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 177 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 178 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 179 180 /* Initialize the bus space tags. */ 181 becc_io_bs_init(&sc->sc_pci_iot, sc); 182 becc_mem_bs_init(&sc->sc_pci_memt, sc); 183 184 /* Initialize the PCI chipset tag. */ 185 becc_pci_init(&sc->sc_pci_chipset, sc); 186 187 /* Initialize the DMA tags. */ 188 becc_pci_dma_init(sc); 189 becc_local_dma_init(sc); 190 191 /* 192 * Attach any on-chip peripherals. We used indirect config, since 193 * the BECC is a soft-core with a variety of peripherals, depending 194 * on configuration. 195 */ 196 config_search(sc->sc_dev, NULL, 197 CFARG_SEARCH, becc_search, 198 CFARG_IATTR, "becc", 199 CFARG_EOL); 200 201 /* 202 * Attach the PCI bus. 203 */ 204 pba.pba_iot = &sc->sc_pci_iot; 205 pba.pba_memt = &sc->sc_pci_memt; 206 pba.pba_dmat = &sc->sc_pci_dmat; 207 pba.pba_dmat64 = NULL; 208 pba.pba_pc = &sc->sc_pci_chipset; 209 pba.pba_bus = 0; 210 pba.pba_bridgetag = NULL; 211 pba.pba_intrswiz = 0; 212 pba.pba_intrtag = 0; 213 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 214 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 215 config_found(sc->sc_dev, &pba, pcibusprint, 216 CFARG_IATTR, "pcibus", 217 CFARG_EOL); 218 } 219 220 /* 221 * becc_search: 222 * 223 * Indirect autoconfiguration glue for BECC. 224 */ 225 static int 226 becc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 227 { 228 struct becc_softc *sc = device_private(parent); 229 struct becc_attach_args ba; 230 231 ba.ba_dmat = &sc->sc_local_dmat; 232 233 if (config_probe(parent, cf, &ba)) 234 config_attach(parent, cf, &ba, becc_print, CFARG_EOL); 235 236 return (0); 237 } 238 239 /* 240 * becc_print: 241 * 242 * Autoconfiguration cfprint routine when attaching 243 * to the BECC. 244 */ 245 static int 246 becc_print(void *aux, const char *pnp) 247 { 248 249 return (UNCONF); 250 } 251 252 /* 253 * becc_pci_dma_init: 254 * 255 * Initialize the PCI DMA tag. 256 */ 257 static void 258 becc_pci_dma_init(struct becc_softc *sc) 259 { 260 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 261 struct arm32_dma_range *dr = sc->sc_pci_dma_range; 262 int i = 0; 263 264 /* 265 * If we have the 128MB window, put it first, since it 266 * will always cover the entire memory range. 267 */ 268 if (becc_rev >= BECC_REV_V8) { 269 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate; 270 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base; 271 dr[i].dr_len = (128U * 1024 * 1024); 272 i++; 273 } 274 275 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate; 276 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base; 277 dr[i].dr_len = (32U * 1024 * 1024); 278 i++; 279 280 dr[i].dr_sysbase = sc->sc_iwin[1].iwin_xlate; 281 dr[i].dr_busbase = sc->sc_iwin[1].iwin_base; 282 dr[i].dr_len = (32U * 1024 * 1024); 283 i++; 284 285 dmat->_ranges = dr; 286 dmat->_nranges = i; 287 288 dmat->_dmamap_create = _bus_dmamap_create; 289 dmat->_dmamap_destroy = _bus_dmamap_destroy; 290 dmat->_dmamap_load = _bus_dmamap_load; 291 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 292 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 293 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 294 dmat->_dmamap_unload = _bus_dmamap_unload; 295 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 296 dmat->_dmamap_sync_post = NULL; 297 298 dmat->_dmamem_alloc = _bus_dmamem_alloc; 299 dmat->_dmamem_free = _bus_dmamem_free; 300 dmat->_dmamem_map = _bus_dmamem_map; 301 dmat->_dmamem_unmap = _bus_dmamem_unmap; 302 dmat->_dmamem_mmap = _bus_dmamem_mmap; 303 304 dmat->_dmatag_subregion = _bus_dmatag_subregion; 305 dmat->_dmatag_destroy = _bus_dmatag_destroy; 306 } 307 308 /* 309 * becc_local_dma_init: 310 * 311 * Initialize the local DMA tag. 312 */ 313 static void 314 becc_local_dma_init(struct becc_softc *sc) 315 { 316 bus_dma_tag_t dmat = &sc->sc_local_dmat; 317 318 dmat->_ranges = NULL; 319 dmat->_nranges = 0; 320 321 dmat->_dmamap_create = _bus_dmamap_create; 322 dmat->_dmamap_destroy = _bus_dmamap_destroy; 323 dmat->_dmamap_load = _bus_dmamap_load; 324 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 325 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 326 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 327 dmat->_dmamap_unload = _bus_dmamap_unload; 328 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 329 dmat->_dmamap_sync_post = NULL; 330 331 dmat->_dmamem_alloc = _bus_dmamem_alloc; 332 dmat->_dmamem_free = _bus_dmamem_free; 333 dmat->_dmamem_map = _bus_dmamem_map; 334 dmat->_dmamem_unmap = _bus_dmamem_unmap; 335 dmat->_dmamem_mmap = _bus_dmamem_mmap; 336 } 337 338 uint32_t 339 becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg) 340 { 341 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 342 343 return (*(volatile uint32_t *) va); 344 } 345 346 void 347 becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val) 348 { 349 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 350 351 *(volatile uint32_t *) va = val; 352 } 353
Indexes created Fri Sep 26 20:09:58 GMT 2025