becc.c revision 1.3
1 /* $NetBSD: becc.c,v 1.3 2003/04/20 17:17:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the ADI Engineering Big Endian 40 * Companion Chip. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #define _ARM32_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 50 #include <arm/xscale/i80200reg.h> 51 #include <arm/xscale/beccreg.h> 52 #include <arm/xscale/beccvar.h> 53 54 /* 55 * Virtual address at which the BECC is mapped. This is filled in 56 * by machine-dependent code. 57 */ 58 vaddr_t becc_vaddr; 59 60 /* 61 * BECC revision number. This is initialized by early bootstrap code. 62 */ 63 int becc_rev; 64 const char *becc_revisions[] = { 65 "<= 7", 66 "8", 67 ">= 9", 68 }; 69 70 /* 71 * There can be only one BECC, so we keep a global pointer to 72 * the softc, so board-specific code can use features of the 73 * BECC without having to have a handle on the softc itself. 74 */ 75 struct becc_softc *becc_softc; 76 77 static int becc_pcibus_print(void *, const char *); 78 79 static int becc_search(struct device *, struct cfdata *, void *); 80 static int becc_print(void *, const char *); 81 82 static void becc_pci_dma_init(struct becc_softc *); 83 static void becc_local_dma_init(struct becc_softc *); 84 85 /* 86 * becc_attach: 87 * 88 * Board-independent attach routine for the BECC. 89 */ 90 void 91 becc_attach(struct becc_softc *sc) 92 { 93 struct pcibus_attach_args pba; 94 uint32_t reg; 95 96 becc_softc = sc; 97 98 /* 99 * Set the AF bit in the BCUMOD since the BECC will honor it. 100 * This allows the BECC to return the requested 4-byte word 101 * first when filling a cache line. 102 */ 103 __asm __volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg)); 104 __asm __volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF)); 105 106 /* 107 * Program the address windows of the PCI core. Note 108 * that PCI master and target cycles must be disabled 109 * while we configure the windows. 110 */ 111 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 112 reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 113 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 114 115 /* 116 * Program the two inbound PCI memory windows. 117 */ 118 becc_pcicore_write(sc, PCI_MAPREG_START + 0, 119 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 120 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 121 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0); 122 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK); 123 124 becc_pcicore_write(sc, PCI_MAPREG_START + 4, 125 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 126 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 127 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4); 128 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK); 129 130 /* 131 * ...and the third on v8 and later. 132 */ 133 if (becc_rev >= BECC_REV_V8) { 134 becc_pcicore_write(sc, PCI_MAPREG_START + 8, 135 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 136 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 137 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8); 138 BECC_CSR_WRITE(BECC_PSTR2, 139 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK); 140 } 141 142 /* 143 * Program the two outbound PCI memory windows. On a 144 * big-endian system, we byte-swap the first window. 145 * The second window is used for STREAM transfers. 146 * 147 * There's a third window on v9 and later, but we don't 148 * use it for anything; program it anyway, just to be 149 * safe. 150 */ 151 #ifdef __ARMEB__ 152 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */ | 153 POMRx_BEE); 154 #else 155 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */); 156 #endif 157 BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */); 158 159 if (becc_rev >= BECC_REV_V9) 160 BECC_CSR_WRITE(BECC_POMR3, 161 sc->sc_owin_xlate[2] /* | POMRx_F32 */); 162 163 /* 164 * Program the PCI I/O window. On a big-endian system, 165 * we do byte-swapping. 166 * 167 * XXX What about STREAM transfers? 168 */ 169 #ifdef __ARMEB__ 170 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate | POIR_BEE); 171 #else 172 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate); 173 #endif 174 175 /* 176 * Configure PCI configuration cycle access. 177 */ 178 BECC_CSR_WRITE(BECC_POCR, 0); 179 180 /* 181 * ...and now reenable PCI access. 182 */ 183 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 184 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 185 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 186 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 187 188 /* Initialize the bus space tags. */ 189 becc_io_bs_init(&sc->sc_pci_iot, sc); 190 becc_mem_bs_init(&sc->sc_pci_memt, sc); 191 192 /* Initialize the PCI chipset tag. */ 193 becc_pci_init(&sc->sc_pci_chipset, sc); 194 195 /* Initialize the DMA tags. */ 196 becc_pci_dma_init(sc); 197 becc_local_dma_init(sc); 198 199 /* 200 * Attach any on-chip peripherals. We used indirect config, since 201 * the BECC is a soft-core with a variety of peripherals, depending 202 * on configuration. 203 */ 204 config_search(becc_search, &sc->sc_dev, NULL); 205 206 /* 207 * Attach the PCI bus. 208 */ 209 pba.pba_busname = "pci"; 210 pba.pba_iot = &sc->sc_pci_iot; 211 pba.pba_memt = &sc->sc_pci_memt; 212 pba.pba_dmat = &sc->sc_pci_dmat; 213 pba.pba_pc = &sc->sc_pci_chipset; 214 pba.pba_bus = 0; 215 pba.pba_bridgetag = NULL; 216 pba.pba_intrswiz = 0; 217 pba.pba_intrtag = 0; 218 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 219 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 220 (void) config_found(&sc->sc_dev, &pba, becc_pcibus_print); 221 } 222 223 /* 224 * becc_pcibus_print: 225 * 226 * Autoconfiguration cfprint routine when attaching 227 * to the "pcibus" attribute. 228 */ 229 static int 230 becc_pcibus_print(void *aux, const char *pnp) 231 { 232 struct pcibus_attach_args *pba = aux; 233 234 if (pnp) 235 printf("%s at %s", pba->pba_busname, pnp); 236 237 printf(" bus %d", pba->pba_bus); 238 239 return (UNCONF); 240 } 241 242 /* 243 * becc_search: 244 * 245 * Indirect autoconfiguration glue for BECC. 246 */ 247 static int 248 becc_search(struct device *parent, struct cfdata *cf, void *aux) 249 { 250 struct becc_softc *sc = (void *) parent; 251 struct becc_attach_args ba; 252 253 ba.ba_dmat = &sc->sc_local_dmat; 254 255 if (config_match(parent, cf, &ba) > 0) 256 config_attach(parent, cf, &ba, becc_print); 257 258 return (0); 259 } 260 261 /* 262 * becc_print: 263 * 264 * Autoconfiguration cfprint routine when attaching 265 * to the BECC. 266 */ 267 static int 268 becc_print(void *aux, const char *pnp) 269 { 270 271 return (UNCONF); 272 } 273 274 /* 275 * becc_pci_dma_init: 276 * 277 * Initialize the PCI DMA tag. 278 */ 279 static void 280 becc_pci_dma_init(struct becc_softc *sc) 281 { 282 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 283 struct arm32_dma_range *dr = sc->sc_pci_dma_range; 284 int i = 0; 285 286 /* 287 * If we have the 128MB window, put it first, since it 288 * will always cover the entire memory range. 289 */ 290 if (becc_rev >= BECC_REV_V8) { 291 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate; 292 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base; 293 dr[i].dr_len = (128U * 1024 * 1024); 294 i++; 295 } 296 297 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate; 298 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base; 299 dr[i].dr_len = (32U * 1024 * 1024); 300 i++; 301 302 dr[i].dr_sysbase = sc->sc_iwin[1].iwin_xlate; 303 dr[i].dr_busbase = sc->sc_iwin[1].iwin_base; 304 dr[i].dr_len = (32U * 1024 * 1024); 305 i++; 306 307 dmat->_ranges = dr; 308 dmat->_nranges = i; 309 310 dmat->_dmamap_create = _bus_dmamap_create; 311 dmat->_dmamap_destroy = _bus_dmamap_destroy; 312 dmat->_dmamap_load = _bus_dmamap_load; 313 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 314 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 315 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 316 dmat->_dmamap_unload = _bus_dmamap_unload; 317 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 318 dmat->_dmamap_sync_post = NULL; 319 320 dmat->_dmamem_alloc = _bus_dmamem_alloc; 321 dmat->_dmamem_free = _bus_dmamem_free; 322 dmat->_dmamem_map = _bus_dmamem_map; 323 dmat->_dmamem_unmap = _bus_dmamem_unmap; 324 dmat->_dmamem_mmap = _bus_dmamem_mmap; 325 } 326 327 /* 328 * becc_local_dma_init: 329 * 330 * Initialize the local DMA tag. 331 */ 332 static void 333 becc_local_dma_init(struct becc_softc *sc) 334 { 335 bus_dma_tag_t dmat = &sc->sc_local_dmat; 336 337 dmat->_ranges = NULL; 338 dmat->_nranges = 0; 339 340 dmat->_dmamap_create = _bus_dmamap_create; 341 dmat->_dmamap_destroy = _bus_dmamap_destroy; 342 dmat->_dmamap_load = _bus_dmamap_load; 343 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 344 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 345 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 346 dmat->_dmamap_unload = _bus_dmamap_unload; 347 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 348 dmat->_dmamap_sync_post = NULL; 349 350 dmat->_dmamem_alloc = _bus_dmamem_alloc; 351 dmat->_dmamem_free = _bus_dmamem_free; 352 dmat->_dmamem_map = _bus_dmamem_map; 353 dmat->_dmamem_unmap = _bus_dmamem_unmap; 354 dmat->_dmamem_mmap = _bus_dmamem_mmap; 355 } 356 357 uint32_t 358 becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg) 359 { 360 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 361 362 return (*(__volatile uint32_t *) va); 363 } 364 365 void 366 becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val) 367 { 368 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 369 370 *(__volatile uint32_t *) va = val; 371 } 372
Indexes created Wed Sep 24 14:09:57 GMT 2025