becc.c revision 1.7
1 /* $NetBSD: becc.c,v 1.7 2003/07/15 00:24:52 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the ADI Engineering Big Endian 40 * Companion Chip. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: becc.c,v 1.7 2003/07/15 00:24:52 lukem Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #define _ARM32_BUS_DMA_PRIVATE 51 #include <machine/bus.h> 52 53 #include <arm/xscale/i80200reg.h> 54 #include <arm/xscale/beccreg.h> 55 #include <arm/xscale/beccvar.h> 56 57 /* 58 * Virtual address at which the BECC is mapped. This is filled in 59 * by machine-dependent code. 60 */ 61 vaddr_t becc_vaddr; 62 63 /* 64 * BECC revision number. This is initialized by early bootstrap code. 65 */ 66 int becc_rev; 67 const char *becc_revisions[] = { 68 "<= 7", 69 "8", 70 ">= 9", 71 }; 72 73 /* 74 * There can be only one BECC, so we keep a global pointer to 75 * the softc, so board-specific code can use features of the 76 * BECC without having to have a handle on the softc itself. 77 */ 78 struct becc_softc *becc_softc; 79 80 static int becc_pcibus_print(void *, const char *); 81 82 static int becc_search(struct device *, struct cfdata *, void *); 83 static int becc_print(void *, const char *); 84 85 static void becc_pci_dma_init(struct becc_softc *); 86 static void becc_local_dma_init(struct becc_softc *); 87 88 /* 89 * becc_attach: 90 * 91 * Board-independent attach routine for the BECC. 92 */ 93 void 94 becc_attach(struct becc_softc *sc) 95 { 96 struct pcibus_attach_args pba; 97 uint32_t reg; 98 99 becc_softc = sc; 100 101 /* 102 * Set the AF bit in the BCUMOD since the BECC will honor it. 103 * This allows the BECC to return the requested 4-byte word 104 * first when filling a cache line. 105 */ 106 __asm __volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg)); 107 __asm __volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF)); 108 109 /* 110 * Program the address windows of the PCI core. Note 111 * that PCI master and target cycles must be disabled 112 * while we configure the windows. 113 */ 114 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 115 reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 116 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 117 118 /* 119 * Program the two inbound PCI memory windows. 120 */ 121 becc_pcicore_write(sc, PCI_MAPREG_START + 0, 122 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 123 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 124 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0); 125 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK); 126 127 becc_pcicore_write(sc, PCI_MAPREG_START + 4, 128 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 129 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 130 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4); 131 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK); 132 133 /* 134 * ...and the third on v8 and later. 135 */ 136 if (becc_rev >= BECC_REV_V8) { 137 becc_pcicore_write(sc, PCI_MAPREG_START + 8, 138 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT | 139 PCI_MAPREG_MEM_PREFETCHABLE_MASK); 140 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8); 141 BECC_CSR_WRITE(BECC_PSTR2, 142 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK); 143 } 144 145 /* 146 * Program the two outbound PCI memory windows. 147 * NOTE: WE DO NOT BYTE-SWAP OUTBOUND WINDOWS IN BIG-ENDIAN 148 * MODE. I know this seems counter-intuitive, but that's 149 * how it is. 150 * 151 * There's a third window on v9 and later, but we don't 152 * use it for anything; program it anyway, just to be 153 * safe. 154 */ 155 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */); 156 BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */); 157 158 if (becc_rev >= BECC_REV_V9) 159 BECC_CSR_WRITE(BECC_POMR3, 160 sc->sc_owin_xlate[2] /* | POMRx_F32 */); 161 162 /* 163 * Program the PCI I/O window. See note above about byte-swapping. 164 * 165 * XXX What about STREAM transfers? 166 */ 167 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate); 168 169 /* 170 * Configure PCI configuration cycle access. 171 */ 172 BECC_CSR_WRITE(BECC_POCR, 0); 173 174 /* 175 * ...and now reenable PCI access. 176 */ 177 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG); 178 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 179 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 180 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg); 181 182 /* Initialize the bus space tags. */ 183 becc_io_bs_init(&sc->sc_pci_iot, sc); 184 becc_mem_bs_init(&sc->sc_pci_memt, sc); 185 186 /* Initialize the PCI chipset tag. */ 187 becc_pci_init(&sc->sc_pci_chipset, sc); 188 189 /* Initialize the DMA tags. */ 190 becc_pci_dma_init(sc); 191 becc_local_dma_init(sc); 192 193 /* 194 * Attach any on-chip peripherals. We used indirect config, since 195 * the BECC is a soft-core with a variety of peripherals, depending 196 * on configuration. 197 */ 198 config_search(becc_search, &sc->sc_dev, NULL); 199 200 /* 201 * Attach the PCI bus. 202 */ 203 pba.pba_busname = "pci"; 204 pba.pba_iot = &sc->sc_pci_iot; 205 pba.pba_memt = &sc->sc_pci_memt; 206 pba.pba_dmat = &sc->sc_pci_dmat; 207 pba.pba_dmat64 = NULL; 208 pba.pba_pc = &sc->sc_pci_chipset; 209 pba.pba_bus = 0; 210 pba.pba_bridgetag = NULL; 211 pba.pba_intrswiz = 0; 212 pba.pba_intrtag = 0; 213 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 214 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 215 (void) config_found(&sc->sc_dev, &pba, becc_pcibus_print); 216 } 217 218 /* 219 * becc_pcibus_print: 220 * 221 * Autoconfiguration cfprint routine when attaching 222 * to the "pcibus" attribute. 223 */ 224 static int 225 becc_pcibus_print(void *aux, const char *pnp) 226 { 227 struct pcibus_attach_args *pba = aux; 228 229 if (pnp) 230 aprint_normal("%s at %s", pba->pba_busname, pnp); 231 232 aprint_normal(" bus %d", pba->pba_bus); 233 234 return (UNCONF); 235 } 236 237 /* 238 * becc_search: 239 * 240 * Indirect autoconfiguration glue for BECC. 241 */ 242 static int 243 becc_search(struct device *parent, struct cfdata *cf, void *aux) 244 { 245 struct becc_softc *sc = (void *) parent; 246 struct becc_attach_args ba; 247 248 ba.ba_dmat = &sc->sc_local_dmat; 249 250 if (config_match(parent, cf, &ba) > 0) 251 config_attach(parent, cf, &ba, becc_print); 252 253 return (0); 254 } 255 256 /* 257 * becc_print: 258 * 259 * Autoconfiguration cfprint routine when attaching 260 * to the BECC. 261 */ 262 static int 263 becc_print(void *aux, const char *pnp) 264 { 265 266 return (UNCONF); 267 } 268 269 /* 270 * becc_pci_dma_init: 271 * 272 * Initialize the PCI DMA tag. 273 */ 274 static void 275 becc_pci_dma_init(struct becc_softc *sc) 276 { 277 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 278 struct arm32_dma_range *dr = sc->sc_pci_dma_range; 279 int i = 0; 280 281 /* 282 * If we have the 128MB window, put it first, since it 283 * will always cover the entire memory range. 284 */ 285 if (becc_rev >= BECC_REV_V8) { 286 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate; 287 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base; 288 dr[i].dr_len = (128U * 1024 * 1024); 289 i++; 290 } 291 292 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate; 293 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base; 294 dr[i].dr_len = (32U * 1024 * 1024); 295 i++; 296 297 dr[i].dr_sysbase = sc->sc_iwin[1].iwin_xlate; 298 dr[i].dr_busbase = sc->sc_iwin[1].iwin_base; 299 dr[i].dr_len = (32U * 1024 * 1024); 300 i++; 301 302 dmat->_ranges = dr; 303 dmat->_nranges = i; 304 305 dmat->_dmamap_create = _bus_dmamap_create; 306 dmat->_dmamap_destroy = _bus_dmamap_destroy; 307 dmat->_dmamap_load = _bus_dmamap_load; 308 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 309 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 310 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 311 dmat->_dmamap_unload = _bus_dmamap_unload; 312 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 313 dmat->_dmamap_sync_post = NULL; 314 315 dmat->_dmamem_alloc = _bus_dmamem_alloc; 316 dmat->_dmamem_free = _bus_dmamem_free; 317 dmat->_dmamem_map = _bus_dmamem_map; 318 dmat->_dmamem_unmap = _bus_dmamem_unmap; 319 dmat->_dmamem_mmap = _bus_dmamem_mmap; 320 } 321 322 /* 323 * becc_local_dma_init: 324 * 325 * Initialize the local DMA tag. 326 */ 327 static void 328 becc_local_dma_init(struct becc_softc *sc) 329 { 330 bus_dma_tag_t dmat = &sc->sc_local_dmat; 331 332 dmat->_ranges = NULL; 333 dmat->_nranges = 0; 334 335 dmat->_dmamap_create = _bus_dmamap_create; 336 dmat->_dmamap_destroy = _bus_dmamap_destroy; 337 dmat->_dmamap_load = _bus_dmamap_load; 338 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 339 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 340 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 341 dmat->_dmamap_unload = _bus_dmamap_unload; 342 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 343 dmat->_dmamap_sync_post = NULL; 344 345 dmat->_dmamem_alloc = _bus_dmamem_alloc; 346 dmat->_dmamem_free = _bus_dmamem_free; 347 dmat->_dmamem_map = _bus_dmamem_map; 348 dmat->_dmamem_unmap = _bus_dmamem_unmap; 349 dmat->_dmamem_mmap = _bus_dmamem_mmap; 350 } 351 352 uint32_t 353 becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg) 354 { 355 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 356 357 return (*(__volatile uint32_t *) va); 358 } 359 360 void 361 becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val) 362 { 363 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg; 364 365 *(__volatile uint32_t *) va = val; 366 } 367
Indexes created Thu Sep 25 08:09:54 GMT 2025