i80200_icu.c revision 1.3.4.4
1 1.3.4.4 nathanw /* $NetBSD: i80200_icu.c,v 1.3.4.4 2002/08/01 02:41:19 nathanw Exp $ */ 2 1.3.4.2 nathanw 3 1.3.4.2 nathanw /* 4 1.3.4.2 nathanw * Copyright (c) 2002 Wasabi Systems, Inc. 5 1.3.4.2 nathanw * All rights reserved. 6 1.3.4.2 nathanw * 7 1.3.4.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.3.4.2 nathanw * 9 1.3.4.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.3.4.2 nathanw * modification, are permitted provided that the following conditions 11 1.3.4.2 nathanw * are met: 12 1.3.4.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.3.4.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.3.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.3.4.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.3.4.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.3.4.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.3.4.2 nathanw * must display the following acknowledgement: 19 1.3.4.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.3.4.2 nathanw * Wasabi Systems, Inc. 21 1.3.4.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.3.4.2 nathanw * or promote products derived from this software without specific prior 23 1.3.4.2 nathanw * written permission. 24 1.3.4.2 nathanw * 25 1.3.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.3.4.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.3.4.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.3.4.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.3.4.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.3.4.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.3.4.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.3.4.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.3.4.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.3.4.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.3.4.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.3.4.2 nathanw */ 37 1.3.4.2 nathanw 38 1.3.4.2 nathanw /* 39 1.3.4.2 nathanw * Intel i80200 Interrupt Controller Unit support. 40 1.3.4.2 nathanw */ 41 1.3.4.2 nathanw 42 1.3.4.2 nathanw #include <sys/param.h> 43 1.3.4.2 nathanw #include <sys/systm.h> 44 1.3.4.2 nathanw 45 1.3.4.2 nathanw #include <arm/cpufunc.h> 46 1.3.4.2 nathanw 47 1.3.4.2 nathanw #include <arm/xscale/i80200reg.h> 48 1.3.4.2 nathanw #include <arm/xscale/i80200var.h> 49 1.3.4.2 nathanw 50 1.3.4.2 nathanw /* Software shadow copy of INTCTL. */ 51 1.3.4.2 nathanw static __volatile uint32_t intctl; 52 1.3.4.2 nathanw 53 1.3.4.2 nathanw /* Pointer to board-specific external IRQ dispatcher. */ 54 1.3.4.2 nathanw void (*i80200_extirq_dispatch)(struct clockframe *); 55 1.3.4.2 nathanw 56 1.3.4.2 nathanw static void 57 1.3.4.2 nathanw i80200_default_extirq_dispatch(struct clockframe *framep) 58 1.3.4.2 nathanw { 59 1.3.4.2 nathanw 60 1.3.4.2 nathanw panic("external IRQ with no dispatch routine"); 61 1.3.4.2 nathanw } 62 1.3.4.2 nathanw 63 1.3.4.2 nathanw /* 64 1.3.4.3 nathanw * i80200_icu_init: 65 1.3.4.2 nathanw * 66 1.3.4.2 nathanw * Initialize the i80200 ICU. 67 1.3.4.2 nathanw */ 68 1.3.4.2 nathanw void 69 1.3.4.3 nathanw i80200_icu_init(void) 70 1.3.4.2 nathanw { 71 1.3.4.2 nathanw 72 1.3.4.2 nathanw /* Disable all interrupt sources. */ 73 1.3.4.2 nathanw intctl = 0; 74 1.3.4.2 nathanw __asm __volatile("mcr p13, 0, %0, c0, c0" 75 1.3.4.2 nathanw : 76 1.3.4.2 nathanw : "r" (intctl)); 77 1.3.4.2 nathanw 78 1.3.4.2 nathanw /* Steer PMU and BMU to IRQ. */ 79 1.3.4.4 nathanw __asm __volatile("mcr p13, 0, %0, c8, c0" 80 1.3.4.2 nathanw : 81 1.3.4.2 nathanw : "r" (0)); 82 1.3.4.2 nathanw 83 1.3.4.2 nathanw i80200_extirq_dispatch = i80200_default_extirq_dispatch; 84 1.3.4.2 nathanw } 85 1.3.4.2 nathanw 86 1.3.4.2 nathanw /* 87 1.3.4.2 nathanw * i80200_intr_enable: 88 1.3.4.2 nathanw * 89 1.3.4.2 nathanw * Enable an interrupt source in the i80200 ICU. 90 1.3.4.2 nathanw */ 91 1.3.4.2 nathanw void 92 1.3.4.2 nathanw i80200_intr_enable(uint32_t intr) 93 1.3.4.2 nathanw { 94 1.3.4.2 nathanw u_int oldirqstate; 95 1.3.4.2 nathanw 96 1.3.4.2 nathanw oldirqstate = disable_interrupts(I32_bit|F32_bit); 97 1.3.4.2 nathanw 98 1.3.4.2 nathanw intctl |= intr; 99 1.3.4.2 nathanw __asm __volatile("mcr p13, 0, %0, c0, c0" 100 1.3.4.2 nathanw : 101 1.3.4.2 nathanw : "r" (intctl)); 102 1.3.4.2 nathanw 103 1.3.4.2 nathanw restore_interrupts(oldirqstate); 104 1.3.4.2 nathanw } 105 1.3.4.2 nathanw 106 1.3.4.2 nathanw /* 107 1.3.4.2 nathanw * i80200_intr_disable: 108 1.3.4.2 nathanw * 109 1.3.4.2 nathanw * Disable an interrupt source in the i80200 ICU. 110 1.3.4.2 nathanw */ 111 1.3.4.2 nathanw void 112 1.3.4.2 nathanw i80200_intr_disable(uint32_t intr) 113 1.3.4.2 nathanw { 114 1.3.4.2 nathanw u_int oldirqstate; 115 1.3.4.2 nathanw 116 1.3.4.2 nathanw oldirqstate = disable_interrupts(I32_bit|F32_bit); 117 1.3.4.2 nathanw 118 1.3.4.2 nathanw intctl &= ~intr; 119 1.3.4.2 nathanw __asm __volatile("mcr p13, 0, %0, c0, c0" 120 1.3.4.2 nathanw : 121 1.3.4.2 nathanw : "r" (intctl)); 122 1.3.4.2 nathanw 123 1.3.4.2 nathanw restore_interrupts(oldirqstate); 124 1.3.4.2 nathanw } 125
Indexes created Sat Oct 25 10:09:55 GMT 2025