i80200_icu.c revision 1.1 1 /* $NetBSD: i80200_icu.c,v 1.1 2002/01/23 21:00:12 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Intel i80200 Interrupt Controller Unit support.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44
45 #include <arm/cpufunc.h>
46
47 #include <arm/xscale/i80200reg.h>
48 #include <arm/xscale/i80200var.h>
49
50 /* Software shadow copy of INTCTL. */
51 static uint32_t intctl;
52
53 /*
54 * i80200_intr_init:
55 *
56 * Initialize the i80200 ICU.
57 */
58 void
59 i80200_intr_init(void)
60 {
61
62 /* Disable all interrupt sources. */
63 intctl = 0;
64 __asm __volatile("mcr p13, 0, %0, c0, c0"
65 :
66 : "r" (intctl));
67
68 /* Steer PMU and BMU to IRQ. */
69 __asm __volatile("mcr p13, 0, %0, c2, c0"
70 :
71 : "r" (0));
72 }
73
74 /*
75 * i80200_intr_enable:
76 *
77 * Enable an interrupt source in the i80200 ICU.
78 */
79 void
80 i80200_intr_enable(uint32_t intr)
81 {
82 u_int oldirqstate;
83
84 oldirqstate = disable_interrupts(I32_bit|F32_bit);
85
86 intctl |= intr;
87 __asm __volatile("mcr p13, 0, %0, c0, c0"
88 :
89 : "r" (intctl));
90
91 restore_interrupts(oldirqstate);
92 }
93
94 /*
95 * i80200_intr_disable:
96 *
97 * Disable an interrupt source in the i80200 ICU.
98 */
99 void
100 i80200_intr_disable(uint32_t intr)
101 {
102 u_int oldirqstate;
103
104 oldirqstate = disable_interrupts(I32_bit|F32_bit);
105
106 intctl &= ~intr;
107 __asm __volatile("mcr p13, 0, %0, c0, c0"
108 :
109 : "r" (intctl));
110
111 restore_interrupts(oldirqstate);
112 }
113