i80200_icu.c revision 1.5 1 /* $NetBSD: i80200_icu.c,v 1.5 2002/06/25 19:39:51 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Intel i80200 Interrupt Controller Unit support.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44
45 #include <arm/cpufunc.h>
46
47 #include <arm/xscale/i80200reg.h>
48 #include <arm/xscale/i80200var.h>
49
50 /* Software shadow copy of INTCTL. */
51 static __volatile uint32_t intctl;
52
53 /* Pointer to board-specific external IRQ dispatcher. */
54 void (*i80200_extirq_dispatch)(struct clockframe *);
55
56 static void
57 i80200_default_extirq_dispatch(struct clockframe *framep)
58 {
59
60 panic("external IRQ with no dispatch routine");
61 }
62
63 /*
64 * i80200_icu_init:
65 *
66 * Initialize the i80200 ICU.
67 */
68 void
69 i80200_icu_init(void)
70 {
71
72 /* Disable all interrupt sources. */
73 intctl = 0;
74 __asm __volatile("mcr p13, 0, %0, c0, c0"
75 :
76 : "r" (intctl));
77
78 /* Steer PMU and BMU to IRQ. */
79 __asm __volatile("mcr p13, 0, %0, c8, c0"
80 :
81 : "r" (0));
82
83 i80200_extirq_dispatch = i80200_default_extirq_dispatch;
84 }
85
86 /*
87 * i80200_intr_enable:
88 *
89 * Enable an interrupt source in the i80200 ICU.
90 */
91 void
92 i80200_intr_enable(uint32_t intr)
93 {
94 u_int oldirqstate;
95
96 oldirqstate = disable_interrupts(I32_bit|F32_bit);
97
98 intctl |= intr;
99 __asm __volatile("mcr p13, 0, %0, c0, c0"
100 :
101 : "r" (intctl));
102
103 restore_interrupts(oldirqstate);
104 }
105
106 /*
107 * i80200_intr_disable:
108 *
109 * Disable an interrupt source in the i80200 ICU.
110 */
111 void
112 i80200_intr_disable(uint32_t intr)
113 {
114 u_int oldirqstate;
115
116 oldirqstate = disable_interrupts(I32_bit|F32_bit);
117
118 intctl &= ~intr;
119 __asm __volatile("mcr p13, 0, %0, c0, c0"
120 :
121 : "r" (intctl));
122
123 restore_interrupts(oldirqstate);
124 }
125