i80312.c revision 1.1
1 /* $NetBSD: i80312.c,v 1.1 2001/11/09 03:27:51 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <arm/xscale/i80312reg.h> 49 #include <arm/xscale/i80312var.h> 50 51 #include <dev/pci/ppbreg.h> 52 53 /* 54 * Statically-allocated bus_space stucture used to access the 55 * i80312's own registers. 56 */ 57 struct bus_space i80312_bs_tag; 58 59 int i80312_pcibus_print(void *, const char *); 60 61 /* 62 * i80312_attach: 63 * 64 * Board-independent attach routine for the i80312. 65 */ 66 void 67 i80312_attach(struct i80312_softc *sc) 68 { 69 struct pcibus_attach_args pba; 70 uint32_t atucr; 71 pcireg_t preg; 72 73 /* 74 * Slice off some useful subregion handles. 75 */ 76 77 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE, 78 I80312_PPB_SIZE, &sc->sc_ppb_sh)) 79 panic("%s: unable to subregion PPB registers\n", 80 sc->sc_dev.dv_xname); 81 82 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE, 83 I80312_ATU_SIZE, &sc->sc_atu_sh)) 84 panic("%s: unable to subregion ATU registers\n", 85 sc->sc_dev.dv_xname); 86 87 /* 88 * Disable the private space decode. 89 */ 90 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh, 91 I80312_PPB_SDER); 92 sc->sc_sder &= ~PPB_SDER_PMSE; 93 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, 94 I80312_PPB_SDER, sc->sc_sder); 95 96 /* 97 * Program the Secondary ID Select register. 98 */ 99 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, 100 I80312_PPB_SISR, sc->sc_sisr); 101 102 /* 103 * Program the private secondary bus spaces. 104 */ 105 if (sc->sc_privmem_size && sc->sc_privio_size) { 106 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR, 107 (sc->sc_privio_base >> 12) << 4); 108 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR, 109 ((sc->sc_privio_base + sc->sc_privio_size - 1) 110 >> 12) << 4); 111 112 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR, 113 (sc->sc_privmem_base >> 20) << 4); 114 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR, 115 ((sc->sc_privmem_base + sc->sc_privmem_size - 1) 116 >> 20) << 4); 117 118 sc->sc_sder |= PPB_SDER_PMSE; 119 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER, 120 sc->sc_sder); 121 } else if (sc->sc_privmem_size || sc->sc_privio_size) { 122 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n", 123 sc->sc_dev.dv_xname, sc->sc_privmem_size, 124 sc->sc_privio_size); 125 printf("%s: private bus spaces not enabled\n", 126 sc->sc_dev.dv_xname); 127 } 128 129 /* 130 * Program the Primary Inbound window. 131 */ 132 if (sc->sc_is_host) 133 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 134 PCI_MAPREG_START, sc->sc_pin_base); 135 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 136 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size)); 137 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 138 I80312_ATU_PIATV, sc->sc_pin_xlate); 139 140 /* 141 * Program the Secondary Inbound window. 142 */ 143 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 144 I80312_ATU_SIAM, sc->sc_sin_base); 145 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 146 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size)); 147 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 148 I80312_ATU_SIATV, sc->sc_sin_xlate); 149 150 /* 151 * Clear: 152 * 153 * Primary Outbound ATU Enable 154 * Secondary Outbound ATU Enable 155 * Secondary Direct Addressing Select 156 * Direct Addressing Enable 157 */ 158 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR); 159 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE); 160 161 /* 162 * Program the Primary Outbound windows. 163 */ 164 if (sc->sc_pmemout_size) 165 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 166 I80312_ATU_POMWV, sc->sc_pmemout_base); 167 if (sc->sc_pioout_size) 168 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 169 I80312_ATU_POIOWV, sc->sc_pioout_base); 170 if (sc->sc_pmemout_size || sc->sc_pioout_size) 171 atucr |= ATU_ACR_POAE; 172 173 /* 174 * Program the Secondary Outbound windows. 175 */ 176 if (sc->sc_smemout_size) 177 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 178 I80312_ATU_SOMWV, sc->sc_smemout_base); 179 if (sc->sc_sioout_size) 180 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 181 I80312_ATU_SOIOWV, sc->sc_sioout_base); 182 if (sc->sc_smemout_size || sc->sc_sioout_size) 183 atucr |= ATU_ACR_SOAE; 184 185 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr); 186 187 /* 188 * Enable bus mastering, memory access, SERR, and parity 189 * checking on the ATU. 190 */ 191 if (sc->sc_is_host) { 192 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 193 PCI_COMMAND_STATUS_REG); 194 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 195 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 196 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 197 PCI_COMMAND_STATUS_REG, preg); 198 } 199 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 200 I80312_ATU_SACS); 201 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 202 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 203 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 204 I80312_ATU_SACS, preg); 205 206 /* 207 * Configure the bridge. If we're a host, set the primary 208 * bus to bus #0 and the secondary bus to bus #1. We also 209 * set the PPB's subordinate bus # to 1. It will be fixed 210 * up later when we fully configure the bus. 211 * 212 * If we're a slave, just use the bus #'s that the host 213 * provides. 214 */ 215 if (sc->sc_is_host) { 216 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh, 217 PPB_REG_BUSINFO, 218 (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) | 219 (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) | 220 (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT)); 221 } 222 223 /* 224 * Initialize the bus space and DMA tags and the PCI chipset tag. 225 */ 226 i80312_io_bs_init(&sc->sc_pci_iot, sc); 227 i80312_mem_bs_init(&sc->sc_pci_memt, sc); 228 #if 0 229 i80312_pci_dma_init(&sc->sc_pci_dmat, sc); 230 #endif 231 i80312_pci_init(&sc->sc_pci_chipset, sc); 232 233 /* 234 * Attach the PCI bus. Note that if we're a host, we can 235 * safely probe for devices on the Primary bus. If we're 236 * a slave, we must limit ourselves to our Secondary bus, 237 * specifically, the private devices on the Secondary bus. 238 */ 239 pba.pba_busname = "pci"; 240 pba.pba_iot = &sc->sc_pci_iot; 241 pba.pba_memt = &sc->sc_pci_memt; 242 pba.pba_dmat = &sc->sc_pci_dmat; 243 pba.pba_pc = &sc->sc_pci_chipset; 244 pba.pba_bus = 1; /* XXX for now */ 245 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 246 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 247 (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); 248 } 249 250 /* 251 * i80312_pcibus_print: 252 * 253 * Autoconfiguration cfprint routine when attaching 254 * to the "pcibus" attribute. 255 */ 256 int 257 i80312_pcibus_print(void *aux, const char *pnp) 258 { 259 struct pcibus_attach_args *pba = aux; 260 261 if (pnp) 262 printf("%s at %s", pba->pba_busname, pnp); 263 264 printf(" bus %d", pba->pba_bus); 265 266 return (UNCONF); 267 } 268
Indexes created Wed Sep 24 14:09:57 GMT 2025