i80312.c revision 1.15
1 /* $NetBSD: i80312.c,v 1.15 2003/07/15 00:24:53 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.15 2003/07/15 00:24:53 lukem Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #define _ARM32_BUS_DMA_PRIVATE 50 #include <machine/bus.h> 51 52 #include <arm/xscale/i80312reg.h> 53 #include <arm/xscale/i80312var.h> 54 55 #include <dev/pci/ppbreg.h> 56 57 /* 58 * Statically-allocated bus_space stucture used to access the 59 * i80312's own registers. 60 */ 61 struct bus_space i80312_bs_tag; 62 63 /* 64 * There can be only one i80312, so we keep a global pointer to 65 * the softc, so board-specific code can use features of the 66 * i80312 without having to have a handle on the softc itself. 67 */ 68 struct i80312_softc *i80312_softc; 69 70 static void i80312_pci_dma_init(struct i80312_softc *); 71 72 static int i80312_pcibus_print(void *, const char *); 73 74 /* 75 * i80312_attach: 76 * 77 * Board-independent attach routine for the i80312. 78 */ 79 void 80 i80312_attach(struct i80312_softc *sc) 81 { 82 struct pcibus_attach_args pba; 83 uint32_t atucr; 84 pcireg_t preg; 85 86 i80312_softc = sc; 87 88 /* 89 * Slice off some useful subregion handles. 90 */ 91 92 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE, 93 I80312_PPB_SIZE, &sc->sc_ppb_sh)) 94 panic("%s: unable to subregion PPB registers", 95 sc->sc_dev.dv_xname); 96 97 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE, 98 I80312_ATU_SIZE, &sc->sc_atu_sh)) 99 panic("%s: unable to subregion ATU registers", 100 sc->sc_dev.dv_xname); 101 102 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_INTC_BASE, 103 I80312_INTC_SIZE, &sc->sc_intc_sh)) 104 panic("%s: unable to subregion INTC registers", 105 sc->sc_dev.dv_xname); 106 107 /* We expect the Memory Controller to be already sliced off. */ 108 109 /* 110 * Disable the private space decode. 111 */ 112 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh, 113 I80312_PPB_SDER); 114 sc->sc_sder &= ~PPB_SDER_PMSE; 115 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, 116 I80312_PPB_SDER, sc->sc_sder); 117 118 /* 119 * Program the Secondary ID Select register. 120 */ 121 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, 122 I80312_PPB_SISR, sc->sc_sisr); 123 124 /* 125 * Program the private secondary bus spaces. 126 */ 127 if (sc->sc_privmem_size && sc->sc_privio_size) { 128 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR, 129 (sc->sc_privio_base >> 12) << 4); 130 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR, 131 ((sc->sc_privio_base + sc->sc_privio_size - 1) 132 >> 12) << 4); 133 134 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR, 135 (sc->sc_privmem_base >> 20) << 4); 136 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR, 137 ((sc->sc_privmem_base + sc->sc_privmem_size - 1) 138 >> 20) << 4); 139 140 sc->sc_sder |= PPB_SDER_PMSE; 141 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER, 142 sc->sc_sder); 143 } else if (sc->sc_privmem_size || sc->sc_privio_size) { 144 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n", 145 sc->sc_dev.dv_xname, sc->sc_privmem_size, 146 sc->sc_privio_size); 147 printf("%s: private bus spaces not enabled\n", 148 sc->sc_dev.dv_xname); 149 } 150 151 /* 152 * Program the Primary Inbound window. 153 */ 154 if (sc->sc_is_host) 155 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 156 PCI_MAPREG_START, sc->sc_pin_base); 157 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 158 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size)); 159 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 160 I80312_ATU_PIATV, sc->sc_pin_xlate); 161 162 /* 163 * Program the Secondary Inbound window. 164 */ 165 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 166 I80312_ATU_SIAM, sc->sc_sin_base); 167 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 168 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size)); 169 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 170 I80312_ATU_SIATV, sc->sc_sin_xlate); 171 172 /* 173 * Mask (disable) the ATU interrupt sources. 174 * XXX May want to revisit this if we encounter 175 * XXX an application that wants it. 176 */ 177 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 178 I80312_ATU_PAIM, 179 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 180 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM | 181 ATU_AIM_PSTIM); 182 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 183 I80312_ATU_SAIM, 184 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 185 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM); 186 187 /* 188 * Clear: 189 * 190 * Primary Outbound ATU Enable 191 * Secondary Outbound ATU Enable 192 * Secondary Direct Addressing Select 193 * Direct Addressing Enable 194 */ 195 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR); 196 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE); 197 198 /* 199 * Program the Primary Outbound windows. 200 */ 201 if (sc->sc_pmemout_size) 202 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 203 I80312_ATU_POMWV, sc->sc_pmemout_base); 204 if (sc->sc_pioout_size) 205 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 206 I80312_ATU_POIOWV, sc->sc_pioout_base); 207 if (sc->sc_pmemout_size || sc->sc_pioout_size) 208 atucr |= ATU_ACR_POAE; 209 210 /* 211 * Program the Secondary Outbound windows. 212 */ 213 if (sc->sc_smemout_size) 214 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 215 I80312_ATU_SOMWV, sc->sc_smemout_base); 216 if (sc->sc_sioout_size) 217 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 218 I80312_ATU_SOIOWV, sc->sc_sioout_base); 219 if (sc->sc_smemout_size || sc->sc_sioout_size) 220 atucr |= ATU_ACR_SOAE; 221 222 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr); 223 224 /* 225 * Enable bus mastering, memory access, SERR, and parity 226 * checking on the ATU. 227 */ 228 if (sc->sc_is_host) { 229 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 230 PCI_COMMAND_STATUS_REG); 231 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 232 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 233 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 234 PCI_COMMAND_STATUS_REG, preg); 235 } 236 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 237 I80312_ATU_SACS); 238 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 239 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 240 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 241 I80312_ATU_SACS, preg); 242 243 /* 244 * Configure the bridge. If we're a host, set the primary 245 * bus to bus #0 and the secondary bus to bus #1. We also 246 * set the PPB's subordinate bus # to 1. It will be fixed 247 * up later when we fully configure the bus. 248 * 249 * If we're a slave, just use the bus #'s that the host 250 * provides. 251 */ 252 if (sc->sc_is_host) { 253 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh, 254 PPB_REG_BUSINFO, 255 (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) | 256 (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) | 257 (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT)); 258 } 259 260 /* Initialize the bus space tags. */ 261 i80312_io_bs_init(&sc->sc_pci_iot, sc); 262 i80312_mem_bs_init(&sc->sc_pci_memt, sc); 263 264 /* Initialize the PCI chipset tag. */ 265 i80312_pci_init(&sc->sc_pci_chipset, sc); 266 267 /* Initialize the DMA tags. */ 268 i80312_pci_dma_init(sc); 269 270 /* 271 * Attach the PCI bus. 272 * 273 * Note: We only probe the Secondary PCI bus, since that 274 * is the only bus on which we can have a private device 275 * space. 276 */ 277 preg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 278 pba.pba_busname = "pci"; 279 pba.pba_iot = &sc->sc_pci_iot; 280 pba.pba_memt = &sc->sc_pci_memt; 281 pba.pba_dmat = &sc->sc_pci_dmat; 282 pba.pba_dmat64 = NULL; 283 pba.pba_pc = &sc->sc_pci_chipset; 284 pba.pba_bus = PPB_BUSINFO_SECONDARY(preg); 285 pba.pba_bridgetag = NULL; 286 pba.pba_intrswiz = 3; 287 pba.pba_intrtag = 0; 288 /* XXX MRL/MRM/MWI seem to have problems, at the moment. */ 289 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED /* | 290 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY */; 291 (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); 292 } 293 294 /* 295 * i80312_pcibus_print: 296 * 297 * Autoconfiguration cfprint routine when attaching 298 * to the "pcibus" attribute. 299 */ 300 static int 301 i80312_pcibus_print(void *aux, const char *pnp) 302 { 303 struct pcibus_attach_args *pba = aux; 304 305 if (pnp) 306 aprint_normal("%s at %s", pba->pba_busname, pnp); 307 308 aprint_normal(" bus %d", pba->pba_bus); 309 310 return (UNCONF); 311 } 312 313 /* 314 * i80312_pci_dma_init: 315 * 316 * Initialize the PCI DMA tag. 317 */ 318 static void 319 i80312_pci_dma_init(struct i80312_softc *sc) 320 { 321 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 322 struct arm32_dma_range *dr = &sc->sc_pci_dma_range; 323 324 dr->dr_sysbase = sc->sc_sin_xlate; 325 dr->dr_busbase = sc->sc_sin_base; 326 dr->dr_len = sc->sc_sin_size; 327 328 dmat->_ranges = dr; 329 dmat->_nranges = 1; 330 331 dmat->_dmamap_create = _bus_dmamap_create; 332 dmat->_dmamap_destroy = _bus_dmamap_destroy; 333 dmat->_dmamap_load = _bus_dmamap_load; 334 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 335 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 336 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 337 dmat->_dmamap_unload = _bus_dmamap_unload; 338 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 339 dmat->_dmamap_sync_post = NULL; 340 341 dmat->_dmamem_alloc = _bus_dmamem_alloc; 342 dmat->_dmamem_free = _bus_dmamem_free; 343 dmat->_dmamem_map = _bus_dmamem_map; 344 dmat->_dmamem_unmap = _bus_dmamem_unmap; 345 dmat->_dmamem_mmap = _bus_dmamem_mmap; 346 } 347
Indexes created Mon Sep 29 21:09:56 GMT 2025