i80312.c revision 1.16
1 /* $NetBSD: i80312.c,v 1.16 2003/10/06 16:06:05 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.16 2003/10/06 16:06:05 thorpej Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #define _ARM32_BUS_DMA_PRIVATE 50 #include <machine/bus.h> 51 52 #include <arm/xscale/i80312reg.h> 53 #include <arm/xscale/i80312var.h> 54 55 #include <dev/pci/ppbreg.h> 56 57 /* 58 * Statically-allocated bus_space stucture used to access the 59 * i80312's own registers. 60 */ 61 struct bus_space i80312_bs_tag; 62 63 /* 64 * There can be only one i80312, so we keep a global pointer to 65 * the softc, so board-specific code can use features of the 66 * i80312 without having to have a handle on the softc itself. 67 */ 68 struct i80312_softc *i80312_softc; 69 70 static void i80312_pci_dma_init(struct i80312_softc *); 71 static void i80312_local_dma_init(struct i80312_softc *); 72 73 static int i80312_iopxs_print(void *, const char *); 74 static int i80312_pcibus_print(void *, const char *); 75 76 /* Built-in devices. */ 77 static const struct iopxs_device { 78 const char *id_name; 79 bus_addr_t id_offset; 80 bus_size_t id_size; 81 } iopxs_devices[] = { 82 /* { "iopaau", I80312_AAU_BASE, I80312_AAU_SIZE }, */ 83 /* { "iopdma", I80312_DMA_BASE0, I80312_DMA_SIZE }, */ 84 /* { "iopdma", I80312_DMA_BASE1, I80312_DMA_SIZE }, */ 85 { "iopiic", I80312_IIC_BASE, I80312_IIC_SIZE }, 86 /* { "iopmu", I80312_MSG_BASE, I80312_MU_SIZE }, */ 87 { NULL, 0, 0 } 88 }; 89 90 /* 91 * i80312_attach: 92 * 93 * Board-independent attach routine for the i80312. 94 */ 95 void 96 i80312_attach(struct i80312_softc *sc) 97 { 98 struct pcibus_attach_args pba; 99 const struct iopxs_device *id; 100 struct iopxs_attach_args ia; 101 uint32_t atucr; 102 pcireg_t preg; 103 104 i80312_softc = sc; 105 106 /* 107 * Slice off some useful subregion handles. 108 */ 109 110 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE, 111 I80312_PPB_SIZE, &sc->sc_ppb_sh)) 112 panic("%s: unable to subregion PPB registers", 113 sc->sc_dev.dv_xname); 114 115 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE, 116 I80312_ATU_SIZE, &sc->sc_atu_sh)) 117 panic("%s: unable to subregion ATU registers", 118 sc->sc_dev.dv_xname); 119 120 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_INTC_BASE, 121 I80312_INTC_SIZE, &sc->sc_intc_sh)) 122 panic("%s: unable to subregion INTC registers", 123 sc->sc_dev.dv_xname); 124 125 /* We expect the Memory Controller to be already sliced off. */ 126 127 /* 128 * Disable the private space decode. 129 */ 130 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh, 131 I80312_PPB_SDER); 132 sc->sc_sder &= ~PPB_SDER_PMSE; 133 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, 134 I80312_PPB_SDER, sc->sc_sder); 135 136 /* 137 * Program the Secondary ID Select register. 138 */ 139 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, 140 I80312_PPB_SISR, sc->sc_sisr); 141 142 /* 143 * Program the private secondary bus spaces. 144 */ 145 if (sc->sc_privmem_size && sc->sc_privio_size) { 146 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR, 147 (sc->sc_privio_base >> 12) << 4); 148 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR, 149 ((sc->sc_privio_base + sc->sc_privio_size - 1) 150 >> 12) << 4); 151 152 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR, 153 (sc->sc_privmem_base >> 20) << 4); 154 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR, 155 ((sc->sc_privmem_base + sc->sc_privmem_size - 1) 156 >> 20) << 4); 157 158 sc->sc_sder |= PPB_SDER_PMSE; 159 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER, 160 sc->sc_sder); 161 } else if (sc->sc_privmem_size || sc->sc_privio_size) { 162 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n", 163 sc->sc_dev.dv_xname, sc->sc_privmem_size, 164 sc->sc_privio_size); 165 printf("%s: private bus spaces not enabled\n", 166 sc->sc_dev.dv_xname); 167 } 168 169 /* 170 * Program the Primary Inbound window. 171 */ 172 if (sc->sc_is_host) 173 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 174 PCI_MAPREG_START, sc->sc_pin_base); 175 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 176 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size)); 177 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 178 I80312_ATU_PIATV, sc->sc_pin_xlate); 179 180 /* 181 * Program the Secondary Inbound window. 182 */ 183 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 184 I80312_ATU_SIAM, sc->sc_sin_base); 185 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 186 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size)); 187 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 188 I80312_ATU_SIATV, sc->sc_sin_xlate); 189 190 /* 191 * Mask (disable) the ATU interrupt sources. 192 * XXX May want to revisit this if we encounter 193 * XXX an application that wants it. 194 */ 195 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 196 I80312_ATU_PAIM, 197 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 198 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM | 199 ATU_AIM_PSTIM); 200 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 201 I80312_ATU_SAIM, 202 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 203 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM); 204 205 /* 206 * Clear: 207 * 208 * Primary Outbound ATU Enable 209 * Secondary Outbound ATU Enable 210 * Secondary Direct Addressing Select 211 * Direct Addressing Enable 212 */ 213 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR); 214 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE); 215 216 /* 217 * Program the Primary Outbound windows. 218 */ 219 if (sc->sc_pmemout_size) 220 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 221 I80312_ATU_POMWV, sc->sc_pmemout_base); 222 if (sc->sc_pioout_size) 223 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 224 I80312_ATU_POIOWV, sc->sc_pioout_base); 225 if (sc->sc_pmemout_size || sc->sc_pioout_size) 226 atucr |= ATU_ACR_POAE; 227 228 /* 229 * Program the Secondary Outbound windows. 230 */ 231 if (sc->sc_smemout_size) 232 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 233 I80312_ATU_SOMWV, sc->sc_smemout_base); 234 if (sc->sc_sioout_size) 235 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 236 I80312_ATU_SOIOWV, sc->sc_sioout_base); 237 if (sc->sc_smemout_size || sc->sc_sioout_size) 238 atucr |= ATU_ACR_SOAE; 239 240 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr); 241 242 /* 243 * Enable bus mastering, memory access, SERR, and parity 244 * checking on the ATU. 245 */ 246 if (sc->sc_is_host) { 247 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 248 PCI_COMMAND_STATUS_REG); 249 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 250 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 251 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 252 PCI_COMMAND_STATUS_REG, preg); 253 } 254 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 255 I80312_ATU_SACS); 256 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 257 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 258 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 259 I80312_ATU_SACS, preg); 260 261 /* 262 * Configure the bridge. If we're a host, set the primary 263 * bus to bus #0 and the secondary bus to bus #1. We also 264 * set the PPB's subordinate bus # to 1. It will be fixed 265 * up later when we fully configure the bus. 266 * 267 * If we're a slave, just use the bus #'s that the host 268 * provides. 269 */ 270 if (sc->sc_is_host) { 271 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh, 272 PPB_REG_BUSINFO, 273 (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) | 274 (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) | 275 (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT)); 276 } 277 278 /* Initialize the bus space tags. */ 279 i80312_io_bs_init(&sc->sc_pci_iot, sc); 280 i80312_mem_bs_init(&sc->sc_pci_memt, sc); 281 282 /* Initialize the PCI chipset tag. */ 283 i80312_pci_init(&sc->sc_pci_chipset, sc); 284 285 /* Initialize the DMA tags. */ 286 i80312_pci_dma_init(sc); 287 i80312_local_dma_init(sc); 288 289 /* 290 * Attach all the IOP built-ins. 291 */ 292 for (id = iopxs_devices; id->id_name != NULL; id++) { 293 ia.ia_name = id->id_name; 294 ia.ia_st = sc->sc_st; 295 ia.ia_sh = sc->sc_sh; 296 ia.ia_dmat = &sc->sc_local_dmat; 297 ia.ia_offset = id->id_offset; 298 ia.ia_size = id->id_size; 299 300 (void) config_found(&sc->sc_dev, &ia, i80312_iopxs_print); 301 } 302 303 /* 304 * Attach the PCI bus. 305 * 306 * Note: We only probe the Secondary PCI bus, since that 307 * is the only bus on which we can have a private device 308 * space. 309 */ 310 preg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 311 pba.pba_busname = "pci"; 312 pba.pba_iot = &sc->sc_pci_iot; 313 pba.pba_memt = &sc->sc_pci_memt; 314 pba.pba_dmat = &sc->sc_pci_dmat; 315 pba.pba_dmat64 = NULL; 316 pba.pba_pc = &sc->sc_pci_chipset; 317 pba.pba_bus = PPB_BUSINFO_SECONDARY(preg); 318 pba.pba_bridgetag = NULL; 319 pba.pba_intrswiz = 3; 320 pba.pba_intrtag = 0; 321 /* XXX MRL/MRM/MWI seem to have problems, at the moment. */ 322 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED /* | 323 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY */; 324 (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); 325 } 326 327 /* 328 * i80312_iopxs_print: 329 * 330 * Autoconfiguration cfprint routine when attaching 331 * to the "iopxs" device. 332 */ 333 static int 334 i80312_iopxs_print(void *aux, const char *pnp) 335 { 336 337 return (QUIET); 338 } 339 340 /* 341 * i80312_pcibus_print: 342 * 343 * Autoconfiguration cfprint routine when attaching 344 * to the "pcibus" attribute. 345 */ 346 static int 347 i80312_pcibus_print(void *aux, const char *pnp) 348 { 349 struct pcibus_attach_args *pba = aux; 350 351 if (pnp) 352 aprint_normal("%s at %s", pba->pba_busname, pnp); 353 354 aprint_normal(" bus %d", pba->pba_bus); 355 356 return (UNCONF); 357 } 358 359 /* 360 * i80312_pci_dma_init: 361 * 362 * Initialize the PCI DMA tag. 363 */ 364 static void 365 i80312_pci_dma_init(struct i80312_softc *sc) 366 { 367 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 368 struct arm32_dma_range *dr = &sc->sc_pci_dma_range; 369 370 dr->dr_sysbase = sc->sc_sin_xlate; 371 dr->dr_busbase = sc->sc_sin_base; 372 dr->dr_len = sc->sc_sin_size; 373 374 dmat->_ranges = dr; 375 dmat->_nranges = 1; 376 377 dmat->_dmamap_create = _bus_dmamap_create; 378 dmat->_dmamap_destroy = _bus_dmamap_destroy; 379 dmat->_dmamap_load = _bus_dmamap_load; 380 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 381 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 382 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 383 dmat->_dmamap_unload = _bus_dmamap_unload; 384 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 385 dmat->_dmamap_sync_post = NULL; 386 387 dmat->_dmamem_alloc = _bus_dmamem_alloc; 388 dmat->_dmamem_free = _bus_dmamem_free; 389 dmat->_dmamem_map = _bus_dmamem_map; 390 dmat->_dmamem_unmap = _bus_dmamem_unmap; 391 dmat->_dmamem_mmap = _bus_dmamem_mmap; 392 } 393 394 /* 395 * i80312_local_dma_init: 396 * 397 * Initialize the local DMA tag. 398 */ 399 static void 400 i80312_local_dma_init(struct i80312_softc *sc) 401 { 402 bus_dma_tag_t dmat = &sc->sc_local_dmat; 403 404 dmat->_ranges = NULL; 405 dmat->_nranges = 0; 406 407 dmat->_dmamap_create = _bus_dmamap_create; 408 dmat->_dmamap_destroy = _bus_dmamap_destroy; 409 dmat->_dmamap_load = _bus_dmamap_load; 410 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 411 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 412 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 413 dmat->_dmamap_unload = _bus_dmamap_unload; 414 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 415 dmat->_dmamap_sync_post = NULL; 416 417 dmat->_dmamem_alloc = _bus_dmamem_alloc; 418 dmat->_dmamem_free = _bus_dmamem_free; 419 dmat->_dmamem_map = _bus_dmamem_map; 420 dmat->_dmamem_unmap = _bus_dmamem_unmap; 421 dmat->_dmamem_mmap = _bus_dmamem_mmap; 422 } 423
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