i80312.c revision 1.2
1 /* $NetBSD: i80312.c,v 1.2 2001/11/09 17:44:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <arm/xscale/i80312reg.h> 49 #include <arm/xscale/i80312var.h> 50 51 #include <dev/pci/ppbreg.h> 52 53 /* 54 * Statically-allocated bus_space stucture used to access the 55 * i80312's own registers. 56 */ 57 struct bus_space i80312_bs_tag; 58 59 int i80312_pcibus_print(void *, const char *); 60 61 /* 62 * i80312_attach: 63 * 64 * Board-independent attach routine for the i80312. 65 */ 66 void 67 i80312_attach(struct i80312_softc *sc) 68 { 69 struct pcibus_attach_args pba; 70 uint32_t atucr; 71 pcireg_t preg; 72 73 /* 74 * Slice off some useful subregion handles. 75 */ 76 77 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE, 78 I80312_PPB_SIZE, &sc->sc_ppb_sh)) 79 panic("%s: unable to subregion PPB registers\n", 80 sc->sc_dev.dv_xname); 81 82 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE, 83 I80312_ATU_SIZE, &sc->sc_atu_sh)) 84 panic("%s: unable to subregion ATU registers\n", 85 sc->sc_dev.dv_xname); 86 87 /* 88 * Disable the private space decode. 89 */ 90 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh, 91 I80312_PPB_SDER); 92 sc->sc_sder &= ~PPB_SDER_PMSE; 93 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, 94 I80312_PPB_SDER, sc->sc_sder); 95 96 /* 97 * Program the Secondary ID Select register. 98 */ 99 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, 100 I80312_PPB_SISR, sc->sc_sisr); 101 102 /* 103 * Program the private secondary bus spaces. 104 */ 105 if (sc->sc_privmem_size && sc->sc_privio_size) { 106 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR, 107 (sc->sc_privio_base >> 12) << 4); 108 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR, 109 ((sc->sc_privio_base + sc->sc_privio_size - 1) 110 >> 12) << 4); 111 112 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR, 113 (sc->sc_privmem_base >> 20) << 4); 114 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR, 115 ((sc->sc_privmem_base + sc->sc_privmem_size - 1) 116 >> 20) << 4); 117 118 sc->sc_sder |= PPB_SDER_PMSE; 119 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER, 120 sc->sc_sder); 121 } else if (sc->sc_privmem_size || sc->sc_privio_size) { 122 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n", 123 sc->sc_dev.dv_xname, sc->sc_privmem_size, 124 sc->sc_privio_size); 125 printf("%s: private bus spaces not enabled\n", 126 sc->sc_dev.dv_xname); 127 } 128 129 /* 130 * Program the Primary Inbound window. 131 */ 132 if (sc->sc_is_host) 133 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 134 PCI_MAPREG_START, sc->sc_pin_base); 135 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 136 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size)); 137 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 138 I80312_ATU_PIATV, sc->sc_pin_xlate); 139 140 /* 141 * Program the Secondary Inbound window. 142 */ 143 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 144 I80312_ATU_SIAM, sc->sc_sin_base); 145 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 146 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size)); 147 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 148 I80312_ATU_SIATV, sc->sc_sin_xlate); 149 150 /* 151 * Mask (disable) the ATU interrupt sources. 152 * XXX May want to revisit this if we encounter 153 * XXX an application that wants it. 154 */ 155 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 156 I80312_ATU_PAIM, 157 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 158 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM | 159 ATU_AIM_PSTIM); 160 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 161 I80312_ATU_SAIM, 162 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 163 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM); 164 165 /* 166 * Clear: 167 * 168 * Primary Outbound ATU Enable 169 * Secondary Outbound ATU Enable 170 * Secondary Direct Addressing Select 171 * Direct Addressing Enable 172 */ 173 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR); 174 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE); 175 176 /* 177 * Program the Primary Outbound windows. 178 */ 179 if (sc->sc_pmemout_size) 180 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 181 I80312_ATU_POMWV, sc->sc_pmemout_base); 182 if (sc->sc_pioout_size) 183 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 184 I80312_ATU_POIOWV, sc->sc_pioout_base); 185 if (sc->sc_pmemout_size || sc->sc_pioout_size) 186 atucr |= ATU_ACR_POAE; 187 188 /* 189 * Program the Secondary Outbound windows. 190 */ 191 if (sc->sc_smemout_size) 192 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 193 I80312_ATU_SOMWV, sc->sc_smemout_base); 194 if (sc->sc_sioout_size) 195 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 196 I80312_ATU_SOIOWV, sc->sc_sioout_base); 197 if (sc->sc_smemout_size || sc->sc_sioout_size) 198 atucr |= ATU_ACR_SOAE; 199 200 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr); 201 202 /* 203 * Enable bus mastering, memory access, SERR, and parity 204 * checking on the ATU. 205 */ 206 if (sc->sc_is_host) { 207 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 208 PCI_COMMAND_STATUS_REG); 209 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 210 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 211 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 212 PCI_COMMAND_STATUS_REG, preg); 213 } 214 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 215 I80312_ATU_SACS); 216 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 217 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 218 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 219 I80312_ATU_SACS, preg); 220 221 /* 222 * Configure the bridge. If we're a host, set the primary 223 * bus to bus #0 and the secondary bus to bus #1. We also 224 * set the PPB's subordinate bus # to 1. It will be fixed 225 * up later when we fully configure the bus. 226 * 227 * If we're a slave, just use the bus #'s that the host 228 * provides. 229 */ 230 if (sc->sc_is_host) { 231 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh, 232 PPB_REG_BUSINFO, 233 (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) | 234 (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) | 235 (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT)); 236 } 237 238 /* 239 * Initialize the bus space and DMA tags and the PCI chipset tag. 240 */ 241 i80312_io_bs_init(&sc->sc_pci_iot, sc); 242 i80312_mem_bs_init(&sc->sc_pci_memt, sc); 243 #if 0 244 i80312_pci_dma_init(&sc->sc_pci_dmat, sc); 245 #endif 246 i80312_pci_init(&sc->sc_pci_chipset, sc); 247 248 /* 249 * Attach the PCI bus. Note that if we're a host, we can 250 * safely probe for devices on the Primary bus. If we're 251 * a slave, we must limit ourselves to our Secondary bus, 252 * specifically, the private devices on the Secondary bus. 253 */ 254 pba.pba_busname = "pci"; 255 pba.pba_iot = &sc->sc_pci_iot; 256 pba.pba_memt = &sc->sc_pci_memt; 257 pba.pba_dmat = &sc->sc_pci_dmat; 258 pba.pba_pc = &sc->sc_pci_chipset; 259 pba.pba_bus = 1; /* XXX for now */ 260 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 261 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 262 (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); 263 } 264 265 /* 266 * i80312_pcibus_print: 267 * 268 * Autoconfiguration cfprint routine when attaching 269 * to the "pcibus" attribute. 270 */ 271 int 272 i80312_pcibus_print(void *aux, const char *pnp) 273 { 274 struct pcibus_attach_args *pba = aux; 275 276 if (pnp) 277 printf("%s at %s", pba->pba_busname, pnp); 278 279 printf(" bus %d", pba->pba_bus); 280 281 return (UNCONF); 282 } 283
Indexes created Wed Sep 24 05:09:52 GMT 2025