i80312.c revision 1.3
1 /* $NetBSD: i80312.c,v 1.3 2001/11/10 23:14:51 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <arm/xscale/i80312reg.h> 49 #include <arm/xscale/i80312var.h> 50 51 #include <dev/pci/ppbreg.h> 52 53 /* 54 * Statically-allocated bus_space stucture used to access the 55 * i80312's own registers. 56 */ 57 struct bus_space i80312_bs_tag; 58 59 int i80312_pcibus_print(void *, const char *); 60 61 /* 62 * i80312_attach: 63 * 64 * Board-independent attach routine for the i80312. 65 */ 66 void 67 i80312_attach(struct i80312_softc *sc) 68 { 69 struct pcibus_attach_args pba; 70 uint32_t atucr; 71 pcireg_t preg; 72 73 /* 74 * Slice off some useful subregion handles. 75 */ 76 77 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE, 78 I80312_PPB_SIZE, &sc->sc_ppb_sh)) 79 panic("%s: unable to subregion PPB registers\n", 80 sc->sc_dev.dv_xname); 81 82 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE, 83 I80312_ATU_SIZE, &sc->sc_atu_sh)) 84 panic("%s: unable to subregion ATU registers\n", 85 sc->sc_dev.dv_xname); 86 87 /* We expect the Memory Controller to be already sliced off. */ 88 89 /* 90 * Disable the private space decode. 91 */ 92 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh, 93 I80312_PPB_SDER); 94 sc->sc_sder &= ~PPB_SDER_PMSE; 95 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, 96 I80312_PPB_SDER, sc->sc_sder); 97 98 /* 99 * Program the Secondary ID Select register. 100 */ 101 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, 102 I80312_PPB_SISR, sc->sc_sisr); 103 104 /* 105 * Program the private secondary bus spaces. 106 */ 107 if (sc->sc_privmem_size && sc->sc_privio_size) { 108 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR, 109 (sc->sc_privio_base >> 12) << 4); 110 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR, 111 ((sc->sc_privio_base + sc->sc_privio_size - 1) 112 >> 12) << 4); 113 114 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR, 115 (sc->sc_privmem_base >> 20) << 4); 116 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR, 117 ((sc->sc_privmem_base + sc->sc_privmem_size - 1) 118 >> 20) << 4); 119 120 sc->sc_sder |= PPB_SDER_PMSE; 121 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER, 122 sc->sc_sder); 123 } else if (sc->sc_privmem_size || sc->sc_privio_size) { 124 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n", 125 sc->sc_dev.dv_xname, sc->sc_privmem_size, 126 sc->sc_privio_size); 127 printf("%s: private bus spaces not enabled\n", 128 sc->sc_dev.dv_xname); 129 } 130 131 /* 132 * Program the Primary Inbound window. 133 */ 134 if (sc->sc_is_host) 135 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 136 PCI_MAPREG_START, sc->sc_pin_base); 137 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 138 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size)); 139 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 140 I80312_ATU_PIATV, sc->sc_pin_xlate); 141 142 /* 143 * Program the Secondary Inbound window. 144 */ 145 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 146 I80312_ATU_SIAM, sc->sc_sin_base); 147 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 148 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size)); 149 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 150 I80312_ATU_SIATV, sc->sc_sin_xlate); 151 152 /* 153 * Mask (disable) the ATU interrupt sources. 154 * XXX May want to revisit this if we encounter 155 * XXX an application that wants it. 156 */ 157 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 158 I80312_ATU_PAIM, 159 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 160 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM | 161 ATU_AIM_PSTIM); 162 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 163 I80312_ATU_SAIM, 164 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM | 165 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM); 166 167 /* 168 * Clear: 169 * 170 * Primary Outbound ATU Enable 171 * Secondary Outbound ATU Enable 172 * Secondary Direct Addressing Select 173 * Direct Addressing Enable 174 */ 175 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR); 176 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE); 177 178 /* 179 * Program the Primary Outbound windows. 180 */ 181 if (sc->sc_pmemout_size) 182 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 183 I80312_ATU_POMWV, sc->sc_pmemout_base); 184 if (sc->sc_pioout_size) 185 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 186 I80312_ATU_POIOWV, sc->sc_pioout_base); 187 if (sc->sc_pmemout_size || sc->sc_pioout_size) 188 atucr |= ATU_ACR_POAE; 189 190 /* 191 * Program the Secondary Outbound windows. 192 */ 193 if (sc->sc_smemout_size) 194 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 195 I80312_ATU_SOMWV, sc->sc_smemout_base); 196 if (sc->sc_sioout_size) 197 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 198 I80312_ATU_SOIOWV, sc->sc_sioout_base); 199 if (sc->sc_smemout_size || sc->sc_sioout_size) 200 atucr |= ATU_ACR_SOAE; 201 202 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr); 203 204 /* 205 * Enable bus mastering, memory access, SERR, and parity 206 * checking on the ATU. 207 */ 208 if (sc->sc_is_host) { 209 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 210 PCI_COMMAND_STATUS_REG); 211 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 212 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 213 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 214 PCI_COMMAND_STATUS_REG, preg); 215 } 216 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 217 I80312_ATU_SACS); 218 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 219 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 220 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 221 I80312_ATU_SACS, preg); 222 223 /* 224 * Configure the bridge. If we're a host, set the primary 225 * bus to bus #0 and the secondary bus to bus #1. We also 226 * set the PPB's subordinate bus # to 1. It will be fixed 227 * up later when we fully configure the bus. 228 * 229 * If we're a slave, just use the bus #'s that the host 230 * provides. 231 */ 232 if (sc->sc_is_host) { 233 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh, 234 PPB_REG_BUSINFO, 235 (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) | 236 (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) | 237 (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT)); 238 } 239 240 /* 241 * Initialize the bus space and DMA tags and the PCI chipset tag. 242 */ 243 i80312_io_bs_init(&sc->sc_pci_iot, sc); 244 i80312_mem_bs_init(&sc->sc_pci_memt, sc); 245 i80312_pci_dma_init(&sc->sc_pci_dmat, sc); 246 i80312_pci_init(&sc->sc_pci_chipset, sc); 247 248 /* 249 * Attach the PCI bus. Note that if we're a host, we can 250 * safely probe for devices on the Primary bus. If we're 251 * a slave, we must limit ourselves to our Secondary bus, 252 * specifically, the private devices on the Secondary bus. 253 */ 254 pba.pba_busname = "pci"; 255 pba.pba_iot = &sc->sc_pci_iot; 256 pba.pba_memt = &sc->sc_pci_memt; 257 pba.pba_dmat = &sc->sc_pci_dmat; 258 pba.pba_pc = &sc->sc_pci_chipset; 259 pba.pba_bus = 1; /* XXX for now */ 260 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 261 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 262 (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); 263 } 264 265 /* 266 * i80312_pcibus_print: 267 * 268 * Autoconfiguration cfprint routine when attaching 269 * to the "pcibus" attribute. 270 */ 271 int 272 i80312_pcibus_print(void *aux, const char *pnp) 273 { 274 struct pcibus_attach_args *pba = aux; 275 276 if (pnp) 277 printf("%s at %s", pba->pba_busname, pnp); 278 279 printf(" bus %d", pba->pba_bus); 280 281 return (UNCONF); 282 } 283
Indexes created Thu Sep 25 16:09:42 GMT 2025