i80312_pci.c revision 1.5
1 /* $NetBSD: i80312_pci.c,v 1.5 2001/11/29 02:26:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/extent.h> 46 #include <sys/malloc.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 52 #include <arm/xscale/i80312reg.h> 53 #include <arm/xscale/i80312var.h> 54 55 #include <dev/pci/ppbreg.h> 56 #include <dev/pci/pciconf.h> 57 58 #include "opt_pci.h" 59 #include "pci.h" 60 61 void i80312_pci_attach_hook(struct device *, struct device *, 62 struct pcibus_attach_args *); 63 int i80312_pci_bus_maxdevs(void *, int); 64 pcitag_t i80312_pci_make_tag(void *, int, int, int); 65 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *, 66 int *); 67 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int); 68 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t); 69 70 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 71 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 72 73 void 74 i80312_pci_init(pci_chipset_tag_t pc, void *cookie) 75 { 76 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 77 struct i80312_softc *sc = cookie; 78 struct extent *ioext, *memext; 79 pcireg_t binfo; 80 int pbus, sbus; 81 #endif 82 83 pc->pc_conf_v = cookie; 84 pc->pc_attach_hook = i80312_pci_attach_hook; 85 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs; 86 pc->pc_make_tag = i80312_pci_make_tag; 87 pc->pc_decompose_tag = i80312_pci_decompose_tag; 88 pc->pc_conf_read = i80312_pci_conf_read; 89 pc->pc_conf_write = i80312_pci_conf_write; 90 91 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 92 /* 93 * Configure the PCI bus. 94 * 95 * XXX We need to revisit this. We currently only configure 96 * the Secondary bus (and its children). The bus configure 97 * code needs changes to support how the busses are arranged 98 * on this chip. 99 */ 100 101 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 102 pbus = PPB_BUSINFO_PRIMARY(binfo); 103 sbus = PPB_BUSINFO_SECONDARY(binfo); 104 105 ioext = extent_create("pciio", sc->sc_sioout_base, 106 sc->sc_sioout_base + sc->sc_sioout_size - 1, 107 M_DEVBUF, NULL, 0, EX_NOWAIT); 108 memext = extent_create("pcimem", sc->sc_smemout_base, 109 sc->sc_smemout_base + sc->sc_smemout_size - 1, 110 M_DEVBUF, NULL, 0, EX_NOWAIT); 111 112 printf("%s: configuring Secondary PCI bus\n", sc->sc_dev.dv_xname); 113 pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align); 114 115 extent_destroy(ioext); 116 extent_destroy(memext); 117 #endif 118 } 119 120 void 121 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 122 { 123 } 124 125 void 126 i80312_pci_attach_hook(struct device *parent, struct device *self, 127 struct pcibus_attach_args *pba) 128 { 129 130 /* Nothing to do. */ 131 } 132 133 int 134 i80312_pci_bus_maxdevs(void *v, int busno) 135 { 136 137 return (32); 138 } 139 140 pcitag_t 141 i80312_pci_make_tag(void *v, int b, int d, int f) 142 { 143 144 return ((b << 16) | (d << 11) | (f << 8)); 145 } 146 147 void 148 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 149 { 150 151 if (bp != NULL) 152 *bp = (tag >> 16) & 0xff; 153 if (dp != NULL) 154 *dp = (tag >> 11) & 0x1f; 155 if (fp != NULL) 156 *fp = (tag >> 8) & 0x7; 157 } 158 159 struct pciconf_state { 160 bus_addr_t ps_addr_reg; 161 bus_addr_t ps_data_reg; 162 bus_addr_t ps_csr_reg; 163 uint32_t ps_addr_val; 164 165 int ps_b, ps_d, ps_f; 166 }; 167 168 static int 169 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset, 170 struct pciconf_state *ps) 171 { 172 pcireg_t binfo; 173 int pbus, sbus; 174 175 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 176 177 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 178 pbus = PPB_BUSINFO_PRIMARY(binfo); 179 sbus = PPB_BUSINFO_SECONDARY(binfo); 180 181 /* 182 * If the bus # is the Primary bus #, use the Primary 183 * Address/Data registers, otherwise use the Secondary 184 * Address/Data registers. 185 */ 186 if (ps->ps_b == pbus) { 187 ps->ps_addr_reg = I80312_ATU_POCCA; 188 ps->ps_data_reg = I80312_ATU_POCCD; 189 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG; 190 } else { 191 ps->ps_addr_reg = I80312_ATU_SOCCA; 192 ps->ps_data_reg = I80312_ATU_SOCCD; 193 ps->ps_csr_reg = I80312_ATU_SACS; 194 } 195 196 /* 197 * If the bus # is the Primary or Secondary bus #, then use 198 * Type 0 cycles, else use Type 1. 199 * 200 * XXX We should filter out all non-private devices here! 201 * XXX How does private space interact with PCI-PCI bridges? 202 */ 203 if (ps->ps_b == pbus || ps->ps_b == sbus) { 204 if (ps->ps_d > (31 - 11)) 205 return (1); 206 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) | 207 offset; 208 } else { 209 /* The tag is already in the correct format. */ 210 ps->ps_addr_val = tag | offset | 1; 211 } 212 213 return (0); 214 } 215 216 pcireg_t 217 i80312_pci_conf_read(void *v, pcitag_t tag, int offset) 218 { 219 struct i80312_softc *sc = v; 220 struct pciconf_state ps; 221 vaddr_t va; 222 pcireg_t rv; 223 u_int s; 224 225 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 226 return ((pcireg_t) -1); 227 228 PCI_CONF_LOCK(s); 229 230 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 231 ps.ps_addr_val); 232 233 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 234 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) { 235 /* 236 * Clear the Master Abort by reading the PCI 237 * Status Register. 238 */ 239 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 240 ps.ps_csr_reg); 241 #if 0 242 printf("conf_read: %d/%d/%d bad address\n", 243 ps.ps_b, ps.ps_d, ps.ps_f); 244 #endif 245 rv = (pcireg_t) -1; 246 } 247 248 PCI_CONF_UNLOCK(s); 249 250 return (rv); 251 } 252 253 void 254 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 255 { 256 struct i80312_softc *sc = v; 257 struct pciconf_state ps; 258 u_int s; 259 260 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 261 return; 262 263 PCI_CONF_LOCK(s); 264 265 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 266 ps.ps_addr_val); 267 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val); 268 269 PCI_CONF_UNLOCK(s); 270 } 271
Indexes created Thu Sep 25 16:09:42 GMT 2025