i80312_pci.c revision 1.7 1 /* $NetBSD: i80312_pci.c,v 1.7 2003/05/23 05:21:26 briggs Exp $ */
2
3 /*
4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * PCI configuration support for i80312 Companion I/O chip.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/device.h>
45 #include <sys/extent.h>
46 #include <sys/malloc.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <machine/bus.h>
51
52 #include <arm/xscale/i80312reg.h>
53 #include <arm/xscale/i80312var.h>
54
55 #include <dev/pci/ppbreg.h>
56 #include <dev/pci/pciconf.h>
57
58 #include "opt_pci.h"
59 #include "pci.h"
60
61 void i80312_pci_attach_hook(struct device *, struct device *,
62 struct pcibus_attach_args *);
63 int i80312_pci_bus_maxdevs(void *, int);
64 pcitag_t i80312_pci_make_tag(void *, int, int, int);
65 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *,
66 int *);
67 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int);
68 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t);
69
70 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
71 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
72
73 void
74 i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
75 {
76 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
77 struct i80312_softc *sc = cookie;
78 struct extent *ioext, *memext;
79 pcireg_t binfo;
80 int pbus, sbus;
81 #endif
82
83 pc->pc_conf_v = cookie;
84 pc->pc_attach_hook = i80312_pci_attach_hook;
85 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
86 pc->pc_make_tag = i80312_pci_make_tag;
87 pc->pc_decompose_tag = i80312_pci_decompose_tag;
88 pc->pc_conf_read = i80312_pci_conf_read;
89 pc->pc_conf_write = i80312_pci_conf_write;
90
91 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
92 /*
93 * Configure the PCI bus.
94 *
95 * XXX We need to revisit this. We only configure the Secondary
96 * bus (and its children). The bus configure code needs changes
97 * to support how the busses are arranged on this chip. We also
98 * need to only configure devices in the private device space on
99 * the Secondary bus.
100 */
101
102 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
103 pbus = PPB_BUSINFO_PRIMARY(binfo);
104 sbus = PPB_BUSINFO_SECONDARY(binfo);
105
106 ioext = extent_create("pciio", sc->sc_sioout_base,
107 sc->sc_sioout_base + sc->sc_sioout_size - 1,
108 M_DEVBUF, NULL, 0, EX_NOWAIT);
109 memext = extent_create("pcimem", sc->sc_smemout_base,
110 sc->sc_smemout_base + sc->sc_smemout_size - 1,
111 M_DEVBUF, NULL, 0, EX_NOWAIT);
112
113 aprint_normal("%s: configuring Secondary PCI bus\n", sc->sc_dev.dv_xname);
114 pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);
115
116 extent_destroy(ioext);
117 extent_destroy(memext);
118 #endif
119 }
120
121 void
122 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
123 {
124 }
125
126 void
127 i80312_pci_attach_hook(struct device *parent, struct device *self,
128 struct pcibus_attach_args *pba)
129 {
130
131 /* Nothing to do. */
132 }
133
134 int
135 i80312_pci_bus_maxdevs(void *v, int busno)
136 {
137
138 return (32);
139 }
140
141 pcitag_t
142 i80312_pci_make_tag(void *v, int b, int d, int f)
143 {
144
145 return ((b << 16) | (d << 11) | (f << 8));
146 }
147
148 void
149 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
150 {
151
152 if (bp != NULL)
153 *bp = (tag >> 16) & 0xff;
154 if (dp != NULL)
155 *dp = (tag >> 11) & 0x1f;
156 if (fp != NULL)
157 *fp = (tag >> 8) & 0x7;
158 }
159
160 struct pciconf_state {
161 bus_addr_t ps_addr_reg;
162 bus_addr_t ps_data_reg;
163 bus_addr_t ps_csr_reg;
164 uint32_t ps_addr_val;
165
166 int ps_b, ps_d, ps_f;
167 };
168
169 static int
170 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset,
171 struct pciconf_state *ps)
172 {
173 pcireg_t binfo;
174 int pbus, sbus;
175
176 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
177
178 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
179 pbus = PPB_BUSINFO_PRIMARY(binfo);
180 sbus = PPB_BUSINFO_SECONDARY(binfo);
181
182 /*
183 * If the bus # is the Primary bus #, use the Primary
184 * Address/Data registers, otherwise use the Secondary
185 * Address/Data registers.
186 */
187 if (ps->ps_b == pbus) {
188 ps->ps_addr_reg = I80312_ATU_POCCA;
189 ps->ps_data_reg = I80312_ATU_POCCD;
190 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG;
191 } else {
192 ps->ps_addr_reg = I80312_ATU_SOCCA;
193 ps->ps_data_reg = I80312_ATU_SOCCD;
194 ps->ps_csr_reg = I80312_ATU_SACS;
195 }
196
197 /*
198 * If the bus # is the Primary or Secondary bus #, then use
199 * Type 0 cycles, else use Type 1.
200 *
201 * XXX We should filter out all non-private devices here!
202 * XXX How does private space interact with PCI-PCI bridges?
203 */
204 if (ps->ps_b == pbus || ps->ps_b == sbus) {
205 if (ps->ps_d > (31 - 11))
206 return (1);
207 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) |
208 offset;
209 } else {
210 /* The tag is already in the correct format. */
211 ps->ps_addr_val = tag | offset | 1;
212 }
213
214 return (0);
215 }
216
217 pcireg_t
218 i80312_pci_conf_read(void *v, pcitag_t tag, int offset)
219 {
220 struct i80312_softc *sc = v;
221 struct pciconf_state ps;
222 vaddr_t va;
223 pcireg_t rv;
224 u_int s;
225
226 if (i80312_pci_conf_setup(sc, tag, offset, &ps))
227 return ((pcireg_t) -1);
228
229 PCI_CONF_LOCK(s);
230
231 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
232 ps.ps_addr_val);
233
234 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
235 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) {
236 /*
237 * Clear the Master Abort by reading the PCI
238 * Status Register.
239 */
240 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
241 ps.ps_csr_reg);
242 #if 0
243 printf("conf_read: %d/%d/%d bad address\n",
244 ps.ps_b, ps.ps_d, ps.ps_f);
245 #endif
246 rv = (pcireg_t) -1;
247 }
248
249 PCI_CONF_UNLOCK(s);
250
251 return (rv);
252 }
253
254 void
255 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
256 {
257 struct i80312_softc *sc = v;
258 struct pciconf_state ps;
259 u_int s;
260
261 if (i80312_pci_conf_setup(sc, tag, offset, &ps))
262 return;
263
264 PCI_CONF_LOCK(s);
265
266 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
267 ps.ps_addr_val);
268 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val);
269
270 PCI_CONF_UNLOCK(s);
271 }
272