i80312reg.h revision 1.6
1 /* $NetBSD: i80312reg.h,v 1.6 2001/11/08 03:20:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt (at) 3am-software.com>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_XSCALE_I80312REG_H_ 40 #define _ARM_XSCALE_I80312REG_H_ 41 42 /* 43 * Register definitions for the Intel 80310 I/O Companion Chip. 44 */ 45 46 /* 47 * Physical addresses 0x1000..0x1fff are used by the Periphial Memory 48 * Mapped Registers. 49 */ 50 51 #define I80312_PMMR_BASE 0x00001000UL 52 #define I80312_PMMR_SIZE 0x00001000UL 53 54 /* 55 * The PMMR registers below are defined as offsets from the i80312 PMMR 56 * base. 57 */ 58 59 /* 60 * PCI-to-PCI Bridge Unit 61 */ 62 #define I80312_PPB_BASE (0) 63 #define I80312_PPB_SIZE 0x100 64 /* 65 * Performance Monitoring Unit 66 */ 67 #define I80312_PMU_BASE (I80312_PPB_BASE + I80312_PPB_SIZE) /* 0x100 */ 68 #define I80312_PMU_SIZE 0x100 69 /* 70 * Address Translation Unit 71 */ 72 #define I80312_ATU_BASE (I80312_PMU_BASE + I80312_PMU_SIZE) /* 0x200 */ 73 #define I80312_ATU_SIZE 0x100 74 /* 75 * Messaging Unit 76 */ 77 #define I80312_MSG_BASE (I80312_ATU_BASE + I80312_ATU_SIZE) /* 0x300 */ 78 #define I80312_MSG_SIZE 0x100 79 /* 80 * DMA Controller 81 */ 82 #define I80312_DMA_BASE (I80312_MSG_BASE + I80312_MSG_SIZE) /* 0x400 */ 83 #define I80312_DMA_SIZE 0x100 84 /* 85 * Memory Controller 86 */ 87 #define I80312_MEM_BASE (I80312_DMA_BASE + I80312_DMA_SIZE) /* 0x500 */ 88 #define I80312_MEM_SIZE 0x100 89 /* 90 * Internal Arbitration Unit 91 */ 92 #define I80312_IARB_BASE (I80312_MEM_BASE + I80312_MEM_SIZE) /* 0x600 */ 93 #define I80312_IARB_SIZE 0x040 94 /* 95 * Bus Interface Unit 96 */ 97 #define I80312_BUS_BASE (I80312_IARB_BASE + I80312_IARB_SIZE)/* 0x640 */ 98 #define I80312_BUS_SIZE 0x040 99 /* 100 * I2C Unit 101 */ 102 #define I80312_IIC_BASE (I80312_BUS_BASE + I80312_BUS_SIZE) /* 0x680 */ 103 #define I80312_IIC_SIZE 0x080 104 /* 105 * Interrupt Controller 106 */ 107 #define I80312_INTC_BASE (I80312_IIC_BASE + I80312_IIC_SIZE) /* 0x700 */ 108 #define I80312_INTC_SIZE 0x100 109 /* 110 * Application Accelerator Unit 111 */ 112 #define I80312_AAU_BASE (I80312_INTC_BASE + I80312_INTC_SIZE)/* 0x800 */ 113 #define I80312_AAU_SIZE 0x100 114 115 /* 116 * PCI-PCI Bridge Unit 117 * 118 * The PCI-PCI Bridge Unit supports both public (accessible to the 119 * host) and private (accessible only to the local system) devices: 120 * 121 * --------- 122 * S_AD[11] 123 * S_AD[12] 124 * Private S_AD[13] 125 * S_AD[14] 126 * S_AD[15] 127 * --------- 128 * S_AD[16] SISR bit 9 129 * S_AD[17] SISR bit 8 130 * S_AD[18] SISR bit 7 131 * Public S_AD[19] SISR bit 6 132 * or S_AD[20] SISR bit 5 133 * Private S_AD[21] SISR bit 4 134 * S_AD[22] SISR bit 3 135 * S_AD[23] SISR bit 2 136 * S_AD[24] SISR bit 1 137 * S_AD[25] SISR bit 0 138 * --------- 139 * S_AD[26] 140 * S_AD[27] 141 * Public S_AD[28] 142 * S_AD[29] 143 * S_AD[30] 144 * S_AD[31] 145 * --------- 146 * 147 * Setting the specified SISR bit makes the corresponding S_AD line 148 * a private sevice. 149 */ 150 #define I80312_PPB_EBCR 0x40 /* Extended Bridge Control */ 151 #define I80312_PPB_SISR 0x42 /* Secondary ID Select Register */ 152 #define I80312_PPB_PBISR 0x44 /* Primary Bridge Int. Stat. */ 153 #define I80312_PPB_SBISR 0x48 /* Secondary Bridge Int. Stat. */ 154 #define I80312_PPB_SACR XXX /* Secondary Arb. Control */ 155 #define I80312_PPB_PIRSR XXX /* PCI Int. Routing Select */ 156 #define I80312_PPB_SIOBR 0x54 /* Secondary I/O Base Register */ 157 #define I80312_PPB_SIOLR 0x55 /* Secondary I/O Limit Register */ 158 #define I80312_PPB_SCDR 0x56 /* Secondary Clock Disable Register */ 159 #define I80312_PPB_SMBR 0x58 /* Secondary Memory Base Register */ 160 #define I80312_PPB_SMLR 0x5a /* Secondary Memory Limit Register */ 161 #define I80312_PPB_SDER 0x5c /* Secondary Decode Enable Register */ 162 #define I80312_PPB_QCR 0x5e /* Queue Control Register */ 163 164 /* 165 * Performance Monitoring Unit 166 */ 167 #define I80312_PMU_GTMR 0x00 168 #define I80312_PMU_ESR 0x04 169 #define I80312_PMU_EMISR 0x08 170 #define I80312_PMU_GTSR 0x10 171 #define I80312_PMU_PECR1 0x14 172 #define I80312_PMU_PECR2 0x18 173 #define I80312_PMU_PECR3 0x1c 174 #define I80312_PMU_PECR4 0x20 175 #define I80312_PMU_PECR5 0x24 176 #define I80312_PMU_PECR6 0x28 177 #define I80312_PMU_PECR7 0x2c 178 #define I80312_PMU_PECR8 0x30 179 #define I80312_PMU_PECR9 0x34 180 #define I80312_PMU_PECR10 0x38 181 #define I80312_PMU_PECR11 0x3c 182 #define I80312_PMU_PECR12 0x40 183 #define I80312_PMU_PECR13 0x44 184 #define I80312_PMU_PECR14 0x48 185 186 /* 187 * Address Translation Unit 188 * The first 64 bytes are identical to a PCI device's config space. 189 */ 190 /* BAR #0 0x10 Primary Inbound ATU Base Address */ 191 #define I80312_ATU_PIAL 0x40 /* Pri. Inbound ATU Limit */ 192 #define I80312_ATU_PIATV 0x44 /* Pri. Inbound ATU Translate Value */ 193 #define I80312_ATU_SIAM 0x48 /* Sec. Inbound ATU Base Address */ 194 #define I80312_ATU_SIAL 0x4c /* Sec. Inbound ATU Limit */ 195 #define I80312_ATU_SIATV 0x50 /* Sec. Inbound ATU Translate Value */ 196 #define I80312_ATU_POMWV 0x54 /* Pri. Outbound Memory Window Value */ 197 /* not used 0x58 */ 198 #define I80312_ATU_POIOWV 0x5c /* Pri. Outbound I/O Window Value */ 199 #define I80312_ATU_PODACWVL 0x60 /* Pri. Outbound DAC Window Value (Lo)*/ 200 #define I80312_ATU_PODACWVH 0x64 /* Pri. Outbound DAC Window Value (Hi)*/ 201 #define I80312_ATU_SOMWV 0x68 /* Sec. Outbound Memory Window Value */ 202 #define I80312_ATU_SOIOWV 0x6c /* Sec. Outbound I/O Window Value */ 203 /* not used 0x70 */ 204 #define I80312_ATU_ERL 0x74 /* Expansion ROM Limit */ 205 #define I80312_ATU_ERTV 0x78 /* Expansion ROM Translate Value */ 206 /* not used 0x7c */ 207 #define I80312_ATU_ACI 0x74 /* ATU Capability Identifier */ 208 #define I80312_ATU_ATNIP 0x78 /* ATU Next Item Pointer */ 209 #define I80312_ATU_APM 0x7c /* ATU Power Management */ 210 /* not used 0x84 */ 211 #define I80312_ATU_ACR 0x88 /* ATU Configuration */ 212 /* not used 0x8c */ 213 #define I80312_ATU_PAIS 0x90 /* Pri. ATU Interrupt Status */ 214 #define I80312_ATU_SAIS 0x94 /* Sec. ATU Interrupt Status */ 215 #define I80312_ATU_SACS 0x98 /* Sec. ATU Command/Status */ 216 #define I80312_ATU_SODACWVL 0x9c /* Sec. Outbound DAC Window Value (lo)*/ 217 #define I80312_ATU_SODACWVH 0xa0 /* Sec. Outbound DAC Window Value (hi)*/ 218 #define I80312_ATU_POCCA 0xa4 /* Pri. Outbound Config Address Data */ 219 #define I80312_ATU_SOCCA 0xa8 /* Sec. Outbound Config Address Data */ 220 #define I80312_ATU_POCCD 0xac /* Pri. Outbound Config Cycle Data */ 221 #define I80312_ATU_SOCCD 0xb0 /* Sec. Outbound Config Cycle Data */ 222 #define I80312_ATU_PAQC 0xb4 /* Pri. ATU Queue Control */ 223 #define I80312_ATU_SAQC 0xb8 /* Sec. ATU Queue Control */ 224 #define I80312_ATU_PAIM 0xbc /* Pri. ATU Interrupt Mask */ 225 #define I80312_ATU_SAIM 0xc0 /* Sec. ATU Interrupt Mask */ 226 /* not used 0xc4 .. 0xfc */ 227 228 #define ATU_LIMIT(x) \ 229 ((0xffffffffUL - ((x) - 1)) & 0xfffffff0UL) 230 231 /* 232 * Messaging Unit 233 */ 234 /* not used 0x00 .. 0x0c */ 235 #define I80312_MSG_IM0 0x10 /* Inbound Message 0 */ 236 #define I80312_MSG_IM1 0x14 /* Inbound Message 1 */ 237 #define I80312_MSG_OM0 0x18 /* Outbound Message 0 */ 238 #define I80312_MSG_OM1 0x1c /* Outbound Message 1 */ 239 #define I80312_MSG_ID 0x20 /* Inbound Doorbell */ 240 #define I80312_MSG_IIS 0x24 /* Inbound Interrupt Status */ 241 #define I80312_MSG_IIM 0x28 /* Inbound Interrupt Mask */ 242 #define I80312_MSG_OD 0x2c /* Outbound Doorbell */ 243 #define I80312_MSG_OIS 0x30 /* Outbound Interrupt Status */ 244 #define I80312_MSG_OIM 0x34 /* Outbound Interrupt Mask */ 245 /* not used 0x38 .. 0x4c */ 246 #define I80312_MSG_MC 0x50 /* MU Configuration */ 247 #define I80312_MSG_QBA 0x54 /* Queue Base Address */ 248 /* not used 0x58 .. 0x5c */ 249 #define I80312_MSG_IFHP 0x60 /* Inbound Free Head Pointer */ 250 #define I80312_MSG_IFTP 0x64 /* Inbound Free Tail Pointer */ 251 #define I80312_MSG_IPHP 0x68 /* Inbound Post Head Pointer */ 252 #define I80312_MSG_IPTP 0x6c /* Inbound Post Tail Pointer */ 253 #define I80312_MSG_OFHP 0x70 /* Outbound Free Head Pointer */ 254 #define I80312_MSG_OFTP 0x74 /* Outbound Free Tail Pointer */ 255 #define I80312_MSG_OPHP 0x78 /* Outbound Post Head Pointer */ 256 #define I80312_MSG_OPTP 0x7c /* Outbound Post Tail Pointer */ 257 #define I80312_MSG_IA 0x80 /* Index Address */ 258 /* not used 0x84 .. 0xfc */ 259 260 /* 261 * DMA Controller 262 */ 263 #define I80312_DMA_CHAN0 0x00 /* Channel 0 */ 264 #define I80312_DMA_CHAN1 0x40 /* Channel 1 */ 265 #define I80312_DMA_CHAN2 0x80 /* Channel 2 */ 266 /* not used 0xc0 .. 0xfc */ 267 268 #define I80312_DMA_CC 0x00 /* Channel Control */ 269 #define I80312_DMA_CS 0x04 /* Channel Status */ 270 /* not used 0x08 */ 271 #define I80312_DMA_DA 0x0c /* Descriptor Address */ 272 #define I80312_DMA_NDA 0x10 /* Next Descriptor Address */ 273 #define I80312_DMA_PA 0x14 /* PCI Address */ 274 #define I80312_DMA_PUA 0x18 /* PCI Upper Address */ 275 #define I80312_DMA_IBA 0x1c /* Internal Bus Address */ 276 #define I80312_DMA_BC 0x20 /* Byte Count */ 277 #define I80312_DMA_DC 0x24 /* Descriptor Control */ 278 /* not used 0x28 .. 0x3c */ 279 280 /* 281 * Memory Controller 282 */ 283 #define I80312_MEM_SI 0x00 /* SDRAM Initialization */ 284 #define I80312_MEM_SC 0x04 /* SDRAM Control */ 285 #define I80312_MEM_SB 0x08 /* SDRAM Base */ 286 #define I80312_MEM_SB0 0x0c /* SDRAM Bank 0 Size */ 287 #define I80312_MEM_SB1 0x10 /* SDRAM Bank 1 Size */ 288 /* not used 0x14 .. 0x30 */ 289 #define I80312_MEM_EC 0x34 /* ECC Control */ 290 #define I80312_MEM_EL0 0x38 /* ECC Log 0 */ 291 #define I80312_MEM_EL1 0x3c /* ECC Log 1 */ 292 #define I80312_MEM_EA0 0x40 /* ECC Address 0 */ 293 #define I80312_MEM_EA1 0x44 /* ECC Address 1 */ 294 #define I80312_MEM_ET 0x48 /* ECC Test */ 295 #define I80312_MEM_FB0 0x4c /* ECC Flash Base 0 */ 296 #define I80312_MEM_FB1 0x50 /* ECC Flash Base 1 */ 297 #define I80312_MEM_FB0S 0x54 /* ECC Flash Bank 0 Size */ 298 #define I80312_MEM_FB1S 0x58 /* ECC Flash Bank 1 Size */ 299 #define I80312_MEM_FWS1 0x5c /* ECC Wait State 1 Size */ 300 #define I80312_MEM_FWS0 0x60 /* ECC Wait State 0 Size */ 301 #define I80312_MEM_IS 0x65 /* ECC Interrupt Status */ 302 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 303 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 304 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 305 #define I80312_MEM_RF 0x68 /* ECC Refresh Frequency */ 306 /* not used 0x6c .. 0xfc */ 307 308 /* 309 * Internal Arbitration Unit 310 */ 311 #define I80312_ARB_IAC 0x00 /* Internal Aribtration Control */ 312 #define I80312_ARB_MLT 0x04 /* Master Latency Timer */ 313 #define I80312_ARB_MTT 0x08 /* Multi-Transaction Timer */ 314 /* not used 0x0c .. 0x3c */ 315 316 /* 317 * Bus(Core) Interface Unit 318 */ 319 /* not used 0x40 */ 320 #define I80312_BUS_IS 0x44 /* Interrupt Status */ 321 /* not used 0x4c .. 0x7c */ 322 323 /* 324 * I2C Bus Interface Unit 325 */ 326 #define I80312_IIC_CTL 0x80 /* Control */ 327 #define I80312_IIC_STS 0x84 /* Status */ 328 #define I80312_IIC_SA 0x88 /* Slave Address */ 329 #define I80312_IIC_DB 0x8c /* Data Buffer */ 330 #define I80312_IIC_CC 0x90 /* Clock Control */ 331 #define I80312_IIC_BM 0x94 /* Bus Monitor */ 332 /* not used 0x98 .. 0xfc */ 333 334 /* 335 * PCI And Peripheral Interrupt (GPIO) Unit 336 */ 337 #define I80312_INTC_IIS 0x00 /* IRQ Interrupt Status */ 338 #define I80312_INTC_F2IS 0x04 /* FIQ2 Interrupt Status */ 339 #define I80312_INTC_F1IS 0x08 /* FIQ1 Interrupt Status */ 340 /* not used 0x0c */ 341 #define I80312_INTC_PDI 0x10 /* Processor Device ID */ 342 /* not used 0x14 .. 0x18 */ 343 #define I80312_INTC_GOE 0x1c /* GPIO Output Enable */ 344 #define I80312_INTC_GID 0x20 /* GPIO Input Data */ 345 #define I80312_INTC_GOD 0x24 /* GPIO Output Data */ 346 /* not used 0x28 .. 0xfc */ 347 348 /* 349 * Application Accelerator Registers 350 */ 351 #define I80312_AAU_CTL 0x00 /* Control */ 352 #define I80312_AAU_STS 0x04 /* Status */ 353 #define I80312_AAU_DSCA 0x08 /* Descriptor Address */ 354 #define I80312_AAU_NDA 0x0c /* Next Descriptor Address */ 355 #define I80312_AAU_SA1 0x10 /* i80200 Source Address 1 */ 356 #define I80312_AAU_SA2 0x14 /* i80200 Source Address 2 */ 357 #define I80312_AAU_SA3 0x18 /* i80200 Source Address 3 */ 358 #define I80312_AAU_SA4 0x1c /* i80200 Source Address 4 */ 359 #define I80312_AAU_DSTA 0x20 /* i80200 Destination Address */ 360 #define I80312_AAU_ABC 0x24 /* Accelerator Byte Count */ 361 #define I80312_AAU_ADC 0x28 /* Accelerator Descriptor Count */ 362 #define I80312_AAU_SA5 0x2c /* i80200 Source Address 5 */ 363 #define I80312_AAU_SA6 0x30 /* i80200 Source Address 6 */ 364 #define I80312_AAU_SA7 0x34 /* i80200 Source Address 7 */ 365 #define I80312_AAU_SA8 0x38 /* i80200 Source Address 8 */ 366 /* not used 0x3c .. 0xfc */ 367 368 /* 369 * Physical addresses 0x00002000..0x7fffffff are used by the 370 * ATU Outbound Direct Addressing Window. 371 */ 372 #define I80312_PCI_DIRECT_BASE 0x00002000UL 373 #define I80312_PCI_DIRECT_SIZE 0x7fffe000UL 374 375 /* 376 * Physical addresses 0x80000000..0x9001ffff are used by the 377 * ATU Outbound Transaction Windows. 378 */ 379 #define I80312_PCI_XLATE_BASE 0x80000000UL 380 #define I80312_PCI_XLATE_SIZE 0x10020000UL 381 382 #define I80312_PCI_XLATE_MSIZE 0x04000000UL /* 64M */ 383 #define I80312_PCI_XLATE_IOSIZE 0x00010000UL /* 64K */ 384 385 #define I80312_PCI_XLATE_PMW_BASE (I80312_PCI_XLATE_BASE) 386 387 #define I80312_PCI_XLATE_PDW_BASE (I80312_PCI_XLATE_PMW_BASE + \ 388 I80312_PCI_XLATE_MSIZE) 389 390 #define I80312_PCI_XLATE_SMW_BASE (I80312_PCI_XLATE_PDW_BASE + \ 391 I80312_PCI_XLATE_MSIZE) 392 393 #define I80312_PCI_XLATE_SDW_BASE (I80312_PCI_XLATE_SMW_BASE + \ 394 I80312_PCI_XLATE_MSIZE) 395 396 #define I80312_PCI_XLATE_PIOW_BASE (I80312_PCI_XLATE_SDW_BASE + \ 397 I80312_PCI_XLATE_MSIZE) 398 399 #define I80312_PCI_XLATE_SIOW_BASE (I80312_PCI_XLATE_PIOW_BASE + \ 400 I80312_PCI_XLATE_IOSIZE) 401 402 #endif /* _ARM_XSCALE_I80312REG_H_ */ 403
Indexes created Mon Sep 29 21:09:56 GMT 2025