i80312var.h revision 1.4
1 /* $NetBSD: i80312var.h,v 1.4 2001/11/09 23:15:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_XSCALE_I80312VAR_H_ 39 #define _ARM_XSCALE_I80312VAR_H_ 40 41 #include <machine/bus.h> 42 43 #include <dev/pci/pcivar.h> 44 45 struct i80312_softc { 46 struct device sc_dev; /* generic device glue */ 47 48 int sc_is_host; /* indicates if we're a host or 49 plugged into another host */ 50 51 /* 52 * This is the bus_space and handle used to access the 53 * i80312 itself. This is filled in by the board-specific 54 * front-end. 55 */ 56 bus_space_tag_t sc_st; 57 bus_space_handle_t sc_sh; 58 59 /* Handles for the various subregions. */ 60 bus_space_handle_t sc_ppb_sh; 61 bus_space_handle_t sc_atu_sh; 62 bus_space_handle_t sc_mem_sh; 63 64 /* 65 * Secondary IDSEL Select bits for providing a private 66 * PCI device space. 67 */ 68 uint16_t sc_sisr; 69 70 /* 71 * We expect the board-specific front-end to have already mapped 72 * the PCI I/O spaces .. they're only 64K each, and I/O mappings 73 * tend to be smaller than a page size, so it's generally more 74 * efficient to map them all into virtual space in one fell swoop. 75 */ 76 vaddr_t sc_piow_vaddr; /* primary I/O window vaddr */ 77 vaddr_t sc_siow_vaddr; /* secondary I/O window vaddr */ 78 79 /* 80 * Variables that define the Primary Inbound window. The base 81 * address is configured by a host via BAR #0. The xlate variable 82 * defines the start of the local address space that it maps to. 83 * The size variable defines the byte size. 84 * 85 * This window is used for incoming PCI memory read/write cycles 86 * from a host. 87 * 88 * ...unless we're a host, in which case we make the Primary 89 * Inbound window work like the Secondary Inbound window, so 90 * that PCI devices on that bus can talk to our local RAM. 91 */ 92 uint32_t sc_pin_base; 93 uint32_t sc_pin_xlate; 94 uint32_t sc_pin_size; 95 96 /* 97 * Variables that define the Secondary Inbound window. The 98 * base variable indicates the PCI base address of the window. 99 * The xlate variable defines the start of the local address 100 * space that it maps to. The size variable defines the byte 101 * size. 102 * 103 * This window is used for DMA with devices on the secondary bus. 104 */ 105 uint32_t sc_sin_base; 106 uint32_t sc_sin_xlate; 107 uint32_t sc_sin_size; 108 109 /* 110 * This is the PCI address that the Primary Outbound Memory 111 * window maps to. 112 */ 113 uint32_t sc_pmemout_base; 114 uint32_t sc_pmemout_size; 115 116 /* 117 * This is the PCI address that the Primary Outbound I/O 118 * window maps to. 119 */ 120 uint32_t sc_pioout_base; 121 uint32_t sc_pioout_size; 122 123 /* 124 * This is the PCI address that the Secondary Outbound Memory 125 * window maps to. 126 */ 127 uint32_t sc_smemout_base; 128 uint32_t sc_smemout_size; 129 130 /* 131 * This is the PCI address that the Secondary Outbound I/O 132 * window maps to. 133 */ 134 uint32_t sc_sioout_base; 135 uint32_t sc_sioout_size; 136 137 /* 138 * This defines the private I/O and Memory spaces on the 139 * Secondary bus. 140 */ 141 uint32_t sc_privio_base; 142 uint32_t sc_privio_size; 143 uint32_t sc_privmem_base; 144 uint32_t sc_privmem_size; 145 146 uint8_t sc_sder; /* secondary decode enable register */ 147 148 /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */ 149 struct bus_space sc_pci_iot; 150 struct bus_space sc_pci_memt; 151 struct arm32_bus_dma_tag sc_pci_dmat; 152 struct arm32_pci_chipset sc_pci_chipset; 153 }; 154 155 extern struct bus_space i80312_bs_tag; 156 157 void i80312_sdram_bounds(bus_space_tag_t, bus_space_handle_t, 158 paddr_t *, psize_t *); 159 160 void i80312_attach(struct i80312_softc *); 161 162 void i80312_bs_init(bus_space_tag_t, void *); 163 void i80312_io_bs_init(bus_space_tag_t, void *); 164 void i80312_mem_bs_init(bus_space_tag_t, void *); 165 166 void i80312_pci_dma_init(bus_dma_tag_t, void *); 167 168 void i80312_pci_init(pci_chipset_tag_t, void *); 169 170 #endif /* _ARM_XSCALE_I80312VAR_H_ */ 171
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