i80321.c revision 1.1.2.7
1 1.1.2.7 nathanw /* $NetBSD: i80321.c,v 1.1.2.7 2002/10/18 02:35:42 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 2002 Wasabi Systems, Inc. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.1.2.2 nathanw * 9 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 11 1.1.2.2 nathanw * are met: 12 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.1.2.2 nathanw * must display the following acknowledgement: 19 1.1.2.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.1.2.2 nathanw * Wasabi Systems, Inc. 21 1.1.2.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.1.2.2 nathanw * or promote products derived from this software without specific prior 23 1.1.2.2 nathanw * written permission. 24 1.1.2.2 nathanw * 25 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.1.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.1.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.1.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.1.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.1.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.1.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.1.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.1.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.1.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.1.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.1.2.2 nathanw */ 37 1.1.2.2 nathanw 38 1.1.2.2 nathanw /* 39 1.1.2.2 nathanw * Autoconfiguration support for the Intel i80321 I/O Processor. 40 1.1.2.2 nathanw */ 41 1.1.2.2 nathanw 42 1.1.2.2 nathanw #include <sys/param.h> 43 1.1.2.2 nathanw #include <sys/systm.h> 44 1.1.2.2 nathanw #include <sys/device.h> 45 1.1.2.2 nathanw 46 1.1.2.5 nathanw #define _ARM32_BUS_DMA_PRIVATE 47 1.1.2.2 nathanw #include <machine/bus.h> 48 1.1.2.2 nathanw 49 1.1.2.2 nathanw #include <arm/xscale/i80321reg.h> 50 1.1.2.2 nathanw #include <arm/xscale/i80321var.h> 51 1.1.2.2 nathanw 52 1.1.2.2 nathanw /* 53 1.1.2.2 nathanw * Statically-allocated bus_space stucture used to access the 54 1.1.2.2 nathanw * i80321's own registers. 55 1.1.2.2 nathanw */ 56 1.1.2.2 nathanw struct bus_space i80321_bs_tag; 57 1.1.2.2 nathanw 58 1.1.2.2 nathanw /* 59 1.1.2.2 nathanw * There can be only one i80321, so we keep a global pointer to 60 1.1.2.2 nathanw * the softc, so board-specific code can use features of the 61 1.1.2.2 nathanw * i80321 without having to have a handle on the softc itself. 62 1.1.2.2 nathanw */ 63 1.1.2.2 nathanw struct i80321_softc *i80321_softc; 64 1.1.2.2 nathanw 65 1.1.2.5 nathanw static int i80321_iopxs_print(void *, const char *); 66 1.1.2.5 nathanw static int i80321_pcibus_print(void *, const char *); 67 1.1.2.2 nathanw 68 1.1.2.4 nathanw /* Built-in devices. */ 69 1.1.2.4 nathanw static const struct iopxs_device { 70 1.1.2.4 nathanw const char *id_name; 71 1.1.2.4 nathanw bus_addr_t id_offset; 72 1.1.2.4 nathanw bus_size_t id_size; 73 1.1.2.4 nathanw } iopxs_devices[] = { 74 1.1.2.4 nathanw { "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE }, 75 1.1.2.4 nathanw { "iopdma", VERDE_DMA_BASE, VERDE_DMA_SIZE }, 76 1.1.2.4 nathanw { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, 77 1.1.2.4 nathanw { "iopwdog", 0, 0 }, 78 1.1.2.4 nathanw { NULL, 0, 0 } 79 1.1.2.4 nathanw }; 80 1.1.2.4 nathanw 81 1.1.2.5 nathanw static void i80321_pci_dma_init(struct i80321_softc *); 82 1.1.2.5 nathanw static void i80321_local_dma_init(struct i80321_softc *); 83 1.1.2.5 nathanw 84 1.1.2.2 nathanw /* 85 1.1.2.2 nathanw * i80321_attach: 86 1.1.2.2 nathanw * 87 1.1.2.2 nathanw * Board-independent attach routine for the i80321. 88 1.1.2.2 nathanw */ 89 1.1.2.2 nathanw void 90 1.1.2.2 nathanw i80321_attach(struct i80321_softc *sc) 91 1.1.2.2 nathanw { 92 1.1.2.2 nathanw struct pcibus_attach_args pba; 93 1.1.2.4 nathanw const struct iopxs_device *id; 94 1.1.2.4 nathanw struct iopxs_attach_args ia; 95 1.1.2.2 nathanw pcireg_t preg; 96 1.1.2.2 nathanw 97 1.1.2.2 nathanw i80321_softc = sc; 98 1.1.2.2 nathanw 99 1.1.2.2 nathanw /* 100 1.1.2.2 nathanw * Slice off some useful subregion handles. 101 1.1.2.2 nathanw */ 102 1.1.2.2 nathanw 103 1.1.2.2 nathanw if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 104 1.1.2.2 nathanw VERDE_ATU_SIZE, &sc->sc_atu_sh)) 105 1.1.2.7 nathanw panic("%s: unable to subregion ATU registers", 106 1.1.2.2 nathanw sc->sc_dev.dv_xname); 107 1.1.2.2 nathanw 108 1.1.2.2 nathanw /* We expect the Memory Controller to be already sliced off. */ 109 1.1.2.2 nathanw 110 1.1.2.2 nathanw /* 111 1.1.2.2 nathanw * Program the Inbound windows. 112 1.1.2.2 nathanw */ 113 1.1.2.2 nathanw if (sc->sc_is_host) { 114 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 115 1.1.2.2 nathanw PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo); 116 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 117 1.1.2.2 nathanw PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi); 118 1.1.2.2 nathanw } 119 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 120 1.1.2.2 nathanw (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0); 121 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0, 122 1.1.2.2 nathanw sc->sc_iwin[0].iwin_xlate); 123 1.1.2.2 nathanw 124 1.1.2.2 nathanw if (sc->sc_is_host) { 125 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 126 1.1.2.2 nathanw PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo); 127 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 128 1.1.2.2 nathanw PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi); 129 1.1.2.2 nathanw } 130 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, 131 1.1.2.2 nathanw (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0); 132 1.1.2.2 nathanw /* no xlate for window 1 */ 133 1.1.2.2 nathanw 134 1.1.2.2 nathanw if (sc->sc_is_host) { 135 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 136 1.1.2.2 nathanw PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo); 137 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 138 1.1.2.2 nathanw PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi); 139 1.1.2.2 nathanw } 140 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 141 1.1.2.2 nathanw (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0); 142 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2, 143 1.1.2.2 nathanw sc->sc_iwin[2].iwin_xlate); 144 1.1.2.2 nathanw 145 1.1.2.2 nathanw if (sc->sc_is_host) { 146 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 147 1.1.2.2 nathanw ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo); 148 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 149 1.1.2.2 nathanw ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi); 150 1.1.2.2 nathanw } 151 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3, 152 1.1.2.2 nathanw (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0); 153 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3, 154 1.1.2.2 nathanw sc->sc_iwin[3].iwin_xlate); 155 1.1.2.2 nathanw 156 1.1.2.2 nathanw /* 157 1.1.2.2 nathanw * Mask (disable) the ATU interrupt sources. 158 1.1.2.2 nathanw * XXX May want to revisit this if we encounter 159 1.1.2.2 nathanw * XXX an application that wants it. 160 1.1.2.2 nathanw */ 161 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 162 1.1.2.2 nathanw ATU_ATUIMR, 163 1.1.2.2 nathanw ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST| 164 1.1.2.2 nathanw ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM| 165 1.1.2.2 nathanw ATUIMR_PTAT|ATUIMR_PMPE); 166 1.1.2.2 nathanw 167 1.1.2.2 nathanw /* 168 1.1.2.2 nathanw * Program the outbound windows. 169 1.1.2.2 nathanw */ 170 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 171 1.1.2.2 nathanw ATU_OIOWTVR, sc->sc_ioout_xlate); 172 1.1.2.2 nathanw 173 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 174 1.1.2.2 nathanw ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo); 175 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 176 1.1.2.2 nathanw ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi); 177 1.1.2.2 nathanw 178 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 179 1.1.2.2 nathanw ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo); 180 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 181 1.1.2.2 nathanw ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi); 182 1.1.2.2 nathanw 183 1.1.2.2 nathanw /* 184 1.1.2.2 nathanw * Set up the ATU configuration register. All we do 185 1.1.2.2 nathanw * right now is enable Outbound Windows. 186 1.1.2.2 nathanw */ 187 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR, 188 1.1.2.2 nathanw ATUCR_OUT_EN); 189 1.1.2.2 nathanw 190 1.1.2.2 nathanw /* 191 1.1.2.2 nathanw * Enable bus mastering, memory access, SERR, and parity 192 1.1.2.2 nathanw * checking on the ATU. 193 1.1.2.2 nathanw */ 194 1.1.2.2 nathanw if (sc->sc_is_host) { 195 1.1.2.2 nathanw preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 196 1.1.2.2 nathanw PCI_COMMAND_STATUS_REG); 197 1.1.2.2 nathanw preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 198 1.1.2.2 nathanw PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 199 1.1.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 200 1.1.2.2 nathanw PCI_COMMAND_STATUS_REG, preg); 201 1.1.2.2 nathanw } 202 1.1.2.2 nathanw 203 1.1.2.4 nathanw /* Initialize the bus space tags. */ 204 1.1.2.2 nathanw i80321_io_bs_init(&sc->sc_pci_iot, sc); 205 1.1.2.2 nathanw i80321_mem_bs_init(&sc->sc_pci_memt, sc); 206 1.1.2.4 nathanw 207 1.1.2.4 nathanw /* Initialize the PCI chipset tag. */ 208 1.1.2.2 nathanw i80321_pci_init(&sc->sc_pci_chipset, sc); 209 1.1.2.2 nathanw 210 1.1.2.4 nathanw /* Initialize the DMA tags. */ 211 1.1.2.5 nathanw i80321_pci_dma_init(sc); 212 1.1.2.5 nathanw i80321_local_dma_init(sc); 213 1.1.2.4 nathanw 214 1.1.2.4 nathanw /* 215 1.1.2.4 nathanw * Attach all the IOP built-ins. 216 1.1.2.4 nathanw */ 217 1.1.2.4 nathanw for (id = iopxs_devices; id->id_name != NULL; id++) { 218 1.1.2.4 nathanw ia.ia_name = id->id_name; 219 1.1.2.4 nathanw ia.ia_st = sc->sc_st; 220 1.1.2.4 nathanw ia.ia_sh = sc->sc_sh; 221 1.1.2.4 nathanw ia.ia_dmat = &sc->sc_local_dmat; 222 1.1.2.4 nathanw ia.ia_offset = id->id_offset; 223 1.1.2.4 nathanw ia.ia_size = id->id_size; 224 1.1.2.4 nathanw 225 1.1.2.4 nathanw (void) config_found(&sc->sc_dev, &ia, i80321_iopxs_print); 226 1.1.2.4 nathanw } 227 1.1.2.4 nathanw 228 1.1.2.2 nathanw /* 229 1.1.2.2 nathanw * Attach the PCI bus. 230 1.1.2.2 nathanw */ 231 1.1.2.2 nathanw preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 232 1.1.2.2 nathanw preg = PCIXSR_BUSNO(preg); 233 1.1.2.2 nathanw if (preg == 0xff) 234 1.1.2.2 nathanw preg = 0; 235 1.1.2.2 nathanw pba.pba_busname = "pci"; 236 1.1.2.2 nathanw pba.pba_iot = &sc->sc_pci_iot; 237 1.1.2.2 nathanw pba.pba_memt = &sc->sc_pci_memt; 238 1.1.2.2 nathanw pba.pba_dmat = &sc->sc_pci_dmat; 239 1.1.2.2 nathanw pba.pba_pc = &sc->sc_pci_chipset; 240 1.1.2.2 nathanw pba.pba_bus = preg; 241 1.1.2.3 nathanw pba.pba_bridgetag = NULL; 242 1.1.2.2 nathanw pba.pba_intrswiz = 0; /* XXX what if busno != 0? */ 243 1.1.2.2 nathanw pba.pba_intrtag = 0; 244 1.1.2.2 nathanw pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 245 1.1.2.2 nathanw PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 246 1.1.2.2 nathanw (void) config_found(&sc->sc_dev, &pba, i80321_pcibus_print); 247 1.1.2.2 nathanw } 248 1.1.2.2 nathanw 249 1.1.2.2 nathanw /* 250 1.1.2.4 nathanw * i80321_iopxs_print: 251 1.1.2.4 nathanw * 252 1.1.2.4 nathanw * Autoconfiguration cfprint routine when attaching 253 1.1.2.4 nathanw * to the "iopxs" device. 254 1.1.2.4 nathanw */ 255 1.1.2.5 nathanw static int 256 1.1.2.4 nathanw i80321_iopxs_print(void *aux, const char *pnp) 257 1.1.2.4 nathanw { 258 1.1.2.4 nathanw 259 1.1.2.4 nathanw return (QUIET); 260 1.1.2.4 nathanw } 261 1.1.2.4 nathanw 262 1.1.2.4 nathanw /* 263 1.1.2.2 nathanw * i80321_pcibus_print: 264 1.1.2.2 nathanw * 265 1.1.2.2 nathanw * Autoconfiguration cfprint routine when attaching 266 1.1.2.2 nathanw * to the "pcibus" attribute. 267 1.1.2.2 nathanw */ 268 1.1.2.5 nathanw static int 269 1.1.2.2 nathanw i80321_pcibus_print(void *aux, const char *pnp) 270 1.1.2.2 nathanw { 271 1.1.2.2 nathanw struct pcibus_attach_args *pba = aux; 272 1.1.2.2 nathanw 273 1.1.2.2 nathanw if (pnp) 274 1.1.2.2 nathanw printf("%s at %s", pba->pba_busname, pnp); 275 1.1.2.2 nathanw 276 1.1.2.2 nathanw printf(" bus %d", pba->pba_bus); 277 1.1.2.2 nathanw 278 1.1.2.2 nathanw return (UNCONF); 279 1.1.2.2 nathanw } 280 1.1.2.5 nathanw 281 1.1.2.5 nathanw /* 282 1.1.2.5 nathanw * i80321_pci_dma_init: 283 1.1.2.5 nathanw * 284 1.1.2.5 nathanw * Initialize the PCI DMA tag. 285 1.1.2.5 nathanw */ 286 1.1.2.5 nathanw static void 287 1.1.2.5 nathanw i80321_pci_dma_init(struct i80321_softc *sc) 288 1.1.2.5 nathanw { 289 1.1.2.5 nathanw bus_dma_tag_t dmat = &sc->sc_pci_dmat; 290 1.1.2.5 nathanw struct arm32_dma_range *dr = &sc->sc_pci_dma_range; 291 1.1.2.5 nathanw 292 1.1.2.5 nathanw dr->dr_sysbase = sc->sc_iwin[2].iwin_xlate; 293 1.1.2.5 nathanw dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo); 294 1.1.2.5 nathanw dr->dr_len = sc->sc_iwin[2].iwin_size; 295 1.1.2.5 nathanw 296 1.1.2.5 nathanw dmat->_ranges = dr; 297 1.1.2.5 nathanw dmat->_nranges = 1; 298 1.1.2.5 nathanw 299 1.1.2.5 nathanw dmat->_dmamap_create = _bus_dmamap_create; 300 1.1.2.5 nathanw dmat->_dmamap_destroy = _bus_dmamap_destroy; 301 1.1.2.5 nathanw dmat->_dmamap_load = _bus_dmamap_load; 302 1.1.2.5 nathanw dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 303 1.1.2.5 nathanw dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 304 1.1.2.5 nathanw dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 305 1.1.2.5 nathanw dmat->_dmamap_unload = _bus_dmamap_unload; 306 1.1.2.6 thorpej dmat->_dmamap_sync_pre = _bus_dmamap_sync; 307 1.1.2.6 thorpej dmat->_dmamap_sync_post = NULL; 308 1.1.2.5 nathanw 309 1.1.2.5 nathanw dmat->_dmamem_alloc = _bus_dmamem_alloc; 310 1.1.2.5 nathanw dmat->_dmamem_free = _bus_dmamem_free; 311 1.1.2.5 nathanw dmat->_dmamem_map = _bus_dmamem_map; 312 1.1.2.5 nathanw dmat->_dmamem_unmap = _bus_dmamem_unmap; 313 1.1.2.5 nathanw dmat->_dmamem_mmap = _bus_dmamem_mmap; 314 1.1.2.5 nathanw } 315 1.1.2.5 nathanw 316 1.1.2.5 nathanw /* 317 1.1.2.5 nathanw * i80321_local_dma_init: 318 1.1.2.5 nathanw * 319 1.1.2.5 nathanw * Initialize the local DMA tag. 320 1.1.2.5 nathanw */ 321 1.1.2.5 nathanw static void 322 1.1.2.5 nathanw i80321_local_dma_init(struct i80321_softc *sc) 323 1.1.2.5 nathanw { 324 1.1.2.5 nathanw bus_dma_tag_t dmat = &sc->sc_local_dmat; 325 1.1.2.5 nathanw 326 1.1.2.5 nathanw dmat->_ranges = NULL; 327 1.1.2.5 nathanw dmat->_nranges = 0; 328 1.1.2.5 nathanw 329 1.1.2.5 nathanw dmat->_dmamap_create = _bus_dmamap_create; 330 1.1.2.5 nathanw dmat->_dmamap_destroy = _bus_dmamap_destroy; 331 1.1.2.5 nathanw dmat->_dmamap_load = _bus_dmamap_load; 332 1.1.2.5 nathanw dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 333 1.1.2.5 nathanw dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 334 1.1.2.5 nathanw dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 335 1.1.2.5 nathanw dmat->_dmamap_unload = _bus_dmamap_unload; 336 1.1.2.6 thorpej dmat->_dmamap_sync_pre = _bus_dmamap_sync; 337 1.1.2.6 thorpej dmat->_dmamap_sync_post = NULL; 338 1.1.2.5 nathanw 339 1.1.2.5 nathanw dmat->_dmamem_alloc = _bus_dmamem_alloc; 340 1.1.2.5 nathanw dmat->_dmamem_free = _bus_dmamem_free; 341 1.1.2.5 nathanw dmat->_dmamem_map = _bus_dmamem_map; 342 1.1.2.5 nathanw dmat->_dmamem_unmap = _bus_dmamem_unmap; 343 1.1.2.5 nathanw dmat->_dmamem_mmap = _bus_dmamem_mmap; 344 1.1.2.5 nathanw } 345
Indexes created Mon Oct 27 08:10:08 GMT 2025