i80321.c revision 1.11
1 /* $NetBSD: i80321.c,v 1.11 2003/01/23 03:56:45 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80321 I/O Processor. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 49 #include <arm/xscale/i80321reg.h> 50 #include <arm/xscale/i80321var.h> 51 52 /* 53 * Statically-allocated bus_space stucture used to access the 54 * i80321's own registers. 55 */ 56 struct bus_space i80321_bs_tag; 57 58 /* 59 * There can be only one i80321, so we keep a global pointer to 60 * the softc, so board-specific code can use features of the 61 * i80321 without having to have a handle on the softc itself. 62 */ 63 struct i80321_softc *i80321_softc; 64 65 static int i80321_iopxs_print(void *, const char *); 66 static int i80321_pcibus_print(void *, const char *); 67 68 /* Built-in devices. */ 69 static const struct iopxs_device { 70 const char *id_name; 71 bus_addr_t id_offset; 72 bus_size_t id_size; 73 } iopxs_devices[] = { 74 { "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE }, 75 { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, 76 { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, 77 { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, 78 { "iopwdog", 0, 0 }, 79 { NULL, 0, 0 } 80 }; 81 82 static void i80321_pci_dma_init(struct i80321_softc *); 83 static void i80321_local_dma_init(struct i80321_softc *); 84 85 /* 86 * i80321_attach: 87 * 88 * Board-independent attach routine for the i80321. 89 */ 90 void 91 i80321_attach(struct i80321_softc *sc) 92 { 93 struct pcibus_attach_args pba; 94 const struct iopxs_device *id; 95 struct iopxs_attach_args ia; 96 pcireg_t preg; 97 98 i80321_softc = sc; 99 100 /* 101 * Slice off some useful subregion handles. 102 */ 103 104 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 105 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 106 panic("%s: unable to subregion ATU registers", 107 sc->sc_dev.dv_xname); 108 109 /* We expect the Memory Controller to be already sliced off. */ 110 111 /* 112 * Program the Inbound windows. 113 */ 114 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 115 (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0); 116 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0, 117 sc->sc_iwin[0].iwin_xlate); 118 if (sc->sc_is_host) { 119 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 120 PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo); 121 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 122 PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi); 123 } 124 125 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, 126 (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0); 127 /* no xlate for window 1 */ 128 if (sc->sc_is_host) { 129 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 130 PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo); 131 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 132 PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi); 133 } 134 135 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 136 (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0); 137 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2, 138 sc->sc_iwin[2].iwin_xlate); 139 if (sc->sc_is_host) { 140 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 141 PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo); 142 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 143 PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi); 144 } 145 146 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3, 147 (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0); 148 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3, 149 sc->sc_iwin[3].iwin_xlate); 150 if (sc->sc_is_host) { 151 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 152 ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo); 153 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 154 ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi); 155 } 156 157 /* 158 * Mask (disable) the ATU interrupt sources. 159 * XXX May want to revisit this if we encounter 160 * XXX an application that wants it. 161 */ 162 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 163 ATU_ATUIMR, 164 ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST| 165 ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM| 166 ATUIMR_PTAT|ATUIMR_PMPE); 167 168 /* 169 * Program the outbound windows. 170 */ 171 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 172 ATU_OIOWTVR, sc->sc_ioout_xlate); 173 174 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 175 ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo); 176 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 177 ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi); 178 179 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 180 ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo); 181 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 182 ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi); 183 184 /* 185 * Set up the ATU configuration register. All we do 186 * right now is enable Outbound Windows. 187 */ 188 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR, 189 ATUCR_OUT_EN); 190 191 /* 192 * Enable bus mastering, memory access, SERR, and parity 193 * checking on the ATU. 194 */ 195 if (sc->sc_is_host) { 196 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 197 PCI_COMMAND_STATUS_REG); 198 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 199 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 200 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 201 PCI_COMMAND_STATUS_REG, preg); 202 } 203 204 /* Initialize the bus space tags. */ 205 i80321_io_bs_init(&sc->sc_pci_iot, sc); 206 i80321_mem_bs_init(&sc->sc_pci_memt, sc); 207 208 /* Initialize the PCI chipset tag. */ 209 i80321_pci_init(&sc->sc_pci_chipset, sc); 210 211 /* Initialize the DMA tags. */ 212 i80321_pci_dma_init(sc); 213 i80321_local_dma_init(sc); 214 215 /* 216 * Attach all the IOP built-ins. 217 */ 218 for (id = iopxs_devices; id->id_name != NULL; id++) { 219 ia.ia_name = id->id_name; 220 ia.ia_st = sc->sc_st; 221 ia.ia_sh = sc->sc_sh; 222 ia.ia_dmat = &sc->sc_local_dmat; 223 ia.ia_offset = id->id_offset; 224 ia.ia_size = id->id_size; 225 226 (void) config_found(&sc->sc_dev, &ia, i80321_iopxs_print); 227 } 228 229 /* 230 * Attach the PCI bus. 231 */ 232 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 233 preg = PCIXSR_BUSNO(preg); 234 if (preg == 0xff) 235 preg = 0; 236 pba.pba_busname = "pci"; 237 pba.pba_iot = &sc->sc_pci_iot; 238 pba.pba_memt = &sc->sc_pci_memt; 239 pba.pba_dmat = &sc->sc_pci_dmat; 240 pba.pba_pc = &sc->sc_pci_chipset; 241 pba.pba_bus = preg; 242 pba.pba_bridgetag = NULL; 243 pba.pba_intrswiz = 0; /* XXX what if busno != 0? */ 244 pba.pba_intrtag = 0; 245 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 246 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 247 (void) config_found(&sc->sc_dev, &pba, i80321_pcibus_print); 248 } 249 250 /* 251 * i80321_iopxs_print: 252 * 253 * Autoconfiguration cfprint routine when attaching 254 * to the "iopxs" device. 255 */ 256 static int 257 i80321_iopxs_print(void *aux, const char *pnp) 258 { 259 260 return (QUIET); 261 } 262 263 /* 264 * i80321_pcibus_print: 265 * 266 * Autoconfiguration cfprint routine when attaching 267 * to the "pcibus" attribute. 268 */ 269 static int 270 i80321_pcibus_print(void *aux, const char *pnp) 271 { 272 struct pcibus_attach_args *pba = aux; 273 274 if (pnp) 275 aprint_normal("%s at %s", pba->pba_busname, pnp); 276 277 aprint_normal(" bus %d", pba->pba_bus); 278 279 return (UNCONF); 280 } 281 282 /* 283 * i80321_pci_dma_init: 284 * 285 * Initialize the PCI DMA tag. 286 */ 287 static void 288 i80321_pci_dma_init(struct i80321_softc *sc) 289 { 290 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 291 struct arm32_dma_range *dr = &sc->sc_pci_dma_range; 292 293 dr->dr_sysbase = sc->sc_iwin[3].iwin_xlate; 294 dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo); 295 dr->dr_len = sc->sc_iwin[3].iwin_size; 296 297 dmat->_ranges = dr; 298 dmat->_nranges = 1; 299 300 dmat->_dmamap_create = _bus_dmamap_create; 301 dmat->_dmamap_destroy = _bus_dmamap_destroy; 302 dmat->_dmamap_load = _bus_dmamap_load; 303 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 304 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 305 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 306 dmat->_dmamap_unload = _bus_dmamap_unload; 307 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 308 dmat->_dmamap_sync_post = NULL; 309 310 dmat->_dmamem_alloc = _bus_dmamem_alloc; 311 dmat->_dmamem_free = _bus_dmamem_free; 312 dmat->_dmamem_map = _bus_dmamem_map; 313 dmat->_dmamem_unmap = _bus_dmamem_unmap; 314 dmat->_dmamem_mmap = _bus_dmamem_mmap; 315 } 316 317 /* 318 * i80321_local_dma_init: 319 * 320 * Initialize the local DMA tag. 321 */ 322 static void 323 i80321_local_dma_init(struct i80321_softc *sc) 324 { 325 bus_dma_tag_t dmat = &sc->sc_local_dmat; 326 327 dmat->_ranges = NULL; 328 dmat->_nranges = 0; 329 330 dmat->_dmamap_create = _bus_dmamap_create; 331 dmat->_dmamap_destroy = _bus_dmamap_destroy; 332 dmat->_dmamap_load = _bus_dmamap_load; 333 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 334 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 335 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 336 dmat->_dmamap_unload = _bus_dmamap_unload; 337 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 338 dmat->_dmamap_sync_post = NULL; 339 340 dmat->_dmamem_alloc = _bus_dmamem_alloc; 341 dmat->_dmamem_free = _bus_dmamem_free; 342 dmat->_dmamem_map = _bus_dmamem_map; 343 dmat->_dmamem_unmap = _bus_dmamem_unmap; 344 dmat->_dmamem_mmap = _bus_dmamem_mmap; 345 } 346
Indexes created Thu Oct 23 22:10:10 GMT 2025