i80321.c revision 1.13.2.1
1 /* $NetBSD: i80321.c,v 1.13.2.1 2004/08/03 10:32:58 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Autoconfiguration support for the Intel i80321 I/O Processor. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321.c,v 1.13.2.1 2004/08/03 10:32:58 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #define _ARM32_BUS_DMA_PRIVATE 50 #include <machine/bus.h> 51 52 #include <arm/xscale/i80321reg.h> 53 #include <arm/xscale/i80321var.h> 54 55 /* 56 * Statically-allocated bus_space stucture used to access the 57 * i80321's own registers. 58 */ 59 struct bus_space i80321_bs_tag; 60 61 /* 62 * There can be only one i80321, so we keep a global pointer to 63 * the softc, so board-specific code can use features of the 64 * i80321 without having to have a handle on the softc itself. 65 */ 66 struct i80321_softc *i80321_softc; 67 68 static int i80321_iopxs_print(void *, const char *); 69 static int i80321_pcibus_print(void *, const char *); 70 71 /* Built-in devices. */ 72 static const struct iopxs_device { 73 const char *id_name; 74 bus_addr_t id_offset; 75 bus_size_t id_size; 76 } iopxs_devices[] = { 77 { "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE }, 78 /* { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, */ 79 /* { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, */ 80 { "iopiic", VERDE_I2C_BASE0, VERDE_I2C_CHSIZE }, 81 { "iopiic", VERDE_I2C_BASE1, VERDE_I2C_CHSIZE }, 82 /* { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, */ 83 { "iopmu", VERDE_MU_BASE, VERDE_MU_SIZE }, 84 { "iopwdog", 0, 0 }, 85 { NULL, 0, 0 } 86 }; 87 88 static void i80321_pci_dma_init(struct i80321_softc *); 89 90 /* 91 * i80321_attach: 92 * 93 * Board-independent attach routine for the i80321. 94 */ 95 void 96 i80321_attach(struct i80321_softc *sc) 97 { 98 struct pcibus_attach_args pba; 99 const struct iopxs_device *id; 100 struct iopxs_attach_args ia; 101 pcireg_t preg; 102 103 i80321_softc = sc; 104 105 /* 106 * Slice off some useful subregion handles. 107 */ 108 109 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 110 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 111 panic("%s: unable to subregion ATU registers", 112 sc->sc_dev.dv_xname); 113 114 /* We expect the Memory Controller to be already sliced off. */ 115 116 /* 117 * Program the Inbound windows. 118 */ 119 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 120 (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0); 121 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0, 122 sc->sc_iwin[0].iwin_xlate); 123 if (sc->sc_is_host) { 124 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 125 PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo); 126 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 127 PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi); 128 } else { 129 sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st, 130 sc->sc_atu_sh, PCI_MAPREG_START); 131 sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st, 132 sc->sc_atu_sh, PCI_MAPREG_START + 0x04); 133 sc->sc_iwin[0].iwin_base_lo = 134 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo); 135 } 136 137 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, 138 (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0); 139 /* no xlate for window 1 */ 140 if (sc->sc_is_host) { 141 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 142 PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo); 143 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 144 PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi); 145 } else { 146 sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st, 147 sc->sc_atu_sh, PCI_MAPREG_START + 0x08); 148 sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st, 149 sc->sc_atu_sh, PCI_MAPREG_START + 0x0c); 150 sc->sc_iwin[1].iwin_base_lo = 151 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 152 } 153 154 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 155 (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0); 156 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2, 157 sc->sc_iwin[2].iwin_xlate); 158 if (sc->sc_is_host) { 159 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 160 PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo); 161 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 162 PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi); 163 } else { 164 sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st, 165 sc->sc_atu_sh, PCI_MAPREG_START + 0x10); 166 sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st, 167 sc->sc_atu_sh, PCI_MAPREG_START + 0x14); 168 sc->sc_iwin[2].iwin_base_lo = 169 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo); 170 } 171 172 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3, 173 (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0); 174 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3, 175 sc->sc_iwin[3].iwin_xlate); 176 if (sc->sc_is_host) { 177 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 178 ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo); 179 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 180 ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi); 181 } else { 182 sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st, 183 sc->sc_atu_sh, ATU_IABAR3); 184 sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st, 185 sc->sc_atu_sh, ATU_IAUBAR3); 186 sc->sc_iwin[3].iwin_base_lo = 187 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo); 188 } 189 190 /* 191 * Mask (disable) the ATU interrupt sources. 192 * XXX May want to revisit this if we encounter 193 * XXX an application that wants it. 194 */ 195 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 196 ATU_ATUIMR, 197 ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST| 198 ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM| 199 ATUIMR_PTAT|ATUIMR_PMPE); 200 201 /* 202 * Program the outbound windows. 203 */ 204 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 205 ATU_OIOWTVR, sc->sc_ioout_xlate); 206 207 if (!sc->sc_is_host) { 208 sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo; 209 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 210 } 211 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 212 ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo); 213 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 214 ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi); 215 216 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 217 ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo); 218 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 219 ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi); 220 221 /* 222 * Set up the ATU configuration register. All we do 223 * right now is enable Outbound Windows. 224 */ 225 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR, 226 ATUCR_OUT_EN); 227 228 /* 229 * Enable bus mastering, memory access, SERR, and parity 230 * checking on the ATU. 231 */ 232 if (sc->sc_is_host) { 233 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 234 PCI_COMMAND_STATUS_REG); 235 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE | 236 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 237 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, 238 PCI_COMMAND_STATUS_REG, preg); 239 } 240 241 /* Initialize the bus space tags. */ 242 i80321_io_bs_init(&sc->sc_pci_iot, sc); 243 i80321_mem_bs_init(&sc->sc_pci_memt, sc); 244 245 /* Initialize the PCI chipset tag. */ 246 i80321_pci_init(&sc->sc_pci_chipset, sc); 247 248 /* Initialize the DMA tags. */ 249 i80321_pci_dma_init(sc); 250 i80321_local_dma_init(sc); 251 252 /* 253 * Attach all the IOP built-ins. 254 */ 255 for (id = iopxs_devices; id->id_name != NULL; id++) { 256 ia.ia_name = id->id_name; 257 ia.ia_st = sc->sc_st; 258 ia.ia_sh = sc->sc_sh; 259 ia.ia_dmat = &sc->sc_local_dmat; 260 ia.ia_offset = id->id_offset; 261 ia.ia_size = id->id_size; 262 263 (void) config_found(&sc->sc_dev, &ia, i80321_iopxs_print); 264 } 265 266 /* 267 * Attach the PCI bus. 268 */ 269 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 270 preg = PCIXSR_BUSNO(preg); 271 if (preg == 0xff) 272 preg = 0; 273 pba.pba_busname = "pci"; 274 pba.pba_iot = &sc->sc_pci_iot; 275 pba.pba_memt = &sc->sc_pci_memt; 276 pba.pba_dmat = &sc->sc_pci_dmat; 277 pba.pba_dmat64 = NULL; 278 pba.pba_pc = &sc->sc_pci_chipset; 279 pba.pba_bus = preg; 280 pba.pba_bridgetag = NULL; 281 pba.pba_intrswiz = 0; /* XXX what if busno != 0? */ 282 pba.pba_intrtag = 0; 283 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 284 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 285 (void) config_found(&sc->sc_dev, &pba, i80321_pcibus_print); 286 } 287 288 /* 289 * i80321_iopxs_print: 290 * 291 * Autoconfiguration cfprint routine when attaching 292 * to the "iopxs" device. 293 */ 294 static int 295 i80321_iopxs_print(void *aux, const char *pnp) 296 { 297 298 return (QUIET); 299 } 300 301 /* 302 * i80321_pcibus_print: 303 * 304 * Autoconfiguration cfprint routine when attaching 305 * to the "pcibus" attribute. 306 */ 307 static int 308 i80321_pcibus_print(void *aux, const char *pnp) 309 { 310 struct pcibus_attach_args *pba = aux; 311 312 if (pnp) 313 aprint_normal("%s at %s", pba->pba_busname, pnp); 314 315 aprint_normal(" bus %d", pba->pba_bus); 316 317 return (UNCONF); 318 } 319 320 /* 321 * i80321_pci_dma_init: 322 * 323 * Initialize the PCI DMA tag. 324 */ 325 static void 326 i80321_pci_dma_init(struct i80321_softc *sc) 327 { 328 bus_dma_tag_t dmat = &sc->sc_pci_dmat; 329 struct arm32_dma_range *dr = &sc->sc_pci_dma_range; 330 331 dr->dr_sysbase = sc->sc_iwin[2].iwin_xlate; 332 dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo); 333 dr->dr_len = sc->sc_iwin[2].iwin_size; 334 335 dmat->_ranges = dr; 336 dmat->_nranges = 1; 337 338 dmat->_dmamap_create = _bus_dmamap_create; 339 dmat->_dmamap_destroy = _bus_dmamap_destroy; 340 dmat->_dmamap_load = _bus_dmamap_load; 341 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 342 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 343 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 344 dmat->_dmamap_unload = _bus_dmamap_unload; 345 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 346 dmat->_dmamap_sync_post = NULL; 347 348 dmat->_dmamem_alloc = _bus_dmamem_alloc; 349 dmat->_dmamem_free = _bus_dmamem_free; 350 dmat->_dmamem_map = _bus_dmamem_map; 351 dmat->_dmamem_unmap = _bus_dmamem_unmap; 352 dmat->_dmamem_mmap = _bus_dmamem_mmap; 353 } 354 355 /* 356 * i80321_local_dma_init: 357 * 358 * Initialize the local DMA tag. 359 */ 360 void 361 i80321_local_dma_init(struct i80321_softc *sc) 362 { 363 bus_dma_tag_t dmat = &sc->sc_local_dmat; 364 365 dmat->_ranges = NULL; 366 dmat->_nranges = 0; 367 368 dmat->_dmamap_create = _bus_dmamap_create; 369 dmat->_dmamap_destroy = _bus_dmamap_destroy; 370 dmat->_dmamap_load = _bus_dmamap_load; 371 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; 372 dmat->_dmamap_load_uio = _bus_dmamap_load_uio; 373 dmat->_dmamap_load_raw = _bus_dmamap_load_raw; 374 dmat->_dmamap_unload = _bus_dmamap_unload; 375 dmat->_dmamap_sync_pre = _bus_dmamap_sync; 376 dmat->_dmamap_sync_post = NULL; 377 378 dmat->_dmamem_alloc = _bus_dmamem_alloc; 379 dmat->_dmamem_free = _bus_dmamem_free; 380 dmat->_dmamem_map = _bus_dmamem_map; 381 dmat->_dmamem_unmap = _bus_dmamem_unmap; 382 dmat->_dmamem_mmap = _bus_dmamem_mmap; 383 } 384
Indexes created Mon Oct 27 04:09:48 GMT 2025