i80321_intr.h revision 1.9 1 1.9 scw /* $NetBSD: i80321_intr.h,v 1.9 2006/11/08 23:45:41 scw Exp $ */
2 1.1 briggs
3 1.1 briggs /*
4 1.9 scw * Copyright (c) 2001, 2002, 2006 Wasabi Systems, Inc.
5 1.1 briggs * All rights reserved.
6 1.1 briggs *
7 1.9 scw * Written by Jason R. Thorpe and Steve C. Woodford for Wasabi Systems, Inc.
8 1.1 briggs *
9 1.1 briggs * Redistribution and use in source and binary forms, with or without
10 1.1 briggs * modification, are permitted provided that the following conditions
11 1.1 briggs * are met:
12 1.1 briggs * 1. Redistributions of source code must retain the above copyright
13 1.1 briggs * notice, this list of conditions and the following disclaimer.
14 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 briggs * notice, this list of conditions and the following disclaimer in the
16 1.1 briggs * documentation and/or other materials provided with the distribution.
17 1.1 briggs * 3. All advertising materials mentioning features or use of this software
18 1.1 briggs * must display the following acknowledgement:
19 1.1 briggs * This product includes software developed for the NetBSD Project by
20 1.1 briggs * Wasabi Systems, Inc.
21 1.1 briggs * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 briggs * or promote products derived from this software without specific prior
23 1.1 briggs * written permission.
24 1.1 briggs *
25 1.1 briggs * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 briggs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 briggs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 briggs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 briggs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 briggs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 briggs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 briggs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 briggs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 briggs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 briggs * POSSIBILITY OF SUCH DAMAGE.
36 1.1 briggs */
37 1.1 briggs
38 1.1 briggs #ifndef _I80321_INTR_H_
39 1.1 briggs #define _I80321_INTR_H_
40 1.1 briggs
41 1.3 thorpej #define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch)
42 1.3 thorpej
43 1.3 thorpej #ifndef _LOCORE
44 1.3 thorpej
45 1.1 briggs #include <arm/armreg.h>
46 1.1 briggs #include <arm/cpufunc.h>
47 1.1 briggs
48 1.1 briggs #include <arm/xscale/i80321reg.h>
49 1.1 briggs
50 1.2 thorpej void i80321_do_pending(void);
51 1.2 thorpej
52 1.7 perry static inline void __attribute__((__unused__))
53 1.1 briggs i80321_set_intrmask(void)
54 1.1 briggs {
55 1.7 perry extern volatile uint32_t intr_enabled;
56 1.1 briggs
57 1.7 perry __asm volatile("mcr p6, 0, %0, c0, c0, 0"
58 1.1 briggs :
59 1.1 briggs : "r" (intr_enabled & ICU_INT_HWMASK));
60 1.1 briggs }
61 1.1 briggs
62 1.8 simonb #define INT_SWMASK \
63 1.8 simonb ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
64 1.8 simonb (1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
65 1.1 briggs
66 1.9 scw #define INT_HPIMASK (1u << ICU_INT_HPI)
67 1.9 scw
68 1.7 perry static inline void __attribute__((__unused__))
69 1.1 briggs i80321_splx(int new)
70 1.1 briggs {
71 1.7 perry extern volatile uint32_t intr_enabled;
72 1.7 perry extern volatile int current_spl_level;
73 1.7 perry extern volatile int i80321_ipending;
74 1.1 briggs extern void i80321_do_pending(void);
75 1.1 briggs int oldirqstate, hwpend;
76 1.1 briggs
77 1.5 scw /* Don't let the compiler re-order this code with preceding code */
78 1.5 scw __insn_barrier();
79 1.5 scw
80 1.1 briggs current_spl_level = new;
81 1.1 briggs
82 1.1 briggs hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
83 1.1 briggs if (hwpend != 0) {
84 1.1 briggs oldirqstate = disable_interrupts(I32_bit);
85 1.1 briggs intr_enabled |= hwpend;
86 1.1 briggs i80321_set_intrmask();
87 1.9 scw #ifdef I80321_HPI_ENABLED
88 1.9 scw if (__predict_false(hwpend & INT_HPIMASK))
89 1.9 scw oldirqstate &= ~I32_bit;
90 1.9 scw #endif
91 1.1 briggs restore_interrupts(oldirqstate);
92 1.1 briggs }
93 1.1 briggs
94 1.1 briggs if ((i80321_ipending & INT_SWMASK) & ~new)
95 1.1 briggs i80321_do_pending();
96 1.1 briggs }
97 1.1 briggs
98 1.7 perry static inline int __attribute__((__unused__))
99 1.1 briggs i80321_splraise(int ipl)
100 1.1 briggs {
101 1.7 perry extern volatile int current_spl_level;
102 1.1 briggs extern int i80321_imask[];
103 1.1 briggs int old;
104 1.1 briggs
105 1.1 briggs old = current_spl_level;
106 1.1 briggs current_spl_level |= i80321_imask[ipl];
107 1.1 briggs
108 1.5 scw /* Don't let the compiler re-order this code with subsequent code */
109 1.5 scw __insn_barrier();
110 1.5 scw
111 1.1 briggs return (old);
112 1.1 briggs }
113 1.1 briggs
114 1.7 perry static inline int __attribute__((__unused__))
115 1.1 briggs i80321_spllower(int ipl)
116 1.1 briggs {
117 1.7 perry extern volatile int current_spl_level;
118 1.1 briggs extern int i80321_imask[];
119 1.1 briggs int old = current_spl_level;
120 1.1 briggs
121 1.1 briggs i80321_splx(i80321_imask[ipl]);
122 1.1 briggs return(old);
123 1.1 briggs }
124 1.1 briggs
125 1.2 thorpej #if !defined(EVBARM_SPL_NOINLINE)
126 1.2 thorpej
127 1.1 briggs #define splx(new) i80321_splx(new)
128 1.1 briggs #define _spllower(ipl) i80321_spllower(ipl)
129 1.1 briggs #define _splraise(ipl) i80321_splraise(ipl)
130 1.1 briggs void _setsoftintr(int);
131 1.1 briggs
132 1.2 thorpej #else
133 1.1 briggs
134 1.1 briggs int _splraise(int);
135 1.1 briggs int _spllower(int);
136 1.1 briggs void splx(int);
137 1.1 briggs void _setsoftintr(int);
138 1.1 briggs
139 1.2 thorpej #endif /* ! EVBARM_SPL_NOINLINE */
140 1.3 thorpej
141 1.3 thorpej #endif /* _LOCORE */
142 1.1 briggs
143 1.4 matt #endif /* _I80321_INTR_H_ */
144