i80321_intr.h revision 1.1 1 /* $NetBSD: i80321_intr.h,v 1.1 2002/08/17 16:42:20 briggs Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _I80321_INTR_H_
39 #define _I80321_INTR_H_
40
41 #include <arm/armreg.h>
42 #include <arm/cpufunc.h>
43
44 #include <arm/xscale/i80321reg.h>
45
46 #if !defined(EVBARM_SPL_NOINLINE)
47 static __inline void
48 i80321_set_intrmask(void)
49 {
50 extern __volatile uint32_t intr_enabled;
51
52 __asm __volatile("mcr p6, 0, %0, c0, c0, 0"
53 :
54 : "r" (intr_enabled & ICU_INT_HWMASK));
55 }
56
57 #define INT_SWMASK \
58 ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
59 (1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
60
61 static __inline void
62 i80321_splx(int new)
63 {
64 extern __volatile uint32_t intr_enabled;
65 extern __volatile int current_spl_level;
66 extern __volatile int i80321_ipending;
67 extern void i80321_do_pending(void);
68 int oldirqstate, hwpend;
69
70 current_spl_level = new;
71
72 hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
73 if (hwpend != 0) {
74 oldirqstate = disable_interrupts(I32_bit);
75 intr_enabled |= hwpend;
76 i80321_set_intrmask();
77 restore_interrupts(oldirqstate);
78 }
79
80 if ((i80321_ipending & INT_SWMASK) & ~new)
81 i80321_do_pending();
82 }
83
84 static __inline int
85 i80321_splraise(int ipl)
86 {
87 extern __volatile int current_spl_level;
88 extern int i80321_imask[];
89 int old;
90
91 old = current_spl_level;
92 current_spl_level |= i80321_imask[ipl];
93
94 return (old);
95 }
96
97 static __inline int
98 i80321_spllower(int ipl)
99 {
100 extern __volatile int current_spl_level;
101 extern int i80321_imask[];
102 int old = current_spl_level;
103
104 i80321_splx(i80321_imask[ipl]);
105 return(old);
106 }
107
108 #define splx(new) i80321_splx(new)
109 #define _spllower(ipl) i80321_spllower(ipl)
110 #define _splraise(ipl) i80321_splraise(ipl)
111 void _setsoftintr(int);
112
113 #undef INT_SWMASK
114
115 #else /* !EVBARM_SPL_NOINTR */
116
117 int _splraise(int);
118 int _spllower(int);
119 void splx(int);
120 void _setsoftintr(int);
121
122 #endif /* else !EVBARM_SPL_NOINTR */
123
124 #endif _I80321_INTR_H_
125