i80321_intr.h revision 1.10 1 /* $NetBSD: i80321_intr.h,v 1.10 2008/04/27 18:58:45 matt Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002, 2006 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe and Steve C. Woodford for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _I80321_INTR_H_
39 #ifndef _NO_INTR_H_
40 #define _I80321_INTR_H_
41
42 #define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch)
43
44 #ifndef _LOCORE
45
46 #include <arm/armreg.h>
47 #include <arm/cpufunc.h>
48 #include <arm/cpu.h>
49
50 #include <arm/xscale/i80321reg.h>
51
52 #ifdef __PROG32
53 static inline void __attribute__((__unused__))
54 i80321_set_intrmask(void)
55 {
56 extern volatile uint32_t intr_enabled;
57
58 __asm volatile("mcr p6, 0, %0, c0, c0, 0"
59 :
60 : "r" (intr_enabled & ICU_INT_HWMASK));
61 }
62
63 #define INT_HPIMASK (1u << ICU_INT_HPI)
64 extern volatile uint32_t intr_enabled;
65 extern volatile int i80321_ipending;
66 extern int i80321_imask[];
67
68 static inline void __attribute__((__unused__))
69 i80321_splx(int new)
70 {
71 int oldirqstate, hwpend;
72
73 /* Don't let the compiler re-order this code with preceding code */
74 __insn_barrier();
75
76 set_curcpl(new);
77
78 hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~i80321_imask[new];
79 if (hwpend != 0) {
80 oldirqstate = disable_interrupts(I32_bit);
81 intr_enabled |= hwpend;
82 i80321_set_intrmask();
83 #ifdef I80321_HPI_ENABLED
84 if (__predict_false(hwpend & INT_HPIMASK))
85 oldirqstate &= ~I32_bit;
86 #endif
87 restore_interrupts(oldirqstate);
88 }
89
90 #ifdef __HAVE_FAST_SOFTINTS
91 cpu_dosoftints();
92 #endif
93 }
94
95 static inline int __attribute__((__unused__))
96 i80321_splraise(int ipl)
97 {
98 int old = curcpl();
99 set_curcpl(ipl);
100
101 /* Don't let the compiler re-order this code with subsequent code */
102 __insn_barrier();
103
104 return (old);
105 }
106
107 static inline int __attribute__((__unused__))
108 i80321_spllower(int ipl)
109 {
110 int old = curcpl();
111 i80321_splx(ipl);
112 return(old);
113 }
114
115 #endif /* __PROG32 */
116
117 #if !defined(EVBARM_SPL_NOINLINE)
118
119 #define splx(new) i80321_splx(new)
120 #define _spllower(ipl) i80321_spllower(ipl)
121 #define _splraise(ipl) i80321_splraise(ipl)
122 void _setsoftintr(int);
123
124 #else
125
126 int _splraise(int);
127 int _spllower(int);
128 void splx(int);
129 void _setsoftintr(int);
130
131 #endif /* ! EVBARM_SPL_NOINLINE */
132
133 #endif /* _LOCORE */
134
135 #endif /* _NO_INTR_H_ */
136 #endif /* _I80321_INTR_H_ */
137