i80321_pci.c revision 1.13.2.3
1 /* $NetBSD: i80321_pci.c,v 1.13.2.3 2017/12/03 11:35:57 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80321 I/O Processor chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.13.2.3 2017/12/03 11:35:57 jdolecek Exp $"); 44 45 #include "opt_pci.h" 46 #include "opt_i80321.h" 47 #include "pci.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/bus.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pciconf.h> 60 #include <dev/pci/ppbreg.h> 61 62 #include <arm/locore.h> 63 64 #include <arm/xscale/i80321reg.h> 65 #include <arm/xscale/i80321var.h> 66 67 void i80321_pci_attach_hook(device_t, device_t, 68 struct pcibus_attach_args *); 69 int i80321_pci_bus_maxdevs(void *, int); 70 pcitag_t i80321_pci_make_tag(void *, int, int, int); 71 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *, 72 int *); 73 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); 74 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); 75 void i80321_pci_conf_interrupt(void *, int, int, int, int, int *); 76 77 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 78 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 79 80 void 81 i80321_pci_init(pci_chipset_tag_t pc, void *cookie) 82 { 83 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 84 struct i80321_softc *sc = cookie; 85 struct extent *ioext, *memext; 86 uint32_t busno; 87 #endif 88 89 pc->pc_conf_v = cookie; 90 pc->pc_attach_hook = i80321_pci_attach_hook; 91 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs; 92 pc->pc_make_tag = i80321_pci_make_tag; 93 pc->pc_decompose_tag = i80321_pci_decompose_tag; 94 pc->pc_conf_read = i80321_pci_conf_read; 95 pc->pc_conf_write = i80321_pci_conf_write; 96 pc->pc_conf_interrupt = i80321_pci_conf_interrupt; 97 98 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 99 /* 100 * Configure the PCI bus. 101 * 102 * XXX We need to revisit this. We only configure the Secondary 103 * bus (and its children). The bus configure code needs changes 104 * to support how the busses are arranged on this chip. We also 105 * need to only configure devices in the private device space on 106 * the Secondary bus. 107 */ 108 109 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 110 busno = PCIXSR_BUSNO(busno); 111 if (busno == 0xff) 112 busno = 0; 113 114 ioext = extent_create("pciio", 115 sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset, 116 sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1, 117 NULL, 0, EX_NOWAIT); 118 119 #ifdef I80321_USE_DIRECT_WIN 120 memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP, 121 VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1, 122 NULL, 0, EX_NOWAIT); 123 #else 124 memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo, 125 sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1, 126 NULL, 0, EX_NOWAIT); 127 #endif 128 129 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 130 pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align); 131 132 extent_destroy(ioext); 133 extent_destroy(memext); 134 #endif 135 } 136 137 void 138 i80321_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 139 { 140 } 141 142 void 143 i80321_pci_attach_hook(device_t parent, device_t self, 144 struct pcibus_attach_args *pba) 145 { 146 147 /* Nothing to do. */ 148 } 149 150 int 151 i80321_pci_bus_maxdevs(void *v, int busno) 152 { 153 154 return (32); 155 } 156 157 pcitag_t 158 i80321_pci_make_tag(void *v, int b, int d, int f) 159 { 160 161 return ((b << 16) | (d << 11) | (f << 8)); 162 } 163 164 void 165 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 166 { 167 168 if (bp != NULL) 169 *bp = (tag >> 16) & 0xff; 170 if (dp != NULL) 171 *dp = (tag >> 11) & 0x1f; 172 if (fp != NULL) 173 *fp = (tag >> 8) & 0x7; 174 } 175 176 struct pciconf_state { 177 uint32_t ps_addr_val; 178 179 int ps_b, ps_d, ps_f; 180 }; 181 182 static int 183 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset, 184 struct pciconf_state *ps) 185 { 186 uint32_t busno; 187 188 if ((unsigned int)offset >= PCI_CONF_SIZE) 189 return (1); 190 191 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 192 193 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 194 busno = PCIXSR_BUSNO(busno); 195 if (busno == 0xff) 196 busno = 0; 197 198 /* 199 * If the bus # is the same as our own, then use Type 0 cycles, 200 * else use Type 1. 201 * 202 * XXX We should filter out all non-private devices here! 203 * XXX How does private space interact with PCI-PCI bridges? 204 */ 205 if (ps->ps_b == busno) { 206 if (ps->ps_d > (31 - 16)) 207 return (1); 208 /* 209 * NOTE: PCI-X requires that that devices updated their 210 * PCIXSR on every config write with the device number 211 * specified in AD[15:11]. If we don't set this field, 212 * each device could end of thinking it is at device 0, 213 * which can cause a number of problems. Doing this 214 * unconditionally should be OK when only PCI devices 215 * are present. 216 */ 217 ps->ps_addr_val = (1U << (ps->ps_d + 16)) | 218 (ps->ps_d << 11) | (ps->ps_f << 8) | offset; 219 } else { 220 /* The tag is already in the correct format. */ 221 ps->ps_addr_val = tag | offset | 1; 222 } 223 224 return (0); 225 } 226 227 pcireg_t 228 i80321_pci_conf_read(void *v, pcitag_t tag, int offset) 229 { 230 struct i80321_softc *sc = v; 231 struct pciconf_state ps; 232 vaddr_t va; 233 uint32_t isr; 234 pcireg_t rv; 235 u_int s; 236 237 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 238 return ((pcireg_t) -1); 239 240 PCI_CONF_LOCK(s); 241 242 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 243 ps.ps_addr_val); 244 245 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 246 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) { 247 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR); 248 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR, 249 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM| 250 ATUISR_PTAT|ATUISR_PMPE)); 251 #if 0 252 printf("conf_read: %d/%d/%d bad address\n", 253 ps.ps_b, ps.ps_d, ps.ps_f); 254 #endif 255 rv = (pcireg_t) -1; 256 } 257 258 PCI_CONF_UNLOCK(s); 259 260 return (rv); 261 } 262 263 void 264 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 265 { 266 struct i80321_softc *sc = v; 267 struct pciconf_state ps; 268 u_int s; 269 270 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 271 return; 272 273 PCI_CONF_LOCK(s); 274 275 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 276 ps.ps_addr_val); 277 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val); 278 279 PCI_CONF_UNLOCK(s); 280 } 281
Indexes created Tue Oct 14 11:09:46 GMT 2025