i80321_pci.c revision 1.3
1 /* $NetBSD: i80321_pci.c,v 1.3 2003/06/30 15:27:12 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80321 I/O Processor chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/extent.h> 46 #include <sys/malloc.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 52 #include <arm/xscale/i80321reg.h> 53 #include <arm/xscale/i80321var.h> 54 55 #include <dev/pci/ppbreg.h> 56 #include <dev/pci/pciconf.h> 57 58 #include "opt_pci.h" 59 #include "pci.h" 60 61 void i80321_pci_attach_hook(struct device *, struct device *, 62 struct pcibus_attach_args *); 63 int i80321_pci_bus_maxdevs(void *, int); 64 pcitag_t i80321_pci_make_tag(void *, int, int, int); 65 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *, 66 int *); 67 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); 68 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); 69 70 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 71 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 72 73 void 74 i80321_pci_init(pci_chipset_tag_t pc, void *cookie) 75 { 76 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 77 struct i80321_softc *sc = cookie; 78 struct extent *ioext, *memext; 79 uint32_t busno; 80 #endif 81 82 pc->pc_conf_v = cookie; 83 pc->pc_attach_hook = i80321_pci_attach_hook; 84 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs; 85 pc->pc_make_tag = i80321_pci_make_tag; 86 pc->pc_decompose_tag = i80321_pci_decompose_tag; 87 pc->pc_conf_read = i80321_pci_conf_read; 88 pc->pc_conf_write = i80321_pci_conf_write; 89 90 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 91 /* 92 * Configure the PCI bus. 93 * 94 * XXX We need to revisit this. We only configure the Secondary 95 * bus (and its children). The bus configure code needs changes 96 * to support how the busses are arranged on this chip. We also 97 * need to only configure devices in the private device space on 98 * the Secondary bus. 99 */ 100 101 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 102 busno = PCIXSR_BUSNO(busno); 103 if (busno == 0xff) 104 busno = 0; 105 106 ioext = extent_create("pciio", sc->sc_ioout_xlate, 107 sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1, 108 M_DEVBUF, NULL, 0, EX_NOWAIT); 109 memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo, 110 sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1, 111 M_DEVBUF, NULL, 0, EX_NOWAIT); 112 113 aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 114 pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align); 115 116 extent_destroy(ioext); 117 extent_destroy(memext); 118 #endif 119 } 120 121 void 122 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 123 { 124 } 125 126 void 127 i80321_pci_attach_hook(struct device *parent, struct device *self, 128 struct pcibus_attach_args *pba) 129 { 130 131 /* Nothing to do. */ 132 } 133 134 int 135 i80321_pci_bus_maxdevs(void *v, int busno) 136 { 137 138 return (32); 139 } 140 141 pcitag_t 142 i80321_pci_make_tag(void *v, int b, int d, int f) 143 { 144 145 return ((b << 16) | (d << 11) | (f << 8)); 146 } 147 148 void 149 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 150 { 151 152 if (bp != NULL) 153 *bp = (tag >> 16) & 0xff; 154 if (dp != NULL) 155 *dp = (tag >> 11) & 0x1f; 156 if (fp != NULL) 157 *fp = (tag >> 8) & 0x7; 158 } 159 160 struct pciconf_state { 161 uint32_t ps_addr_val; 162 163 int ps_b, ps_d, ps_f; 164 }; 165 166 static int 167 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset, 168 struct pciconf_state *ps) 169 { 170 uint32_t busno; 171 172 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 173 174 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 175 busno = PCIXSR_BUSNO(busno); 176 if (busno == 0xff) 177 busno = 0; 178 179 /* 180 * If the bus # is the same as our own, then use Type 0 cycles, 181 * else use Type 1. 182 * 183 * XXX We should filter out all non-private devices here! 184 * XXX How does private space interact with PCI-PCI bridges? 185 */ 186 if (ps->ps_b == busno) { 187 if (ps->ps_d > (31 - 16)) 188 return (1); 189 /* 190 * NOTE: PCI-X requires that that devices updated their 191 * PCIXSR on every config write with the device number 192 * specified in AD[15:11]. If we don't set this field, 193 * each device could end of thinking it is at device 0, 194 * which can cause a number of problems. Doing this 195 * unconditionally should be OK when only PCI devices 196 * are present. 197 */ 198 ps->ps_addr_val = (1U << (ps->ps_d + 16)) | 199 (ps->ps_d << 11) | (ps->ps_f << 8) | offset; 200 } else { 201 /* The tag is already in the correct format. */ 202 ps->ps_addr_val = tag | offset | 1; 203 } 204 205 return (0); 206 } 207 208 pcireg_t 209 i80321_pci_conf_read(void *v, pcitag_t tag, int offset) 210 { 211 struct i80321_softc *sc = v; 212 struct pciconf_state ps; 213 vaddr_t va; 214 uint32_t isr; 215 pcireg_t rv; 216 u_int s; 217 218 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 219 return ((pcireg_t) -1); 220 221 PCI_CONF_LOCK(s); 222 223 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 224 ps.ps_addr_val); 225 226 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 227 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) { 228 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR); 229 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR, 230 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM| 231 ATUISR_PTAT|ATUISR_PMPE)); 232 #if 0 233 printf("conf_read: %d/%d/%d bad address\n", 234 ps.ps_b, ps.ps_d, ps.ps_f); 235 #endif 236 rv = (pcireg_t) -1; 237 } 238 239 PCI_CONF_UNLOCK(s); 240 241 return (rv); 242 } 243 244 void 245 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 246 { 247 struct i80321_softc *sc = v; 248 struct pciconf_state ps; 249 u_int s; 250 251 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 252 return; 253 254 PCI_CONF_LOCK(s); 255 256 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 257 ps.ps_addr_val); 258 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val); 259 260 PCI_CONF_UNLOCK(s); 261 } 262
Indexes created Wed Oct 15 16:09:53 GMT 2025