i80321_pci.c revision 1.5.10.1
1 /* $NetBSD: i80321_pci.c,v 1.5.10.1 2006/06/21 14:49:41 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80321 I/O Processor chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.5.10.1 2006/06/21 14:49:41 yamt Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/extent.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 55 #include <arm/xscale/i80321reg.h> 56 #include <arm/xscale/i80321var.h> 57 58 #include <dev/pci/ppbreg.h> 59 #include <dev/pci/pciconf.h> 60 61 #include "opt_pci.h" 62 #include "pci.h" 63 64 void i80321_pci_attach_hook(struct device *, struct device *, 65 struct pcibus_attach_args *); 66 int i80321_pci_bus_maxdevs(void *, int); 67 pcitag_t i80321_pci_make_tag(void *, int, int, int); 68 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *, 69 int *); 70 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); 71 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); 72 73 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 74 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 75 76 void 77 i80321_pci_init(pci_chipset_tag_t pc, void *cookie) 78 { 79 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 80 struct i80321_softc *sc = cookie; 81 struct extent *ioext, *memext; 82 uint32_t busno; 83 #endif 84 85 pc->pc_conf_v = cookie; 86 pc->pc_attach_hook = i80321_pci_attach_hook; 87 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs; 88 pc->pc_make_tag = i80321_pci_make_tag; 89 pc->pc_decompose_tag = i80321_pci_decompose_tag; 90 pc->pc_conf_read = i80321_pci_conf_read; 91 pc->pc_conf_write = i80321_pci_conf_write; 92 93 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 94 /* 95 * Configure the PCI bus. 96 * 97 * XXX We need to revisit this. We only configure the Secondary 98 * bus (and its children). The bus configure code needs changes 99 * to support how the busses are arranged on this chip. We also 100 * need to only configure devices in the private device space on 101 * the Secondary bus. 102 */ 103 104 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 105 busno = PCIXSR_BUSNO(busno); 106 if (busno == 0xff) 107 busno = 0; 108 109 ioext = extent_create("pciio", 110 sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset, 111 sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1, 112 M_DEVBUF, NULL, 0, EX_NOWAIT); 113 memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo, 114 sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1, 115 M_DEVBUF, NULL, 0, EX_NOWAIT); 116 117 aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 118 pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align); 119 120 extent_destroy(ioext); 121 extent_destroy(memext); 122 #endif 123 } 124 125 void 126 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 127 { 128 } 129 130 void 131 i80321_pci_attach_hook(struct device *parent, struct device *self, 132 struct pcibus_attach_args *pba) 133 { 134 135 /* Nothing to do. */ 136 } 137 138 int 139 i80321_pci_bus_maxdevs(void *v, int busno) 140 { 141 142 return (32); 143 } 144 145 pcitag_t 146 i80321_pci_make_tag(void *v, int b, int d, int f) 147 { 148 149 return ((b << 16) | (d << 11) | (f << 8)); 150 } 151 152 void 153 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 154 { 155 156 if (bp != NULL) 157 *bp = (tag >> 16) & 0xff; 158 if (dp != NULL) 159 *dp = (tag >> 11) & 0x1f; 160 if (fp != NULL) 161 *fp = (tag >> 8) & 0x7; 162 } 163 164 struct pciconf_state { 165 uint32_t ps_addr_val; 166 167 int ps_b, ps_d, ps_f; 168 }; 169 170 static int 171 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset, 172 struct pciconf_state *ps) 173 { 174 uint32_t busno; 175 176 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 177 178 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 179 busno = PCIXSR_BUSNO(busno); 180 if (busno == 0xff) 181 busno = 0; 182 183 /* 184 * If the bus # is the same as our own, then use Type 0 cycles, 185 * else use Type 1. 186 * 187 * XXX We should filter out all non-private devices here! 188 * XXX How does private space interact with PCI-PCI bridges? 189 */ 190 if (ps->ps_b == busno) { 191 if (ps->ps_d > (31 - 16)) 192 return (1); 193 /* 194 * NOTE: PCI-X requires that that devices updated their 195 * PCIXSR on every config write with the device number 196 * specified in AD[15:11]. If we don't set this field, 197 * each device could end of thinking it is at device 0, 198 * which can cause a number of problems. Doing this 199 * unconditionally should be OK when only PCI devices 200 * are present. 201 */ 202 ps->ps_addr_val = (1U << (ps->ps_d + 16)) | 203 (ps->ps_d << 11) | (ps->ps_f << 8) | offset; 204 } else { 205 /* The tag is already in the correct format. */ 206 ps->ps_addr_val = tag | offset | 1; 207 } 208 209 return (0); 210 } 211 212 pcireg_t 213 i80321_pci_conf_read(void *v, pcitag_t tag, int offset) 214 { 215 struct i80321_softc *sc = v; 216 struct pciconf_state ps; 217 vaddr_t va; 218 uint32_t isr; 219 pcireg_t rv; 220 u_int s; 221 222 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 223 return ((pcireg_t) -1); 224 225 PCI_CONF_LOCK(s); 226 227 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 228 ps.ps_addr_val); 229 230 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 231 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) { 232 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR); 233 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR, 234 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM| 235 ATUISR_PTAT|ATUISR_PMPE)); 236 #if 0 237 printf("conf_read: %d/%d/%d bad address\n", 238 ps.ps_b, ps.ps_d, ps.ps_f); 239 #endif 240 rv = (pcireg_t) -1; 241 } 242 243 PCI_CONF_UNLOCK(s); 244 245 return (rv); 246 } 247 248 void 249 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 250 { 251 struct i80321_softc *sc = v; 252 struct pciconf_state ps; 253 u_int s; 254 255 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 256 return; 257 258 PCI_CONF_LOCK(s); 259 260 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 261 ps.ps_addr_val); 262 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val); 263 264 PCI_CONF_UNLOCK(s); 265 } 266
Indexes created Tue Oct 14 15:09:51 GMT 2025