i80321_timer.c revision 1.1.2.3
1 1.1.2.3 nathanw /* $NetBSD: i80321_timer.c,v 1.1.2.3 2002/08/13 02:17:58 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.1.2.2 nathanw * 9 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 11 1.1.2.2 nathanw * are met: 12 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.1.2.2 nathanw * must display the following acknowledgement: 19 1.1.2.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.1.2.2 nathanw * Wasabi Systems, Inc. 21 1.1.2.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.1.2.2 nathanw * or promote products derived from this software without specific prior 23 1.1.2.2 nathanw * written permission. 24 1.1.2.2 nathanw * 25 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.1.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.1.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.1.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.1.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.1.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.1.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.1.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.1.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.1.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.1.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.1.2.2 nathanw */ 37 1.1.2.2 nathanw 38 1.1.2.2 nathanw /* 39 1.1.2.2 nathanw * Timer/clock support for the Intel i80321 I/O processor. 40 1.1.2.2 nathanw */ 41 1.1.2.2 nathanw 42 1.1.2.3 nathanw #include "opt_perfctrs.h" 43 1.1.2.3 nathanw 44 1.1.2.2 nathanw #include <sys/param.h> 45 1.1.2.2 nathanw #include <sys/systm.h> 46 1.1.2.2 nathanw #include <sys/kernel.h> 47 1.1.2.2 nathanw #include <sys/time.h> 48 1.1.2.2 nathanw 49 1.1.2.2 nathanw #include <machine/bus.h> 50 1.1.2.2 nathanw #include <arm/cpufunc.h> 51 1.1.2.2 nathanw 52 1.1.2.2 nathanw #include <arm/xscale/i80321reg.h> 53 1.1.2.2 nathanw #include <arm/xscale/i80321var.h> 54 1.1.2.2 nathanw 55 1.1.2.2 nathanw void (*i80321_hardclock_hook)(void); 56 1.1.2.2 nathanw 57 1.1.2.2 nathanw #define COUNTS_PER_SEC 200000000 /* 200MHz */ 58 1.1.2.2 nathanw #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) 59 1.1.2.2 nathanw 60 1.1.2.2 nathanw static void *clock_ih; 61 1.1.2.2 nathanw 62 1.1.2.2 nathanw static uint32_t counts_per_hz; 63 1.1.2.2 nathanw 64 1.1.2.2 nathanw int clockhandler(void *); 65 1.1.2.2 nathanw 66 1.1.2.2 nathanw static __inline uint32_t 67 1.1.2.2 nathanw tmr0_read(void) 68 1.1.2.2 nathanw { 69 1.1.2.2 nathanw uint32_t rv; 70 1.1.2.2 nathanw 71 1.1.2.2 nathanw __asm __volatile("mrc p6, 0, %0, c0, c1, 0" 72 1.1.2.2 nathanw : "=r" (rv)); 73 1.1.2.2 nathanw return (rv); 74 1.1.2.2 nathanw } 75 1.1.2.2 nathanw 76 1.1.2.2 nathanw static __inline void 77 1.1.2.2 nathanw tmr0_write(uint32_t val) 78 1.1.2.2 nathanw { 79 1.1.2.2 nathanw 80 1.1.2.2 nathanw __asm __volatile("mcr p6, 0, %0, c0, c1, 0" 81 1.1.2.2 nathanw : 82 1.1.2.2 nathanw : "r" (val)); 83 1.1.2.2 nathanw } 84 1.1.2.2 nathanw 85 1.1.2.2 nathanw static __inline uint32_t 86 1.1.2.2 nathanw tcr0_read(void) 87 1.1.2.2 nathanw { 88 1.1.2.2 nathanw uint32_t rv; 89 1.1.2.2 nathanw 90 1.1.2.2 nathanw __asm __volatile("mrc p6, 0, %0, c2, c1, 0" 91 1.1.2.2 nathanw : "=r" (rv)); 92 1.1.2.2 nathanw return (rv); 93 1.1.2.2 nathanw } 94 1.1.2.2 nathanw 95 1.1.2.2 nathanw static __inline void 96 1.1.2.2 nathanw tcr0_write(uint32_t val) 97 1.1.2.2 nathanw { 98 1.1.2.2 nathanw 99 1.1.2.2 nathanw __asm __volatile("mcr p6, 0, %0, c2, c1, 0" 100 1.1.2.2 nathanw : 101 1.1.2.2 nathanw : "r" (val)); 102 1.1.2.2 nathanw } 103 1.1.2.2 nathanw 104 1.1.2.2 nathanw static __inline void 105 1.1.2.2 nathanw trr0_write(uint32_t val) 106 1.1.2.2 nathanw { 107 1.1.2.2 nathanw 108 1.1.2.2 nathanw __asm __volatile("mcr p6, 0, %0, c4, c1, 0" 109 1.1.2.2 nathanw : 110 1.1.2.2 nathanw : "r" (val)); 111 1.1.2.2 nathanw } 112 1.1.2.2 nathanw 113 1.1.2.2 nathanw static __inline void 114 1.1.2.2 nathanw tisr_write(uint32_t val) 115 1.1.2.2 nathanw { 116 1.1.2.2 nathanw 117 1.1.2.2 nathanw __asm __volatile("mcr p6, 0, %0, c6, c1, 0" 118 1.1.2.2 nathanw : 119 1.1.2.2 nathanw : "r" (val)); 120 1.1.2.2 nathanw } 121 1.1.2.2 nathanw 122 1.1.2.2 nathanw /* 123 1.1.2.2 nathanw * i80321_calibrate_delay: 124 1.1.2.2 nathanw * 125 1.1.2.2 nathanw * Calibrate the delay loop. 126 1.1.2.2 nathanw */ 127 1.1.2.2 nathanw void 128 1.1.2.2 nathanw i80321_calibrate_delay(void) 129 1.1.2.2 nathanw { 130 1.1.2.2 nathanw 131 1.1.2.2 nathanw /* 132 1.1.2.2 nathanw * Just use hz=100 for now -- we'll adjust it, if necessary, 133 1.1.2.2 nathanw * in cpu_initclocks(). 134 1.1.2.2 nathanw */ 135 1.1.2.2 nathanw counts_per_hz = COUNTS_PER_SEC / 100; 136 1.1.2.2 nathanw 137 1.1.2.2 nathanw tmr0_write(0); /* stop timer */ 138 1.1.2.2 nathanw tisr_write(TISR_TMR0); /* clear interrupt */ 139 1.1.2.2 nathanw trr0_write(counts_per_hz); /* reload value */ 140 1.1.2.2 nathanw tcr0_write(counts_per_hz); /* current value */ 141 1.1.2.2 nathanw 142 1.1.2.2 nathanw tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 143 1.1.2.2 nathanw } 144 1.1.2.2 nathanw 145 1.1.2.2 nathanw /* 146 1.1.2.2 nathanw * cpu_initclocks: 147 1.1.2.2 nathanw * 148 1.1.2.2 nathanw * Initialize the clock and get them going. 149 1.1.2.2 nathanw */ 150 1.1.2.2 nathanw void 151 1.1.2.2 nathanw cpu_initclocks(void) 152 1.1.2.2 nathanw { 153 1.1.2.2 nathanw u_int oldirqstate; 154 1.1.2.3 nathanw #if defined(PERFCTRS) 155 1.1.2.3 nathanw void *pmu_ih; 156 1.1.2.3 nathanw extern int xscale_pmc_dispatch(void *); 157 1.1.2.3 nathanw #endif 158 1.1.2.2 nathanw 159 1.1.2.2 nathanw if (hz < 50 || COUNTS_PER_SEC % hz) { 160 1.1.2.2 nathanw printf("Cannot get %d Hz clock; using 100 Hz\n", hz); 161 1.1.2.2 nathanw hz = 100; 162 1.1.2.2 nathanw } 163 1.1.2.2 nathanw tick = 1000000 / hz; /* number of microseconds between interrupts */ 164 1.1.2.2 nathanw tickfix = 1000000 - (hz * tick); 165 1.1.2.2 nathanw if (tickfix) { 166 1.1.2.2 nathanw int ftp; 167 1.1.2.2 nathanw 168 1.1.2.2 nathanw ftp = min(ffs(tickfix), ffs(hz)); 169 1.1.2.2 nathanw tickfix >>= (ftp - 1); 170 1.1.2.2 nathanw tickfixinterval = hz >> (ftp - 1); 171 1.1.2.2 nathanw } 172 1.1.2.2 nathanw 173 1.1.2.2 nathanw /* 174 1.1.2.2 nathanw * We only have one timer available; stathz and profhz are 175 1.1.2.2 nathanw * always left as 0 (the upper-layer clock code deals with 176 1.1.2.2 nathanw * this situation). 177 1.1.2.2 nathanw */ 178 1.1.2.2 nathanw if (stathz != 0) 179 1.1.2.2 nathanw printf("Cannot get %d Hz statclock\n", stathz); 180 1.1.2.2 nathanw stathz = 0; 181 1.1.2.2 nathanw 182 1.1.2.2 nathanw if (profhz != 0) 183 1.1.2.2 nathanw printf("Cannot get %d Hz profclock\n", profhz); 184 1.1.2.2 nathanw profhz = 0; 185 1.1.2.2 nathanw 186 1.1.2.2 nathanw /* Report the clock frequency. */ 187 1.1.2.2 nathanw printf("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 188 1.1.2.2 nathanw 189 1.1.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 190 1.1.2.2 nathanw 191 1.1.2.2 nathanw /* Hook up the clock interrupt handler. */ 192 1.1.2.2 nathanw clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK, 193 1.1.2.2 nathanw clockhandler, NULL); 194 1.1.2.2 nathanw if (clock_ih == NULL) 195 1.1.2.2 nathanw panic("cpu_initclocks: unable to register timer interrupt"); 196 1.1.2.2 nathanw 197 1.1.2.3 nathanw #if defined(PERFCTRS) 198 1.1.2.3 nathanw pmu_ih = i80321_intr_establish(ICU_INT_PMU, IPL_STATCLOCK, 199 1.1.2.3 nathanw xscale_pmc_dispatch, NULL); 200 1.1.2.3 nathanw if (pmu_ih == NULL) 201 1.1.2.3 nathanw panic("cpu_initclocks: unable to register timer interrupt"); 202 1.1.2.3 nathanw #endif 203 1.1.2.3 nathanw 204 1.1.2.2 nathanw /* Set up the new clock parameters. */ 205 1.1.2.2 nathanw 206 1.1.2.2 nathanw tmr0_write(0); /* stop timer */ 207 1.1.2.2 nathanw tisr_write(TISR_TMR0); /* clear interrupt */ 208 1.1.2.2 nathanw 209 1.1.2.2 nathanw counts_per_hz = COUNTS_PER_SEC / hz; 210 1.1.2.2 nathanw 211 1.1.2.2 nathanw trr0_write(counts_per_hz); /* reload value */ 212 1.1.2.2 nathanw tcr0_write(counts_per_hz); /* current value */ 213 1.1.2.2 nathanw 214 1.1.2.2 nathanw tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 215 1.1.2.2 nathanw 216 1.1.2.2 nathanw restore_interrupts(oldirqstate); 217 1.1.2.2 nathanw } 218 1.1.2.2 nathanw 219 1.1.2.2 nathanw /* 220 1.1.2.2 nathanw * setstatclockrate: 221 1.1.2.2 nathanw * 222 1.1.2.2 nathanw * Set the rate of the statistics clock. 223 1.1.2.2 nathanw * 224 1.1.2.2 nathanw * We assume that hz is either stathz or profhz, and that neither 225 1.1.2.2 nathanw * will change after being set by cpu_initclocks(). We could 226 1.1.2.2 nathanw * recalculate the intervals here, but that would be a pain. 227 1.1.2.2 nathanw */ 228 1.1.2.2 nathanw void 229 1.1.2.2 nathanw setstatclockrate(int hz) 230 1.1.2.2 nathanw { 231 1.1.2.2 nathanw 232 1.1.2.2 nathanw /* 233 1.1.2.2 nathanw * XXX Use TMR1? 234 1.1.2.2 nathanw */ 235 1.1.2.2 nathanw } 236 1.1.2.2 nathanw 237 1.1.2.2 nathanw /* 238 1.1.2.2 nathanw * microtime: 239 1.1.2.2 nathanw * 240 1.1.2.2 nathanw * Fill in the specified timeval struct with the current time 241 1.1.2.2 nathanw * accurate to the microsecond. 242 1.1.2.2 nathanw */ 243 1.1.2.2 nathanw void 244 1.1.2.2 nathanw microtime(struct timeval *tvp) 245 1.1.2.2 nathanw { 246 1.1.2.2 nathanw static struct timeval lasttv; 247 1.1.2.2 nathanw u_int oldirqstate; 248 1.1.2.2 nathanw uint32_t counts; 249 1.1.2.2 nathanw 250 1.1.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 251 1.1.2.2 nathanw 252 1.1.2.2 nathanw counts = counts_per_hz - tcr0_read(); 253 1.1.2.2 nathanw 254 1.1.2.2 nathanw /* Fill in the timeval struct. */ 255 1.1.2.2 nathanw *tvp = time; 256 1.1.2.2 nathanw tvp->tv_usec += (counts / COUNTS_PER_USEC); 257 1.1.2.2 nathanw 258 1.1.2.2 nathanw /* Make sure microseconds doesn't overflow. */ 259 1.1.2.2 nathanw while (tvp->tv_usec >= 1000000) { 260 1.1.2.2 nathanw tvp->tv_usec -= 1000000; 261 1.1.2.2 nathanw tvp->tv_sec++; 262 1.1.2.2 nathanw } 263 1.1.2.2 nathanw 264 1.1.2.2 nathanw /* Make sure the time has advanced. */ 265 1.1.2.2 nathanw if (tvp->tv_sec == lasttv.tv_sec && 266 1.1.2.2 nathanw tvp->tv_usec <= lasttv.tv_usec) { 267 1.1.2.2 nathanw tvp->tv_usec = lasttv.tv_usec + 1; 268 1.1.2.2 nathanw if (tvp->tv_usec >= 1000000) { 269 1.1.2.2 nathanw tvp->tv_usec -= 1000000; 270 1.1.2.2 nathanw tvp->tv_sec++; 271 1.1.2.2 nathanw } 272 1.1.2.2 nathanw } 273 1.1.2.2 nathanw 274 1.1.2.2 nathanw lasttv = *tvp; 275 1.1.2.2 nathanw 276 1.1.2.2 nathanw restore_interrupts(oldirqstate); 277 1.1.2.2 nathanw } 278 1.1.2.2 nathanw 279 1.1.2.2 nathanw /* 280 1.1.2.2 nathanw * delay: 281 1.1.2.2 nathanw * 282 1.1.2.2 nathanw * Delay for at least N microseconds. 283 1.1.2.2 nathanw */ 284 1.1.2.2 nathanw void 285 1.1.2.2 nathanw delay(u_int n) 286 1.1.2.2 nathanw { 287 1.1.2.2 nathanw uint32_t cur, last, delta, usecs; 288 1.1.2.2 nathanw 289 1.1.2.2 nathanw /* 290 1.1.2.2 nathanw * This works by polling the timer and counting the 291 1.1.2.2 nathanw * number of microseconds that go by. 292 1.1.2.2 nathanw */ 293 1.1.2.2 nathanw last = tcr0_read(); 294 1.1.2.2 nathanw delta = usecs = 0; 295 1.1.2.2 nathanw 296 1.1.2.2 nathanw while (n > usecs) { 297 1.1.2.2 nathanw cur = tcr0_read(); 298 1.1.2.2 nathanw 299 1.1.2.2 nathanw /* Check to see if the timer has wrapped around. */ 300 1.1.2.2 nathanw if (last < cur) 301 1.1.2.2 nathanw delta += (last + (counts_per_hz - cur)); 302 1.1.2.2 nathanw else 303 1.1.2.2 nathanw delta += (last - cur); 304 1.1.2.2 nathanw 305 1.1.2.2 nathanw last = cur; 306 1.1.2.2 nathanw 307 1.1.2.2 nathanw if (delta >= COUNTS_PER_USEC) { 308 1.1.2.2 nathanw usecs += delta / COUNTS_PER_USEC; 309 1.1.2.2 nathanw delta %= COUNTS_PER_USEC; 310 1.1.2.2 nathanw } 311 1.1.2.2 nathanw } 312 1.1.2.2 nathanw } 313 1.1.2.2 nathanw 314 1.1.2.2 nathanw /* 315 1.1.2.2 nathanw * inittodr: 316 1.1.2.2 nathanw * 317 1.1.2.2 nathanw * Initialize time from the time-of-day register. 318 1.1.2.2 nathanw */ 319 1.1.2.2 nathanw void 320 1.1.2.2 nathanw inittodr(time_t base) 321 1.1.2.2 nathanw { 322 1.1.2.2 nathanw 323 1.1.2.2 nathanw time.tv_sec = base; 324 1.1.2.2 nathanw time.tv_usec = 0; 325 1.1.2.2 nathanw } 326 1.1.2.2 nathanw 327 1.1.2.2 nathanw /* 328 1.1.2.2 nathanw * resettodr: 329 1.1.2.2 nathanw * 330 1.1.2.2 nathanw * Reset the time-of-day register with the current time. 331 1.1.2.2 nathanw */ 332 1.1.2.2 nathanw void 333 1.1.2.2 nathanw resettodr(void) 334 1.1.2.2 nathanw { 335 1.1.2.2 nathanw } 336 1.1.2.2 nathanw 337 1.1.2.2 nathanw /* 338 1.1.2.2 nathanw * clockhandler: 339 1.1.2.2 nathanw * 340 1.1.2.2 nathanw * Handle the hardclock interrupt. 341 1.1.2.2 nathanw */ 342 1.1.2.2 nathanw int 343 1.1.2.2 nathanw clockhandler(void *arg) 344 1.1.2.2 nathanw { 345 1.1.2.2 nathanw struct clockframe *frame = arg; 346 1.1.2.2 nathanw 347 1.1.2.2 nathanw tisr_write(TISR_TMR0); 348 1.1.2.2 nathanw 349 1.1.2.2 nathanw hardclock(frame); 350 1.1.2.2 nathanw 351 1.1.2.2 nathanw if (i80321_hardclock_hook != NULL) 352 1.1.2.2 nathanw (*i80321_hardclock_hook)(); 353 1.1.2.2 nathanw 354 1.1.2.2 nathanw return (1); 355 1.1.2.2 nathanw } 356
Indexes created Thu Oct 02 14:10:14 GMT 2025