i80321var.h revision 1.14
1 /* $NetBSD: i80321var.h,v 1.14 2021/08/06 09:01:36 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_XSCALE_I80321VAR_H_ 39 #define _ARM_XSCALE_I80321VAR_H_ 40 41 #include <sys/queue.h> 42 #include <dev/pci/pcivar.h> 43 44 /* 45 * There are roughly 32 interrupt sources. 46 */ 47 #define NIRQ 32 48 49 struct intrhand { 50 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 51 int (*ih_func)(void *); /* handler */ 52 void *ih_arg; /* arg for handler */ 53 int ih_ipl; /* IPL_* */ 54 int ih_irq; /* IRQ number */ 55 }; 56 57 #define IRQNAMESIZE sizeof("iop321 irq 31") 58 59 struct intrq { 60 TAILQ_HEAD(, intrhand) iq_list; /* handler list */ 61 struct evcnt iq_ev; /* event counter */ 62 int iq_ist; /* share type */ 63 }; 64 65 struct i80321_softc { 66 device_t sc_dev; /* generic device glue */ 67 68 int sc_is_host; /* indicates if we're a host or 69 plugged into another host */ 70 71 /* 72 * This is the bus_space and handle used to access the 73 * i80321 itself. This is filled in by the board-specific 74 * front-end. 75 */ 76 bus_space_tag_t sc_st; 77 bus_space_handle_t sc_sh; 78 79 /* Handles for the various subregions. */ 80 bus_space_handle_t sc_atu_sh; 81 bus_space_handle_t sc_mcu_sh; 82 83 /* 84 * We expect the board-specific front-end to have already mapped 85 * the PCI I/O space .. it is only 64K, and I/O mappings tend to 86 * be smaller than a page size, so it's generally more efficient 87 * to map them all into virtual space in one fell swoop. 88 */ 89 vaddr_t sc_iow_vaddr; /* I/O window vaddr */ 90 91 /* 92 * Variables that define the Inbound windows. The base address of 93 * 0-2 are configured by a host via BARs. The xlate variable 94 * defines the start of the local address space that it maps to. 95 * The size variable defines the byte size. 96 * 97 * The first 3 windows are for incoming PCI memory read/write 98 * cycles from a host. The 4th window, not configured by the 99 * host (as it outside the normal BAR range) is the inbound 100 * window for PCI devices controlled by the i80321. 101 */ 102 struct { 103 uint32_t iwin_base_hi; 104 uint32_t iwin_base_lo; 105 uint32_t iwin_xlate; 106 uint32_t iwin_size; 107 } sc_iwin[4]; 108 109 /* 110 * Variables that define the Outbound windows. 111 */ 112 struct { 113 uint32_t owin_xlate_lo; 114 uint32_t owin_xlate_hi; 115 } sc_owin[2]; 116 117 /* 118 * This is the PCI address that the Outbound I/O window maps to. 119 * The offset is to keep the actual used I/O address away from 0, 120 * which can be bad if, say, an i8254x gig-e chip gets mapped there. 121 * The 0 value apparently looks like "unconfigured" to the controller 122 * and it ignores writes to that region (it doesn't cause a bus fault, 123 * it just ignores them--leading to a non-functional controller). The 124 * wm(4) driver usually uses memory-mapped regions, but does use the 125 * I/O-mapped region for reset operations in order to work around a 126 * bug in the chip. 127 * Iyonix, while using sc_ioout_xlate 0 needs an offset of 0, too, in 128 * order to function properly. These values are both set in the 129 * port-specific i80321_mainbus_attach() routine. 130 */ 131 uint32_t sc_ioout_xlate; 132 uint32_t sc_ioout_xlate_offset; 133 134 /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */ 135 struct bus_space sc_pci_iot; 136 struct bus_space sc_pci_memt; 137 struct arm32_bus_dma_tag sc_pci_dmat; 138 struct arm32_pci_chipset sc_pci_chipset; 139 140 /* DMA window info for PCI DMA. */ 141 struct arm32_dma_range sc_pci_dma_range; 142 143 /* GPIO state */ 144 uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */ 145 uint8_t sc_gpio_val; /* GPIO output pin value */ 146 147 /* DMA tag for local devices. */ 148 struct arm32_bus_dma_tag sc_local_dmat; 149 }; 150 151 /* 152 * Arguments used to attach IOP built-ins. 153 */ 154 struct iopxs_attach_args { 155 const char *ia_name; /* name of device */ 156 bus_space_tag_t ia_st; /* space tag */ 157 bus_space_handle_t ia_sh;/* handle of IOP base */ 158 bus_dma_tag_t ia_dmat; /* DMA tag */ 159 bus_addr_t ia_offset; /* offset of device from IOP base */ 160 bus_size_t ia_size; /* size of sub-device */ 161 }; 162 163 extern struct bus_space i80321_bs_tag; 164 extern struct i80321_softc *i80321_softc; 165 extern const char * const i80321_irqnames[]; 166 167 extern void (*i80321_hardclock_hook)(void); 168 169 void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t, 170 paddr_t *, psize_t *); 171 172 void i80321_calibrate_delay(void); 173 174 void i80321_icu_init(void); 175 void i80321_intr_init(void); 176 void i80321_intr_evcnt_attach(void); 177 void *i80321_intr_establish(int, int, int (*)(void *), void *); 178 void i80321_intr_disestablish(void *); 179 180 void i80321_gpio_set_direction(uint8_t, uint8_t); 181 void i80321_gpio_set_val(uint8_t, uint8_t); 182 uint8_t i80321_gpio_get_val(void); 183 184 void i80321_bs_init(bus_space_tag_t, void *); 185 void i80321_io_bs_init(bus_space_tag_t, void *); 186 void i80321_mem_bs_init(bus_space_tag_t, void *); 187 188 void i80321_local_dma_init(struct i80321_softc *sc); 189 190 void i80321_pci_init(pci_chipset_tag_t, void *); 191 192 void i80321_attach(struct i80321_softc *); 193 194 #endif /* _ARM_XSCALE_I80321VAR_H_ */ 195
Indexes created Sun Sep 28 16:09:52 GMT 2025