i80321var.h revision 1.2 1 /* $NetBSD: i80321var.h,v 1.2 2002/07/25 15:00:49 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _ARM_XSCALE_I80321VAR_H_
39 #define _ARM_XSCALE_I80321VAR_H_
40
41 #include <sys/queue.h>
42 #include <dev/pci/pcivar.h>
43
44 /*
45 * There are roughly 32 interrupt sources.
46 */
47 #define NIRQ 32
48
49 struct intrhand {
50 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
51 int (*ih_func)(void *); /* handler */
52 void *ih_arg; /* arg for handler */
53 int ih_ipl; /* IPL_* */
54 int ih_irq; /* IRQ number */
55 };
56
57 #define IRQNAMESIZE sizeof("iop321 irq 31")
58
59 struct intrq {
60 TAILQ_HEAD(, intrhand) iq_list; /* handler list */
61 struct evcnt iq_ev; /* event counter */
62 int iq_mask; /* IRQs to mask while handling */
63 int iq_levels; /* IPL_*'s this IRQ has */
64 int iq_ist; /* share type */
65 char iq_name[IRQNAMESIZE]; /* interrupt name */
66 };
67
68 struct i80321_softc {
69 struct device sc_dev; /* generic device glue */
70
71 int sc_is_host; /* indicates if we're a host or
72 plugged into another host */
73
74 /*
75 * This is the bus_space and handle used to access the
76 * i80321 itself. This is filled in by the board-specific
77 * front-end.
78 */
79 bus_space_tag_t sc_st;
80 bus_space_handle_t sc_sh;
81
82 /* Handles for the various subregions. */
83 bus_space_handle_t sc_atu_sh;
84 bus_space_handle_t sc_mcu_sh;
85
86 /*
87 * We expect the board-specific front-end to have already mapped
88 * the PCI I/O space .. it is only 64K, and I/O mappings tend to
89 * be smaller than a page size, so it's generally more efficient
90 * to map them all into virtual space in one fell swoop.
91 */
92 vaddr_t sc_iow_vaddr; /* I/O window vaddr */
93
94 /*
95 * Variables that define the Inbound windows. The base address of
96 * 0-2 are configured by a host via BARs. The xlate variable
97 * defines the start of the local address space that it maps to.
98 * The size variable defines the byte size.
99 *
100 * The first 3 windows are for incoming PCI memory read/write
101 * cycles from a host. The 4th window, not configured by the
102 * host (as it outside the normal BAR range) is the inbound
103 * window for PCI devices controlled by the i80321.
104 */
105 struct {
106 uint32_t iwin_base_hi;
107 uint32_t iwin_base_lo;
108 uint32_t iwin_xlate;
109 uint32_t iwin_size;
110 } sc_iwin[4];
111
112 /*
113 * Variables that define the Outbound windows.
114 */
115 struct {
116 uint32_t owin_xlate_lo;
117 uint32_t owin_xlate_hi;
118 } sc_owin[2];
119
120 /*
121 * This is the PCI address that the Outbound I/O
122 * window maps to.
123 */
124 uint32_t sc_ioout_xlate;
125
126 /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
127 struct bus_space sc_pci_iot;
128 struct bus_space sc_pci_memt;
129 struct arm32_bus_dma_tag sc_pci_dmat;
130 struct arm32_pci_chipset sc_pci_chipset;
131
132 /* GPIO state */
133 uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */
134 uint8_t sc_gpio_val; /* GPIO output pin value */
135
136 /* DMA tag for local devices. */
137 struct arm32_bus_dma_tag sc_local_dmat;
138 };
139
140 extern struct bus_space i80321_bs_tag;
141 extern struct i80321_softc *i80321_softc;
142
143 extern void (*i80321_hardclock_hook)(void);
144
145 void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
146 paddr_t *, psize_t *);
147
148 void i80321_calibrate_delay(void);
149
150 void i80321_icu_init(void);
151 void i80321_intr_init(void);
152 void *i80321_intr_establish(int, int, int (*)(void *), void *);
153 void i80321_intr_disestablish(void *);
154
155 void i80321_bs_init(bus_space_tag_t, void *);
156 void i80321_io_bs_init(bus_space_tag_t, void *);
157 void i80321_mem_bs_init(bus_space_tag_t, void *);
158
159 void i80321_local_dma_init(bus_dma_tag_t, void *);
160
161 void i80321_pci_dma_init(bus_dma_tag_t, void *);
162
163 void i80321_pci_init(pci_chipset_tag_t, void *);
164
165 void i80321_attach(struct i80321_softc *);
166
167 #endif /* _ARM_XSCALE_I80321VAR_H_ */
168