iopaaureg.h revision 1.2
1 /* $NetBSD: iopaaureg.h,v 1.2 2002/08/02 06:52:17 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _XSCALE_IOPAAUREG_H_ 39 #define _XSCALE_IOPAAUREG_H_ 40 41 /* 42 * The AAU can transfer a maximum of 16MB. 43 * 44 * XXX The DMA maps are > 32K if we allow the maximum number 45 * XXX of DMA segments (16MB / 4K + 1) -- fix this bus_dma 46 * XXX problem. 47 */ 48 #define AAU_MAX_XFER (16U * 1024 * 1024) 49 #if 0 50 #define AAU_MAX_SEGS ((AAU_MAX_XFER / PAGE_SIZE) + 1) 51 #else 52 #define AAU_MAX_SEGS 1024 53 #endif 54 55 /* 56 * AAU I/O descriptor for operations with various numbers of inputs. 57 * Note that all descriptors must be 8-word (32-byte) aligned. 58 */ 59 struct aau_desc_4 { 60 struct aau_desc_4 *d_next; /* pointer to next (va) */ 61 uint32_t d_pa; /* our physical address */ 62 63 /* Hardware portion -- must be 32-byte aligned. */ 64 uint32_t d_nda; /* next descriptor address */ 65 uint32_t d_sar[4]; /* source address */ 66 uint32_t d_dar; /* destination address */ 67 uint32_t d_bc; /* byte count */ 68 uint32_t d_dc; /* descriptor control */ 69 } __attribute__((__packed__)); 70 71 #define SYNC_DESC_4_OFFSET offsetof(struct aau_desc_4, d_nda) 72 #define SYNC_DESC_4_SIZE (sizeof(struct aau_desc_4) - SYNC_DESC_4_OFFSET) 73 #define SYNC_DESC_4(d) \ 74 cpu_dcache_wbinv_range(((vaddr_t)(d)) + SYNC_DESC_4_OFFSET, \ 75 SYNC_DESC_4_SIZE) 76 77 /* Descriptor control */ 78 #define AAU_DC_IE (1U << 0) /* interrupt enable */ 79 #define AAU_DC_B1_CC(x) ((x) << 1) /* block command/control */ 80 #define AAU_DC_B2_CC(x) ((x) << 4) 81 #define AAU_DC_B3_CC(x) ((x) << 7) 82 #define AAU_DC_B4_CC(x) ((x) << 10) 83 #define AAU_DC_B5_CC(x) ((x) << 13) 84 #define AAU_DC_B6_CC(x) ((x) << 16) 85 #define AAU_DC_B7_CC(x) ((x) << 19) 86 #define AAU_DC_B8_CC(x) ((x) << 22) 87 #define AAU_DC_SBCI_5_8 (1U << 25) /* SAR5-SAR8 valid */ 88 #define AAU_DC_SBCI_5_16 (2U << 25) /* SAR5-SAR16 valid */ 89 #define AAU_DC_SBCI_5_32 (3U << 25) /* SAR5-SAR32 valid */ 90 #define AAU_DC_TC (1U << 28) /* transfer complete */ 91 #define AAU_DC_PERR (1U << 29) /* parity check error */ 92 #define AAU_DC_PENB (1U << 30) /* parity check enable */ 93 #define AAU_DC_DWE (1U << 31) /* destination write enable */ 94 95 #define AAU_DC_CC_NULL 0 /* null command */ 96 #define AAU_DC_CC_XOR 1U /* XOR command */ 97 #define AAU_DC_CC_FILL 2U /* fill command */ 98 #define AAU_DC_CC_DIRECT_FILL 7U /* direct fill (copy) */ 99 100 /* Hardware registers */ 101 #define AAU_ACR 0x00 /* accelerator control */ 102 #define AAU_ASR 0x04 /* accelerator status */ 103 #define AAU_ADAR 0x08 /* descriptor address */ 104 #define AAU_ANDAR 0x0c /* next descriptor address */ 105 #define AAU_DAR 0x20 /* destination address */ 106 #define AAU_ABCR 0x24 /* byte count */ 107 #define AAU_ADCR 0x28 /* descriptor control */ 108 /* i80321 only */ 109 #define AAU_EDCR0 0x3c /* extended descriptor control 0 */ 110 #define AAU_EDCR1 0x60 /* extended descriptor control 1 */ 111 #define AAU_EDCR2 0x84 /* extended descriptor control 2 */ 112 113 #define AAU_ACR_AAE (1U << 0) /* accelerator enable */ 114 #define AAU_ACR_CR (1U << 1) /* chain resume */ 115 #define AAU_ACR_512 (1U << 2) /* 512-byte buffer enable */ 116 117 #define AAU_ASR_MA (1U << 5) /* master abort */ 118 #define AAU_ASR_ECIF (1U << 8) /* end of chain interrupt */ 119 #define AAU_ASR_ETIF (1U << 9) /* end of transfer interrupt */ 120 #define AAU_ASR_AAF (1U << 10) /* acellerator active */ 121 122 #define AAU_ABCR_MASK 0x00ffffff /* 24-bit count */ 123 124 #endif /* _XSCALE_IOPAAUREG_H_ */ 125
Indexes created Mon Sep 29 18:09:42 GMT 2025