ixp425_if_npe.c revision 1.14 1 1.14 msaitoh /* $NetBSD: ixp425_if_npe.c,v 1.14 2009/03/11 13:20:30 msaitoh Exp $ */
2 1.1 scw
3 1.1 scw /*-
4 1.1 scw * Copyright (c) 2006 Sam Leffler. All rights reserved.
5 1.1 scw *
6 1.1 scw * Redistribution and use in source and binary forms, with or without
7 1.1 scw * modification, are permitted provided that the following conditions
8 1.1 scw * are met:
9 1.1 scw * 1. Redistributions of source code must retain the above copyright
10 1.1 scw * notice, this list of conditions and the following disclaimer.
11 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 scw * notice, this list of conditions and the following disclaimer in the
13 1.1 scw * documentation and/or other materials provided with the distribution.
14 1.1 scw *
15 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 scw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 1.1 scw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 1.1 scw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 1.1 scw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 1.1 scw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 1.1 scw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 1.1 scw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 1.1 scw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 1.1 scw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 1.1 scw */
26 1.1 scw
27 1.1 scw #include <sys/cdefs.h>
28 1.1 scw #if 0
29 1.1 scw __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $");
30 1.1 scw #endif
31 1.14 msaitoh __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.14 2009/03/11 13:20:30 msaitoh Exp $");
32 1.1 scw
33 1.1 scw /*
34 1.1 scw * Intel XScale NPE Ethernet driver.
35 1.1 scw *
36 1.1 scw * This driver handles the two ports present on the IXP425.
37 1.1 scw * Packet processing is done by the Network Processing Engines
38 1.1 scw * (NPE's) that work together with a MAC and PHY. The MAC
39 1.1 scw * is also mapped to the XScale cpu; the PHY is accessed via
40 1.1 scw * the MAC. NPE-XScale communication happens through h/w
41 1.1 scw * queues managed by the Q Manager block.
42 1.1 scw *
43 1.1 scw * The code here replaces the ethAcc, ethMii, and ethDB classes
44 1.1 scw * in the Intel Access Library (IAL) and the OS-specific driver.
45 1.1 scw *
46 1.1 scw * XXX add vlan support
47 1.1 scw * XXX NPE-C port doesn't work yet
48 1.1 scw */
49 1.1 scw
50 1.1 scw #include "bpfilter.h"
51 1.1 scw
52 1.1 scw #include <sys/param.h>
53 1.1 scw #include <sys/systm.h>
54 1.1 scw #include <sys/kernel.h>
55 1.1 scw #include <sys/device.h>
56 1.1 scw #include <sys/callout.h>
57 1.1 scw #include <sys/mbuf.h>
58 1.1 scw #include <sys/malloc.h>
59 1.1 scw #include <sys/socket.h>
60 1.1 scw #include <sys/endian.h>
61 1.1 scw #include <sys/ioctl.h>
62 1.11 msaitoh #include <sys/syslog.h>
63 1.1 scw
64 1.1 scw #include <machine/bus.h>
65 1.1 scw
66 1.1 scw #include <net/if.h>
67 1.1 scw #include <net/if_dl.h>
68 1.1 scw #include <net/if_media.h>
69 1.1 scw #include <net/if_ether.h>
70 1.1 scw
71 1.1 scw #if NBPFILTER > 0
72 1.1 scw #include <net/bpf.h>
73 1.1 scw #endif
74 1.1 scw
75 1.1 scw #include <arm/xscale/ixp425reg.h>
76 1.1 scw #include <arm/xscale/ixp425var.h>
77 1.1 scw #include <arm/xscale/ixp425_qmgr.h>
78 1.1 scw #include <arm/xscale/ixp425_npevar.h>
79 1.1 scw #include <arm/xscale/ixp425_if_npereg.h>
80 1.1 scw
81 1.1 scw #include <dev/mii/miivar.h>
82 1.1 scw
83 1.1 scw #include "locators.h"
84 1.1 scw
85 1.1 scw struct npebuf {
86 1.1 scw struct npebuf *ix_next; /* chain to next buffer */
87 1.1 scw void *ix_m; /* backpointer to mbuf */
88 1.1 scw bus_dmamap_t ix_map; /* bus dma map for associated data */
89 1.1 scw struct npehwbuf *ix_hw; /* associated h/w block */
90 1.1 scw uint32_t ix_neaddr; /* phys address of ix_hw */
91 1.1 scw };
92 1.1 scw
93 1.1 scw struct npedma {
94 1.1 scw const char* name;
95 1.1 scw int nbuf; /* # npebuf's allocated */
96 1.1 scw bus_dmamap_t m_map;
97 1.1 scw struct npehwbuf *hwbuf; /* NPE h/w buffers */
98 1.1 scw bus_dmamap_t buf_map;
99 1.1 scw bus_addr_t buf_phys; /* phys addr of buffers */
100 1.1 scw struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
101 1.1 scw };
102 1.1 scw
103 1.1 scw struct npe_softc {
104 1.1 scw struct device sc_dev;
105 1.1 scw struct ethercom sc_ethercom;
106 1.11 msaitoh uint8_t sc_enaddr[ETHER_ADDR_LEN];
107 1.1 scw struct mii_data sc_mii;
108 1.1 scw bus_space_tag_t sc_iot;
109 1.1 scw bus_dma_tag_t sc_dt;
110 1.1 scw bus_space_handle_t sc_ioh; /* MAC register window */
111 1.1 scw bus_space_handle_t sc_miih; /* MII register window */
112 1.1 scw struct ixpnpe_softc *sc_npe; /* NPE support */
113 1.1 scw int sc_unit;
114 1.1 scw int sc_phy;
115 1.1 scw struct callout sc_tick_ch; /* Tick callout */
116 1.1 scw struct npedma txdma;
117 1.1 scw struct npebuf *tx_free; /* list of free tx buffers */
118 1.1 scw struct npedma rxdma;
119 1.1 scw int rx_qid; /* rx qid */
120 1.1 scw int rx_freeqid; /* rx free buffers qid */
121 1.1 scw int tx_qid; /* tx qid */
122 1.1 scw int tx_doneqid; /* tx completed qid */
123 1.1 scw struct npestats *sc_stats;
124 1.1 scw bus_dmamap_t sc_stats_map;
125 1.1 scw bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
126 1.13 msaitoh int sc_if_flags; /* keep last if_flags */
127 1.1 scw };
128 1.1 scw
129 1.1 scw /*
130 1.1 scw * Per-unit static configuration for IXP425. The tx and
131 1.1 scw * rx free Q id's are fixed by the NPE microcode. The
132 1.1 scw * rx Q id's are programmed to be separate to simplify
133 1.1 scw * multi-port processing. It may be better to handle
134 1.1 scw * all traffic through one Q (as done by the Intel drivers).
135 1.1 scw *
136 1.1 scw * Note that the PHY's are accessible only from MAC A
137 1.1 scw * on the IXP425. This and other platform-specific
138 1.1 scw * assumptions probably need to be handled through hints.
139 1.1 scw */
140 1.1 scw static const struct {
141 1.1 scw const char *desc; /* device description */
142 1.1 scw int npeid; /* NPE assignment */
143 1.1 scw uint32_t imageid; /* NPE firmware image id */
144 1.1 scw uint32_t regbase;
145 1.1 scw int regsize;
146 1.1 scw uint32_t miibase;
147 1.1 scw int miisize;
148 1.1 scw uint8_t rx_qid;
149 1.1 scw uint8_t rx_freeqid;
150 1.1 scw uint8_t tx_qid;
151 1.1 scw uint8_t tx_doneqid;
152 1.1 scw } npeconfig[NPE_PORTS_MAX] = {
153 1.1 scw { .desc = "IXP NPE-B",
154 1.1 scw .npeid = NPE_B,
155 1.1 scw .imageid = IXP425_NPE_B_IMAGEID,
156 1.1 scw .regbase = IXP425_MAC_A_HWBASE,
157 1.1 scw .regsize = IXP425_MAC_A_SIZE,
158 1.1 scw .miibase = IXP425_MAC_A_HWBASE,
159 1.1 scw .miisize = IXP425_MAC_A_SIZE,
160 1.1 scw .rx_qid = 4,
161 1.1 scw .rx_freeqid = 27,
162 1.1 scw .tx_qid = 24,
163 1.1 scw .tx_doneqid = 31
164 1.1 scw },
165 1.1 scw { .desc = "IXP NPE-C",
166 1.1 scw .npeid = NPE_C,
167 1.1 scw .imageid = IXP425_NPE_C_IMAGEID,
168 1.1 scw .regbase = IXP425_MAC_B_HWBASE,
169 1.1 scw .regsize = IXP425_MAC_B_SIZE,
170 1.1 scw .miibase = IXP425_MAC_A_HWBASE,
171 1.1 scw .miisize = IXP425_MAC_A_SIZE,
172 1.1 scw .rx_qid = 12,
173 1.1 scw .rx_freeqid = 28,
174 1.1 scw .tx_qid = 25,
175 1.1 scw .tx_doneqid = 31
176 1.1 scw },
177 1.1 scw };
178 1.1 scw static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
179 1.1 scw
180 1.1 scw static __inline uint32_t
181 1.1 scw RD4(struct npe_softc *sc, bus_size_t off)
182 1.1 scw {
183 1.1 scw return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
184 1.1 scw }
185 1.1 scw
186 1.1 scw static __inline void
187 1.1 scw WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
188 1.1 scw {
189 1.1 scw bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
190 1.1 scw }
191 1.1 scw
192 1.1 scw static int npe_activate(struct npe_softc *);
193 1.1 scw #if 0
194 1.1 scw static void npe_deactivate(struct npe_softc *);
195 1.1 scw #endif
196 1.1 scw static int npe_ifmedia_change(struct ifnet *ifp);
197 1.1 scw static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr);
198 1.6 matt static void npe_setmac(struct npe_softc *sc, const u_char *eaddr);
199 1.11 msaitoh static void npe_getmac(struct npe_softc *sc);
200 1.1 scw static void npe_txdone(int qid, void *arg);
201 1.1 scw static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
202 1.1 scw struct mbuf *);
203 1.1 scw static void npe_rxdone(int qid, void *arg);
204 1.13 msaitoh static void npeinit_macreg(struct npe_softc *);
205 1.1 scw static int npeinit(struct ifnet *);
206 1.13 msaitoh static void npeinit_locked(void *);
207 1.1 scw static void npestart(struct ifnet *);
208 1.1 scw static void npestop(struct ifnet *, int);
209 1.1 scw static void npewatchdog(struct ifnet *);
210 1.3 christos static int npeioctl(struct ifnet * ifp, u_long, void *);
211 1.1 scw
212 1.1 scw static int npe_setrxqosentry(struct npe_softc *, int classix,
213 1.1 scw int trafclass, int qid);
214 1.1 scw static int npe_updatestats(struct npe_softc *);
215 1.1 scw #if 0
216 1.1 scw static int npe_getstats(struct npe_softc *);
217 1.1 scw static uint32_t npe_getimageid(struct npe_softc *);
218 1.1 scw static int npe_setloopback(struct npe_softc *, int ena);
219 1.1 scw #endif
220 1.1 scw
221 1.1 scw static int npe_miibus_readreg(struct device *, int, int);
222 1.1 scw static void npe_miibus_writereg(struct device *, int, int, int);
223 1.1 scw static void npe_miibus_statchg(struct device *);
224 1.1 scw
225 1.1 scw static int npe_debug;
226 1.1 scw #define DPRINTF(sc, fmt, ...) do { \
227 1.1 scw if (npe_debug) printf(fmt, __VA_ARGS__); \
228 1.1 scw } while (0)
229 1.1 scw #define DPRINTFn(n, sc, fmt, ...) do { \
230 1.1 scw if (npe_debug >= n) printf(fmt, __VA_ARGS__); \
231 1.1 scw } while (0)
232 1.1 scw
233 1.1 scw #define NPE_TXBUF 128
234 1.1 scw #define NPE_RXBUF 64
235 1.1 scw
236 1.1 scw #ifndef ETHER_ALIGN
237 1.1 scw #define ETHER_ALIGN 2 /* XXX: Ditch this */
238 1.1 scw #endif
239 1.1 scw
240 1.11 msaitoh #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \
241 1.11 msaitoh + ((uint64_t)addr[1] << 32) \
242 1.11 msaitoh + ((uint64_t)addr[2] << 24) \
243 1.11 msaitoh + ((uint64_t)addr[3] << 16) \
244 1.11 msaitoh + ((uint64_t)addr[4] << 8) \
245 1.11 msaitoh + (uint64_t)addr[5])
246 1.11 msaitoh
247 1.1 scw /* NB: all tx done processing goes through one queue */
248 1.1 scw static int tx_doneqid = -1;
249 1.1 scw
250 1.11 msaitoh void (*npe_getmac_md)(int, uint8_t *);
251 1.11 msaitoh
252 1.1 scw static int npe_match(struct device *, struct cfdata *, void *);
253 1.1 scw static void npe_attach(struct device *, struct device *, void *);
254 1.1 scw
255 1.1 scw CFATTACH_DECL(npe, sizeof(struct npe_softc),
256 1.1 scw npe_match, npe_attach, NULL, NULL);
257 1.1 scw
258 1.1 scw static int
259 1.1 scw npe_match(struct device *parent, struct cfdata *cf, void *arg)
260 1.1 scw {
261 1.1 scw struct ixpnpe_attach_args *na = arg;
262 1.1 scw
263 1.1 scw return (na->na_unit == NPE_B || na->na_unit == NPE_C);
264 1.1 scw }
265 1.1 scw
266 1.1 scw static void
267 1.1 scw npe_attach(struct device *parent, struct device *self, void *arg)
268 1.1 scw {
269 1.1 scw struct npe_softc *sc = (void *)self;
270 1.1 scw struct ixpnpe_attach_args *na = arg;
271 1.1 scw struct ifnet *ifp;
272 1.1 scw
273 1.1 scw aprint_naive("\n");
274 1.1 scw aprint_normal(": Ethernet co-processor\n");
275 1.1 scw
276 1.1 scw sc->sc_iot = na->na_iot;
277 1.1 scw sc->sc_dt = na->na_dt;
278 1.1 scw sc->sc_npe = na->na_npe;
279 1.1 scw sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1;
280 1.1 scw sc->sc_phy = na->na_phy;
281 1.1 scw
282 1.1 scw memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom));
283 1.1 scw memset(&sc->sc_mii, 0, sizeof(sc->sc_mii));
284 1.1 scw
285 1.4 ad callout_init(&sc->sc_tick_ch, 0);
286 1.1 scw
287 1.1 scw if (npe_activate(sc)) {
288 1.1 scw aprint_error("%s: Failed to activate NPE (missing "
289 1.1 scw "microcode?)\n", sc->sc_dev.dv_xname);
290 1.1 scw return;
291 1.1 scw }
292 1.1 scw
293 1.14 msaitoh npe_getmac(sc);
294 1.13 msaitoh npeinit_macreg(sc);
295 1.1 scw
296 1.1 scw aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
297 1.11 msaitoh ether_sprintf(sc->sc_enaddr));
298 1.1 scw
299 1.1 scw ifp = &sc->sc_ethercom.ec_if;
300 1.1 scw ifmedia_init(&sc->sc_mii.mii_media, 0, npe_ifmedia_change,
301 1.1 scw npe_ifmedia_status);
302 1.1 scw
303 1.1 scw if (sc->sc_phy != IXPNPECF_PHY_DEFAULT) {
304 1.1 scw sc->sc_mii.mii_ifp = ifp;
305 1.1 scw sc->sc_mii.mii_readreg = npe_miibus_readreg;
306 1.1 scw sc->sc_mii.mii_writereg = npe_miibus_writereg;
307 1.1 scw sc->sc_mii.mii_statchg = npe_miibus_statchg;
308 1.7 dyoung sc->sc_ethercom.ec_mii = &sc->sc_mii;
309 1.1 scw
310 1.1 scw mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
311 1.1 scw (sc->sc_phy > IXPNPECF_PHY_DEFAULT) ?
312 1.1 scw sc->sc_phy : MII_PHY_ANY,
313 1.1 scw MII_OFFSET_ANY, MIIF_NOISOLATE);
314 1.1 scw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
315 1.1 scw } else {
316 1.1 scw /* Assume direct connection to a 100mbit switch */
317 1.1 scw ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX, 0,0);
318 1.1 scw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX);
319 1.1 scw }
320 1.1 scw
321 1.1 scw ifp->if_softc = sc;
322 1.1 scw strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
323 1.1 scw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
324 1.1 scw ifp->if_start = npestart;
325 1.1 scw ifp->if_ioctl = npeioctl;
326 1.1 scw ifp->if_watchdog = npewatchdog;
327 1.1 scw ifp->if_init = npeinit;
328 1.1 scw ifp->if_stop = npestop;
329 1.1 scw IFQ_SET_READY(&ifp->if_snd);
330 1.1 scw
331 1.10 msaitoh /* VLAN capable */
332 1.10 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
333 1.10 msaitoh
334 1.1 scw if_attach(ifp);
335 1.11 msaitoh ether_ifattach(ifp, sc->sc_enaddr);
336 1.1 scw }
337 1.1 scw
338 1.1 scw /*
339 1.1 scw * Compute and install the multicast filter.
340 1.1 scw */
341 1.1 scw static void
342 1.1 scw npe_setmcast(struct npe_softc *sc)
343 1.1 scw {
344 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
345 1.1 scw uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
346 1.11 msaitoh uint32_t reg;
347 1.1 scw int i;
348 1.1 scw
349 1.11 msaitoh /* Always use filter. Is here a correct position? */
350 1.11 msaitoh reg = RD4(sc, NPE_MAC_RX_CNTRL1);
351 1.11 msaitoh WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN);
352 1.11 msaitoh
353 1.1 scw if (ifp->if_flags & IFF_PROMISC) {
354 1.1 scw memset(mask, 0, ETHER_ADDR_LEN);
355 1.1 scw memset(addr, 0, ETHER_ADDR_LEN);
356 1.1 scw } else if (ifp->if_flags & IFF_ALLMULTI) {
357 1.1 scw static const uint8_t allmulti[ETHER_ADDR_LEN] =
358 1.1 scw { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
359 1.1 scw all_multi:
360 1.1 scw memcpy(mask, allmulti, ETHER_ADDR_LEN);
361 1.1 scw memcpy(addr, allmulti, ETHER_ADDR_LEN);
362 1.1 scw } else {
363 1.1 scw uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
364 1.1 scw struct ether_multistep step;
365 1.1 scw struct ether_multi *enm;
366 1.1 scw
367 1.1 scw memset(clr, 0, ETHER_ADDR_LEN);
368 1.1 scw memset(set, 0xff, ETHER_ADDR_LEN);
369 1.1 scw
370 1.1 scw ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm);
371 1.1 scw while (enm != NULL) {
372 1.1 scw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
373 1.1 scw ifp->if_flags |= IFF_ALLMULTI;
374 1.1 scw goto all_multi;
375 1.1 scw }
376 1.1 scw
377 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
378 1.1 scw clr[i] |= enm->enm_addrlo[i];
379 1.1 scw set[i] &= enm->enm_addrlo[i];
380 1.1 scw }
381 1.1 scw
382 1.1 scw ETHER_NEXT_MULTI(step, enm);
383 1.1 scw }
384 1.1 scw
385 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
386 1.1 scw mask[i] = set[i] | ~clr[i];
387 1.1 scw addr[i] = set[i];
388 1.1 scw }
389 1.1 scw }
390 1.1 scw
391 1.1 scw /*
392 1.1 scw * Write the mask and address registers.
393 1.1 scw */
394 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
395 1.1 scw WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
396 1.1 scw WR4(sc, NPE_MAC_ADDR(i), addr[i]);
397 1.1 scw }
398 1.1 scw }
399 1.1 scw
400 1.1 scw static int
401 1.1 scw npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
402 1.1 scw const char *name, int nbuf, int maxseg)
403 1.1 scw {
404 1.1 scw bus_dma_segment_t seg;
405 1.1 scw int rseg, error, i;
406 1.3 christos void *hwbuf;
407 1.1 scw size_t size;
408 1.1 scw
409 1.10 msaitoh memset(dma, 0, sizeof(*dma));
410 1.1 scw
411 1.1 scw dma->name = name;
412 1.1 scw dma->nbuf = nbuf;
413 1.1 scw
414 1.1 scw size = nbuf * sizeof(struct npehwbuf);
415 1.1 scw
416 1.1 scw /* XXX COHERENT for now */
417 1.1 scw error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg,
418 1.1 scw 1, &rseg, BUS_DMA_NOWAIT);
419 1.1 scw if (error) {
420 1.1 scw printf("%s: unable to allocate memory for %s h/w buffers, "
421 1.1 scw "error %u\n", sc->sc_dev.dv_xname, dma->name, error);
422 1.1 scw }
423 1.1 scw
424 1.1 scw error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf,
425 1.1 scw BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
426 1.1 scw if (error) {
427 1.1 scw printf("%s: unable to map memory for %s h/w buffers, "
428 1.1 scw "error %u\n", sc->sc_dev.dv_xname, dma->name, error);
429 1.1 scw free_dmamem:
430 1.1 scw bus_dmamem_free(sc->sc_dt, &seg, rseg);
431 1.1 scw return error;
432 1.1 scw }
433 1.1 scw dma->hwbuf = (void *)hwbuf;
434 1.1 scw
435 1.1 scw error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0,
436 1.1 scw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map);
437 1.1 scw if (error) {
438 1.1 scw printf("%s: unable to create map for %s h/w buffers, "
439 1.1 scw "error %u\n", sc->sc_dev.dv_xname, dma->name, error);
440 1.1 scw unmap_dmamem:
441 1.1 scw dma->hwbuf = NULL;
442 1.1 scw bus_dmamem_unmap(sc->sc_dt, hwbuf, size);
443 1.1 scw goto free_dmamem;
444 1.1 scw }
445 1.1 scw
446 1.1 scw error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL,
447 1.1 scw BUS_DMA_NOWAIT);
448 1.1 scw if (error) {
449 1.1 scw printf("%s: unable to load map for %s h/w buffers, "
450 1.1 scw "error %u\n", sc->sc_dev.dv_xname, dma->name, error);
451 1.1 scw destroy_dmamap:
452 1.1 scw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
453 1.1 scw goto unmap_dmamem;
454 1.1 scw }
455 1.1 scw
456 1.1 scw /* XXX M_TEMP */
457 1.1 scw dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO);
458 1.1 scw if (dma->buf == NULL) {
459 1.1 scw printf("%s: unable to allocate memory for %s s/w buffers\n",
460 1.1 scw sc->sc_dev.dv_xname, dma->name);
461 1.1 scw bus_dmamap_unload(sc->sc_dt, dma->buf_map);
462 1.1 scw error = ENOMEM;
463 1.1 scw goto destroy_dmamap;
464 1.1 scw }
465 1.1 scw
466 1.1 scw dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr;
467 1.1 scw for (i = 0; i < dma->nbuf; i++) {
468 1.1 scw struct npebuf *npe = &dma->buf[i];
469 1.1 scw struct npehwbuf *hw = &dma->hwbuf[i];
470 1.1 scw
471 1.1 scw /* calculate offset to shared area */
472 1.1 scw npe->ix_neaddr = dma->buf_phys +
473 1.1 scw ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
474 1.1 scw KASSERT((npe->ix_neaddr & 0x1f) == 0);
475 1.10 msaitoh error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg,
476 1.1 scw MCLBYTES, 0, 0, &npe->ix_map);
477 1.1 scw if (error != 0) {
478 1.1 scw printf("%s: unable to create dmamap for %s buffer %u, "
479 1.1 scw "error %u\n", sc->sc_dev.dv_xname, dma->name, i,
480 1.1 scw error);
481 1.1 scw /* XXXSCW: Free up maps... */
482 1.1 scw return error;
483 1.1 scw }
484 1.1 scw npe->ix_hw = hw;
485 1.1 scw }
486 1.1 scw bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize,
487 1.1 scw BUS_DMASYNC_PREWRITE);
488 1.1 scw return 0;
489 1.1 scw }
490 1.1 scw
491 1.1 scw #if 0
492 1.1 scw static void
493 1.1 scw npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
494 1.1 scw {
495 1.1 scw int i;
496 1.1 scw
497 1.1 scw /* XXXSCW: Clean this up */
498 1.1 scw
499 1.1 scw if (dma->hwbuf != NULL) {
500 1.1 scw for (i = 0; i < dma->nbuf; i++) {
501 1.1 scw struct npebuf *npe = &dma->buf[i];
502 1.1 scw bus_dmamap_destroy(sc->sc_dt, npe->ix_map);
503 1.1 scw }
504 1.1 scw bus_dmamap_unload(sc->sc_dt, dma->buf_map);
505 1.3 christos bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map);
506 1.1 scw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
507 1.1 scw }
508 1.1 scw if (dma->buf != NULL)
509 1.1 scw free(dma->buf, M_TEMP);
510 1.1 scw memset(dma, 0, sizeof(*dma));
511 1.1 scw }
512 1.1 scw #endif
513 1.1 scw
514 1.1 scw static int
515 1.1 scw npe_activate(struct npe_softc *sc)
516 1.1 scw {
517 1.1 scw bus_dma_segment_t seg;
518 1.1 scw int unit = sc->sc_unit;
519 1.1 scw int error, i, rseg;
520 1.3 christos void *statbuf;
521 1.1 scw
522 1.1 scw /* load NPE firmware and start it running */
523 1.1 scw error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid);
524 1.1 scw if (error != 0)
525 1.1 scw return error;
526 1.1 scw
527 1.1 scw if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase,
528 1.1 scw npeconfig[unit].regsize, 0, &sc->sc_ioh)) {
529 1.1 scw printf("%s: Cannot map registers 0x%x:0x%x\n",
530 1.1 scw sc->sc_dev.dv_xname, npeconfig[unit].regbase,
531 1.1 scw npeconfig[unit].regsize);
532 1.1 scw return ENOMEM;
533 1.1 scw }
534 1.1 scw
535 1.1 scw if (npeconfig[unit].miibase != npeconfig[unit].regbase) {
536 1.1 scw /*
537 1.1 scw * The PHY's are only accessible from one MAC (it appears)
538 1.1 scw * so for other MAC's setup an additional mapping for
539 1.1 scw * frobbing the PHY registers.
540 1.1 scw */
541 1.1 scw if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase,
542 1.1 scw npeconfig[unit].miisize, 0, &sc->sc_miih)) {
543 1.1 scw printf("%s: Cannot map MII registers 0x%x:0x%x\n",
544 1.1 scw sc->sc_dev.dv_xname, npeconfig[unit].miibase,
545 1.1 scw npeconfig[unit].miisize);
546 1.1 scw return ENOMEM;
547 1.1 scw }
548 1.1 scw } else
549 1.1 scw sc->sc_miih = sc->sc_ioh;
550 1.1 scw error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG);
551 1.1 scw if (error != 0)
552 1.1 scw return error;
553 1.1 scw error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1);
554 1.1 scw if (error != 0)
555 1.1 scw return error;
556 1.1 scw
557 1.1 scw /* setup statistics block */
558 1.1 scw error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats),
559 1.1 scw sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);
560 1.1 scw if (error) {
561 1.1 scw printf("%s: unable to allocate memory for stats block, "
562 1.1 scw "error %u\n", sc->sc_dev.dv_xname, error);
563 1.1 scw return error;
564 1.1 scw }
565 1.1 scw
566 1.1 scw error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats),
567 1.1 scw &statbuf, BUS_DMA_NOWAIT);
568 1.1 scw if (error) {
569 1.1 scw printf("%s: unable to map memory for stats block, "
570 1.1 scw "error %u\n", sc->sc_dev.dv_xname, error);
571 1.1 scw return error;
572 1.1 scw }
573 1.1 scw sc->sc_stats = (void *)statbuf;
574 1.1 scw
575 1.1 scw error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1,
576 1.1 scw sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
577 1.1 scw &sc->sc_stats_map);
578 1.1 scw if (error) {
579 1.1 scw printf("%s: unable to create map for stats block, "
580 1.1 scw "error %u\n", sc->sc_dev.dv_xname, error);
581 1.1 scw return error;
582 1.1 scw }
583 1.1 scw
584 1.1 scw if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats,
585 1.1 scw sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) {
586 1.1 scw printf("%s: unable to load memory for stats block, error %u\n",
587 1.1 scw sc->sc_dev.dv_xname, error);
588 1.1 scw return error;
589 1.1 scw }
590 1.1 scw sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr;
591 1.1 scw
592 1.1 scw /* XXX disable half-bridge LEARNING+FILTERING feature */
593 1.1 scw
594 1.1 scw /*
595 1.1 scw * Setup h/w rx/tx queues. There are four q's:
596 1.1 scw * rx inbound q of rx'd frames
597 1.1 scw * rx_free pool of ixpbuf's for receiving frames
598 1.1 scw * tx outbound q of frames to send
599 1.1 scw * tx_done q of tx frames that have been processed
600 1.1 scw *
601 1.1 scw * The NPE handles the actual tx/rx process and the q manager
602 1.1 scw * handles the queues. The driver just writes entries to the
603 1.1 scw * q manager mailbox's and gets callbacks when there are rx'd
604 1.1 scw * frames to process or tx'd frames to reap. These callbacks
605 1.1 scw * are controlled by the q configurations; e.g. we get a
606 1.1 scw * callback when tx_done has 2 or more frames to process and
607 1.1 scw * when the rx q has at least one frame. These setings can
608 1.1 scw * changed at the time the q is configured.
609 1.1 scw */
610 1.1 scw sc->rx_qid = npeconfig[unit].rx_qid;
611 1.1 scw ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1,
612 1.1 scw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc);
613 1.1 scw sc->rx_freeqid = npeconfig[unit].rx_freeqid;
614 1.1 scw ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc);
615 1.1 scw /* tell the NPE to direct all traffic to rx_qid */
616 1.1 scw #if 0
617 1.1 scw for (i = 0; i < 8; i++)
618 1.1 scw #else
619 1.1 scw printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname);
620 1.1 scw for (i = 0; i < 4; i++)
621 1.1 scw #endif
622 1.1 scw npe_setrxqosentry(sc, i, 0, sc->rx_qid);
623 1.1 scw
624 1.1 scw sc->tx_qid = npeconfig[unit].tx_qid;
625 1.1 scw sc->tx_doneqid = npeconfig[unit].tx_doneqid;
626 1.1 scw ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc);
627 1.1 scw if (tx_doneqid == -1) {
628 1.1 scw ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2,
629 1.1 scw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
630 1.1 scw tx_doneqid = sc->tx_doneqid;
631 1.1 scw }
632 1.1 scw
633 1.1 scw KASSERT(npes[npeconfig[unit].npeid] == NULL);
634 1.1 scw npes[npeconfig[unit].npeid] = sc;
635 1.1 scw
636 1.1 scw return 0;
637 1.1 scw }
638 1.1 scw
639 1.1 scw #if 0
640 1.1 scw static void
641 1.1 scw npe_deactivate(struct npe_softc *sc);
642 1.1 scw {
643 1.1 scw int unit = sc->sc_unit;
644 1.1 scw
645 1.1 scw npes[npeconfig[unit].npeid] = NULL;
646 1.1 scw
647 1.1 scw /* XXX disable q's */
648 1.1 scw if (sc->sc_npe != NULL)
649 1.1 scw ixpnpe_stop(sc->sc_npe);
650 1.1 scw if (sc->sc_stats != NULL) {
651 1.1 scw bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
652 1.1 scw bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
653 1.1 scw sc->sc_stats_map);
654 1.1 scw bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map);
655 1.1 scw }
656 1.1 scw if (sc->sc_stats_tag != NULL)
657 1.1 scw bus_dma_tag_destroy(sc->sc_stats_tag);
658 1.1 scw npe_dma_destroy(sc, &sc->txdma);
659 1.1 scw npe_dma_destroy(sc, &sc->rxdma);
660 1.1 scw bus_generic_detach(sc->sc_dev);
661 1.1 scw if (sc->sc_mii)
662 1.1 scw device_delete_child(sc->sc_dev, sc->sc_mii);
663 1.1 scw #if 0
664 1.1 scw /* XXX sc_ioh and sc_miih */
665 1.1 scw if (sc->mem_res)
666 1.1 scw bus_release_resource(dev, SYS_RES_IOPORT,
667 1.1 scw rman_get_rid(sc->mem_res), sc->mem_res);
668 1.1 scw sc->mem_res = 0;
669 1.1 scw #endif
670 1.1 scw }
671 1.1 scw #endif
672 1.1 scw
673 1.1 scw /*
674 1.1 scw * Change media according to request.
675 1.1 scw */
676 1.1 scw static int
677 1.1 scw npe_ifmedia_change(struct ifnet *ifp)
678 1.1 scw {
679 1.1 scw struct npe_softc *sc = ifp->if_softc;
680 1.1 scw
681 1.7 dyoung if (sc->sc_phy > IXPNPECF_PHY_DEFAULT)
682 1.7 dyoung return ether_mediachange(ifp);
683 1.7 dyoung return 0;
684 1.1 scw }
685 1.1 scw
686 1.1 scw /*
687 1.1 scw * Notify the world which media we're using.
688 1.1 scw */
689 1.1 scw static void
690 1.1 scw npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
691 1.1 scw {
692 1.1 scw struct npe_softc *sc = ifp->if_softc;
693 1.1 scw
694 1.1 scw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT)
695 1.1 scw mii_pollstat(&sc->sc_mii);
696 1.1 scw
697 1.1 scw ifmr->ifm_active = sc->sc_mii.mii_media_active;
698 1.1 scw ifmr->ifm_status = sc->sc_mii.mii_media_status;
699 1.1 scw }
700 1.1 scw
701 1.1 scw static void
702 1.1 scw npe_addstats(struct npe_softc *sc)
703 1.1 scw {
704 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
705 1.1 scw struct npestats *ns = sc->sc_stats;
706 1.1 scw
707 1.1 scw ifp->if_oerrors +=
708 1.1 scw be32toh(ns->dot3StatsInternalMacTransmitErrors)
709 1.1 scw + be32toh(ns->dot3StatsCarrierSenseErrors)
710 1.1 scw + be32toh(ns->TxVLANIdFilterDiscards)
711 1.1 scw ;
712 1.1 scw ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors)
713 1.1 scw + be32toh(ns->dot3StatsInternalMacReceiveErrors)
714 1.1 scw + be32toh(ns->RxOverrunDiscards)
715 1.1 scw + be32toh(ns->RxUnderflowEntryDiscards)
716 1.1 scw ;
717 1.1 scw ifp->if_collisions +=
718 1.1 scw be32toh(ns->dot3StatsSingleCollisionFrames)
719 1.1 scw + be32toh(ns->dot3StatsMultipleCollisionFrames)
720 1.1 scw ;
721 1.1 scw }
722 1.1 scw
723 1.1 scw static void
724 1.1 scw npe_tick(void *xsc)
725 1.1 scw {
726 1.1 scw #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
727 1.1 scw struct npe_softc *sc = xsc;
728 1.1 scw uint32_t msg[2];
729 1.1 scw
730 1.1 scw /*
731 1.1 scw * NB: to avoid sleeping with the softc lock held we
732 1.1 scw * split the NPE msg processing into two parts. The
733 1.1 scw * request for statistics is sent w/o waiting for a
734 1.1 scw * reply and then on the next tick we retrieve the
735 1.1 scw * results. This works because npe_tick is the only
736 1.1 scw * code that talks via the mailbox's (except at setup).
737 1.1 scw * This likely can be handled better.
738 1.1 scw */
739 1.1 scw if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
740 1.1 scw bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0,
741 1.1 scw sizeof(struct npestats), BUS_DMASYNC_POSTREAD);
742 1.1 scw npe_addstats(sc);
743 1.1 scw }
744 1.1 scw npe_updatestats(sc);
745 1.1 scw mii_tick(&sc->sc_mii);
746 1.1 scw
747 1.1 scw /* schedule next poll */
748 1.1 scw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
749 1.1 scw #undef ACK
750 1.1 scw }
751 1.1 scw
752 1.1 scw static void
753 1.6 matt npe_setmac(struct npe_softc *sc, const u_char *eaddr)
754 1.1 scw {
755 1.11 msaitoh
756 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
757 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
758 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
759 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
760 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
761 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
762 1.1 scw }
763 1.1 scw
764 1.1 scw static void
765 1.11 msaitoh npe_getmac(struct npe_softc *sc)
766 1.1 scw {
767 1.11 msaitoh uint8_t *eaddr = sc->sc_enaddr;
768 1.11 msaitoh
769 1.11 msaitoh if (npe_getmac_md != NULL) {
770 1.11 msaitoh (*npe_getmac_md)(sc->sc_dev.dv_unit, eaddr);
771 1.11 msaitoh } else {
772 1.11 msaitoh /*
773 1.11 msaitoh * Some system's unicast address appears to be loaded from
774 1.11 msaitoh * EEPROM on reset
775 1.11 msaitoh */
776 1.11 msaitoh eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
777 1.11 msaitoh eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
778 1.11 msaitoh eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
779 1.11 msaitoh eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
780 1.11 msaitoh eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
781 1.11 msaitoh eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
782 1.11 msaitoh }
783 1.1 scw }
784 1.1 scw
785 1.1 scw struct txdone {
786 1.1 scw struct npebuf *head;
787 1.1 scw struct npebuf **tail;
788 1.1 scw int count;
789 1.1 scw };
790 1.1 scw
791 1.1 scw static __inline void
792 1.1 scw npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
793 1.1 scw {
794 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
795 1.1 scw
796 1.1 scw *td->tail = sc->tx_free;
797 1.1 scw sc->tx_free = td->head;
798 1.1 scw /*
799 1.1 scw * We're no longer busy, so clear the busy flag and call the
800 1.1 scw * start routine to xmit more packets.
801 1.1 scw */
802 1.1 scw ifp->if_opackets += td->count;
803 1.1 scw ifp->if_flags &= ~IFF_OACTIVE;
804 1.1 scw ifp->if_timer = 0;
805 1.1 scw npestart(ifp);
806 1.1 scw }
807 1.1 scw
808 1.1 scw /*
809 1.1 scw * Q manager callback on tx done queue. Reap mbufs
810 1.1 scw * and return tx buffers to the free list. Finally
811 1.1 scw * restart output. Note the microcode has only one
812 1.1 scw * txdone q wired into it so we must use the NPE ID
813 1.1 scw * returned with each npehwbuf to decide where to
814 1.1 scw * send buffers.
815 1.1 scw */
816 1.1 scw static void
817 1.1 scw npe_txdone(int qid, void *arg)
818 1.1 scw {
819 1.1 scw #define P2V(a, dma) \
820 1.1 scw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
821 1.1 scw struct npe_softc *sc;
822 1.1 scw struct npebuf *npe;
823 1.1 scw struct txdone *td, q[NPE_MAX];
824 1.1 scw uint32_t entry;
825 1.1 scw
826 1.1 scw /* XXX no NPE-A support */
827 1.1 scw q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
828 1.1 scw q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
829 1.1 scw /* XXX max # at a time? */
830 1.1 scw while (ixpqmgr_qread(qid, &entry) == 0) {
831 1.1 scw sc = npes[NPE_QM_Q_NPE(entry)];
832 1.1 scw DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n",
833 1.1 scw __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
834 1.1 scw
835 1.1 scw npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
836 1.1 scw m_freem(npe->ix_m);
837 1.1 scw npe->ix_m = NULL;
838 1.1 scw
839 1.1 scw td = &q[NPE_QM_Q_NPE(entry)];
840 1.1 scw *td->tail = npe;
841 1.1 scw td->tail = &npe->ix_next;
842 1.1 scw td->count++;
843 1.1 scw }
844 1.1 scw
845 1.1 scw if (q[NPE_B].count)
846 1.1 scw npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
847 1.1 scw if (q[NPE_C].count)
848 1.1 scw npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
849 1.1 scw #undef P2V
850 1.1 scw }
851 1.1 scw
852 1.1 scw static __inline struct mbuf *
853 1.1 scw npe_getcl(void)
854 1.1 scw {
855 1.1 scw struct mbuf *m;
856 1.1 scw
857 1.1 scw MGETHDR(m, M_DONTWAIT, MT_DATA);
858 1.1 scw if (m != NULL) {
859 1.1 scw MCLGET(m, M_DONTWAIT);
860 1.1 scw if ((m->m_flags & M_EXT) == 0) {
861 1.1 scw m_freem(m);
862 1.1 scw m = NULL;
863 1.1 scw }
864 1.1 scw }
865 1.1 scw return (m);
866 1.1 scw }
867 1.1 scw
868 1.1 scw static int
869 1.1 scw npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
870 1.1 scw {
871 1.1 scw struct npehwbuf *hw;
872 1.1 scw int error;
873 1.1 scw
874 1.1 scw if (m == NULL) {
875 1.1 scw m = npe_getcl();
876 1.1 scw if (m == NULL)
877 1.1 scw return ENOBUFS;
878 1.1 scw }
879 1.11 msaitoh KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
880 1.11 msaitoh m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT;
881 1.1 scw /* backload payload and align ip hdr */
882 1.11 msaitoh m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size
883 1.11 msaitoh - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
884 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
885 1.1 scw BUS_DMA_READ|BUS_DMA_NOWAIT);
886 1.1 scw if (error != 0) {
887 1.1 scw m_freem(m);
888 1.1 scw return error;
889 1.1 scw }
890 1.1 scw hw = npe->ix_hw;
891 1.1 scw hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr);
892 1.1 scw /* NB: NPE requires length be a multiple of 64 */
893 1.1 scw /* NB: buffer length is shifted in word */
894 1.1 scw hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16);
895 1.1 scw hw->ix_ne[0].next = 0;
896 1.1 scw npe->ix_m = m;
897 1.1 scw /* Flush the memory in the mbuf */
898 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize,
899 1.1 scw BUS_DMASYNC_PREREAD);
900 1.1 scw return 0;
901 1.1 scw }
902 1.1 scw
903 1.1 scw /*
904 1.1 scw * RX q processing for a specific NPE. Claim entries
905 1.1 scw * from the hardware queue and pass the frames up the
906 1.1 scw * stack. Pass the rx buffers to the free list.
907 1.1 scw */
908 1.1 scw static void
909 1.1 scw npe_rxdone(int qid, void *arg)
910 1.1 scw {
911 1.1 scw #define P2V(a, dma) \
912 1.1 scw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
913 1.1 scw struct npe_softc *sc = arg;
914 1.1 scw struct npedma *dma = &sc->rxdma;
915 1.1 scw uint32_t entry;
916 1.1 scw
917 1.1 scw while (ixpqmgr_qread(qid, &entry) == 0) {
918 1.1 scw struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
919 1.1 scw struct mbuf *m;
920 1.1 scw
921 1.1 scw DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
922 1.1 scw __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
923 1.1 scw /*
924 1.1 scw * Allocate a new mbuf to replenish the rx buffer.
925 1.1 scw * If doing so fails we drop the rx'd frame so we
926 1.1 scw * can reuse the previous mbuf. When we're able to
927 1.1 scw * allocate a new mbuf dispatch the mbuf w/ rx'd
928 1.1 scw * data up the stack and replace it with the newly
929 1.1 scw * allocated one.
930 1.1 scw */
931 1.1 scw m = npe_getcl();
932 1.1 scw if (m != NULL) {
933 1.1 scw struct mbuf *mrx = npe->ix_m;
934 1.1 scw struct npehwbuf *hw = npe->ix_hw;
935 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
936 1.1 scw
937 1.1 scw /* Flush mbuf memory for rx'd data */
938 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
939 1.1 scw npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
940 1.1 scw
941 1.1 scw /* XXX flush hw buffer; works now 'cuz coherent */
942 1.1 scw /* set m_len etc. per rx frame size */
943 1.1 scw mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
944 1.1 scw mrx->m_pkthdr.len = mrx->m_len;
945 1.1 scw mrx->m_pkthdr.rcvif = ifp;
946 1.11 msaitoh /* Don't add M_HASFCS. See below */
947 1.11 msaitoh
948 1.11 msaitoh #if 1
949 1.11 msaitoh if (mrx->m_pkthdr.len < sizeof(struct ether_header)) {
950 1.11 msaitoh log(LOG_INFO, "%s: too short frame (len=%d)\n",
951 1.11 msaitoh sc->sc_dev.dv_xname, mrx->m_pkthdr.len);
952 1.11 msaitoh /* Back out "newly allocated" mbuf. */
953 1.11 msaitoh m_freem(m);
954 1.11 msaitoh ifp->if_ierrors++;
955 1.11 msaitoh goto fail;
956 1.11 msaitoh }
957 1.11 msaitoh if ((ifp->if_flags & IFF_PROMISC) == 0) {
958 1.11 msaitoh struct ether_header *eh;
959 1.11 msaitoh
960 1.11 msaitoh /*
961 1.11 msaitoh * Workaround for "Non-Intel XScale Technology
962 1.11 msaitoh * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet
963 1.11 msaitoh * matches the filter (both unicast and
964 1.11 msaitoh * multicast).
965 1.11 msaitoh */
966 1.11 msaitoh eh = mtod(mrx, struct ether_header *);
967 1.11 msaitoh if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) {
968 1.11 msaitoh /* unicast */
969 1.11 msaitoh
970 1.11 msaitoh if (sc->sc_enaddr[5] != eh->ether_dhost[5]) {
971 1.11 msaitoh /* discard it */
972 1.11 msaitoh #if 0
973 1.11 msaitoh printf("discard it\n");
974 1.11 msaitoh #endif
975 1.11 msaitoh /*
976 1.11 msaitoh * Back out "newly allocated"
977 1.11 msaitoh * mbuf.
978 1.11 msaitoh */
979 1.11 msaitoh m_freem(m);
980 1.11 msaitoh goto fail;
981 1.11 msaitoh }
982 1.11 msaitoh } else if (memcmp(eh->ether_dhost,
983 1.11 msaitoh etherbroadcastaddr, 6) == 0) {
984 1.11 msaitoh /* Always accept broadcast packet*/
985 1.11 msaitoh } else {
986 1.11 msaitoh struct ethercom *ec = &sc->sc_ethercom;
987 1.11 msaitoh struct ether_multi *enm;
988 1.11 msaitoh struct ether_multistep step;
989 1.11 msaitoh int match = 0;
990 1.11 msaitoh
991 1.11 msaitoh /* multicast */
992 1.11 msaitoh
993 1.11 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
994 1.11 msaitoh while (enm != NULL) {
995 1.11 msaitoh uint64_t lowint, highint, dest;
996 1.11 msaitoh
997 1.11 msaitoh lowint = MAC2UINT64(enm->enm_addrlo);
998 1.11 msaitoh highint = MAC2UINT64(enm->enm_addrhi);
999 1.11 msaitoh dest = MAC2UINT64(eh->ether_dhost);
1000 1.11 msaitoh #if 0
1001 1.11 msaitoh printf("%llx\n", lowint);
1002 1.11 msaitoh printf("%llx\n", dest);
1003 1.11 msaitoh printf("%llx\n", highint);
1004 1.11 msaitoh #endif
1005 1.11 msaitoh if ((lowint <= dest) && (dest <= highint)) {
1006 1.11 msaitoh match = 1;
1007 1.11 msaitoh break;
1008 1.11 msaitoh }
1009 1.11 msaitoh ETHER_NEXT_MULTI(step, enm);
1010 1.11 msaitoh }
1011 1.11 msaitoh if (match == 0) {
1012 1.11 msaitoh /* discard it */
1013 1.11 msaitoh #if 0
1014 1.11 msaitoh printf("discard it(M)\n");
1015 1.11 msaitoh #endif
1016 1.11 msaitoh /*
1017 1.11 msaitoh * Back out "newly allocated"
1018 1.11 msaitoh * mbuf.
1019 1.11 msaitoh */
1020 1.11 msaitoh m_freem(m);
1021 1.11 msaitoh goto fail;
1022 1.11 msaitoh }
1023 1.11 msaitoh }
1024 1.11 msaitoh }
1025 1.11 msaitoh if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) {
1026 1.11 msaitoh log(LOG_INFO, "%s: oversized frame (len=%d)\n",
1027 1.11 msaitoh sc->sc_dev.dv_xname, mrx->m_pkthdr.len);
1028 1.11 msaitoh /* Back out "newly allocated" mbuf. */
1029 1.11 msaitoh m_freem(m);
1030 1.11 msaitoh ifp->if_ierrors++;
1031 1.11 msaitoh goto fail;
1032 1.11 msaitoh }
1033 1.11 msaitoh #endif
1034 1.11 msaitoh
1035 1.11 msaitoh /*
1036 1.11 msaitoh * Trim FCS!
1037 1.11 msaitoh * NPE always adds the FCS by this driver's setting,
1038 1.11 msaitoh * so we always trim it here and not add M_HASFCS.
1039 1.11 msaitoh */
1040 1.11 msaitoh m_adj(mrx, -ETHER_CRC_LEN);
1041 1.1 scw
1042 1.1 scw ifp->if_ipackets++;
1043 1.10 msaitoh #if NBPFILTER > 0
1044 1.10 msaitoh /*
1045 1.10 msaitoh * Tap off here if there is a bpf listener.
1046 1.10 msaitoh */
1047 1.10 msaitoh if (__predict_false(ifp->if_bpf))
1048 1.10 msaitoh bpf_mtap(ifp->if_bpf, mrx);
1049 1.10 msaitoh #endif
1050 1.1 scw ifp->if_input(ifp, mrx);
1051 1.1 scw } else {
1052 1.11 msaitoh fail:
1053 1.1 scw /* discard frame and re-use mbuf */
1054 1.1 scw m = npe->ix_m;
1055 1.1 scw }
1056 1.1 scw if (npe_rxbuf_init(sc, npe, m) == 0) {
1057 1.1 scw /* return npe buf to rx free list */
1058 1.1 scw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1059 1.1 scw } else {
1060 1.1 scw /* XXX should not happen */
1061 1.1 scw }
1062 1.1 scw }
1063 1.1 scw #undef P2V
1064 1.1 scw }
1065 1.1 scw
1066 1.1 scw static void
1067 1.1 scw npe_startxmit(struct npe_softc *sc)
1068 1.1 scw {
1069 1.1 scw struct npedma *dma = &sc->txdma;
1070 1.1 scw int i;
1071 1.1 scw
1072 1.1 scw sc->tx_free = NULL;
1073 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1074 1.1 scw struct npebuf *npe = &dma->buf[i];
1075 1.1 scw if (npe->ix_m != NULL) {
1076 1.1 scw /* NB: should not happen */
1077 1.1 scw printf("%s: %s: free mbuf at entry %u\n",
1078 1.1 scw sc->sc_dev.dv_xname, __func__, i);
1079 1.1 scw m_freem(npe->ix_m);
1080 1.1 scw }
1081 1.1 scw npe->ix_m = NULL;
1082 1.1 scw npe->ix_next = sc->tx_free;
1083 1.1 scw sc->tx_free = npe;
1084 1.1 scw }
1085 1.1 scw }
1086 1.1 scw
1087 1.1 scw static void
1088 1.1 scw npe_startrecv(struct npe_softc *sc)
1089 1.1 scw {
1090 1.1 scw struct npedma *dma = &sc->rxdma;
1091 1.1 scw struct npebuf *npe;
1092 1.1 scw int i;
1093 1.1 scw
1094 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1095 1.1 scw npe = &dma->buf[i];
1096 1.1 scw npe_rxbuf_init(sc, npe, npe->ix_m);
1097 1.1 scw /* set npe buf on rx free list */
1098 1.1 scw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1099 1.1 scw }
1100 1.1 scw }
1101 1.1 scw
1102 1.1 scw static void
1103 1.13 msaitoh npeinit_macreg(struct npe_softc *sc)
1104 1.1 scw {
1105 1.1 scw
1106 1.1 scw /*
1107 1.1 scw * Reset MAC core.
1108 1.1 scw */
1109 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1110 1.1 scw DELAY(NPE_MAC_RESET_DELAY);
1111 1.1 scw /* configure MAC to generate MDC clock */
1112 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1113 1.1 scw
1114 1.1 scw /* disable transmitter and reciver in the MAC */
1115 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1,
1116 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1117 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1,
1118 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1119 1.1 scw
1120 1.1 scw /*
1121 1.1 scw * Set the MAC core registers.
1122 1.1 scw */
1123 1.1 scw WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1124 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1125 1.1 scw WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
1126 1.1 scw /* thresholds determined by NPE firmware FS */
1127 1.1 scw WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1128 1.1 scw WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1129 1.12 msaitoh WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT);
1130 1.12 msaitoh /* tx fifo threshold (bytes) */
1131 1.1 scw WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1132 1.1 scw WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1133 1.1 scw WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1134 1.1 scw WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1135 1.12 msaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
1136 1.12 msaitoh /* assumes MII mode */
1137 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1,
1138 1.1 scw NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1139 1.1 scw | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1140 1.1 scw | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1141 1.1 scw | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1142 1.1 scw /* XXX pad strip? */
1143 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1,
1144 1.1 scw NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */
1145 1.1 scw | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */
1146 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1147 1.13 msaitoh }
1148 1.1 scw
1149 1.13 msaitoh /*
1150 1.13 msaitoh * Reset and initialize the chip
1151 1.13 msaitoh */
1152 1.13 msaitoh static void
1153 1.13 msaitoh npeinit_locked(void *xsc)
1154 1.13 msaitoh {
1155 1.13 msaitoh struct npe_softc *sc = xsc;
1156 1.13 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1157 1.13 msaitoh
1158 1.13 msaitoh /* Cancel any pending I/O. */
1159 1.13 msaitoh npestop(ifp, 0);
1160 1.13 msaitoh
1161 1.13 msaitoh /* Reset the chip to a known state. */
1162 1.13 msaitoh npeinit_macreg(sc);
1163 1.6 matt npe_setmac(sc, CLLADDR(ifp->if_sadl));
1164 1.13 msaitoh npe_ifmedia_change(ifp);
1165 1.1 scw npe_setmcast(sc);
1166 1.1 scw
1167 1.1 scw npe_startxmit(sc);
1168 1.1 scw npe_startrecv(sc);
1169 1.1 scw
1170 1.1 scw ifp->if_flags |= IFF_RUNNING;
1171 1.1 scw ifp->if_flags &= ~IFF_OACTIVE;
1172 1.1 scw ifp->if_timer = 0; /* just in case */
1173 1.1 scw
1174 1.1 scw /* enable transmitter and reciver in the MAC */
1175 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1,
1176 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1177 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1,
1178 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1179 1.1 scw
1180 1.1 scw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
1181 1.1 scw }
1182 1.1 scw
1183 1.1 scw static int
1184 1.1 scw npeinit(struct ifnet *ifp)
1185 1.1 scw {
1186 1.1 scw struct npe_softc *sc = ifp->if_softc;
1187 1.1 scw int s;
1188 1.1 scw
1189 1.1 scw s = splnet();
1190 1.1 scw npeinit_locked(sc);
1191 1.1 scw splx(s);
1192 1.1 scw
1193 1.1 scw return (0);
1194 1.1 scw }
1195 1.1 scw
1196 1.1 scw /*
1197 1.1 scw * Defragment an mbuf chain, returning at most maxfrags separate
1198 1.1 scw * mbufs+clusters. If this is not possible NULL is returned and
1199 1.1 scw * the original mbuf chain is left in it's present (potentially
1200 1.1 scw * modified) state. We use two techniques: collapsing consecutive
1201 1.1 scw * mbufs and replacing consecutive mbufs by a cluster.
1202 1.1 scw */
1203 1.1 scw static __inline struct mbuf *
1204 1.1 scw npe_defrag(struct mbuf *m0)
1205 1.1 scw {
1206 1.1 scw struct mbuf *m;
1207 1.1 scw
1208 1.1 scw MGETHDR(m, M_DONTWAIT, MT_DATA);
1209 1.1 scw if (m == NULL)
1210 1.1 scw return (NULL);
1211 1.1 scw M_COPY_PKTHDR(m, m0);
1212 1.1 scw
1213 1.1 scw if ((m->m_len = m0->m_pkthdr.len) > MHLEN) {
1214 1.1 scw MCLGET(m, M_DONTWAIT);
1215 1.1 scw if ((m->m_flags & M_EXT) == 0) {
1216 1.1 scw m_freem(m);
1217 1.1 scw return (NULL);
1218 1.1 scw }
1219 1.1 scw }
1220 1.1 scw
1221 1.3 christos m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
1222 1.1 scw m_freem(m0);
1223 1.1 scw
1224 1.1 scw return (m);
1225 1.1 scw }
1226 1.1 scw
1227 1.1 scw /*
1228 1.1 scw * Dequeue packets and place on the h/w transmit queue.
1229 1.1 scw */
1230 1.1 scw static void
1231 1.1 scw npestart(struct ifnet *ifp)
1232 1.1 scw {
1233 1.1 scw struct npe_softc *sc = ifp->if_softc;
1234 1.1 scw struct npebuf *npe;
1235 1.1 scw struct npehwbuf *hw;
1236 1.1 scw struct mbuf *m, *n;
1237 1.1 scw bus_dma_segment_t *segs;
1238 1.1 scw int nseg, len, error, i;
1239 1.1 scw uint32_t next;
1240 1.1 scw
1241 1.13 msaitoh if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1242 1.1 scw return;
1243 1.1 scw
1244 1.1 scw while (sc->tx_free != NULL) {
1245 1.1 scw IFQ_DEQUEUE(&ifp->if_snd, m);
1246 1.13 msaitoh if (m == NULL)
1247 1.13 msaitoh break;
1248 1.1 scw npe = sc->tx_free;
1249 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
1250 1.1 scw BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1251 1.1 scw if (error == EFBIG) {
1252 1.1 scw n = npe_defrag(m);
1253 1.1 scw if (n == NULL) {
1254 1.1 scw printf("%s: %s: too many fragments\n",
1255 1.1 scw sc->sc_dev.dv_xname, __func__);
1256 1.1 scw m_freem(m);
1257 1.1 scw return; /* XXX? */
1258 1.1 scw }
1259 1.1 scw m = n;
1260 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map,
1261 1.1 scw m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1262 1.1 scw }
1263 1.1 scw if (error != 0) {
1264 1.1 scw printf("%s: %s: error %u\n",
1265 1.1 scw sc->sc_dev.dv_xname, __func__, error);
1266 1.1 scw m_freem(m);
1267 1.1 scw return; /* XXX? */
1268 1.1 scw }
1269 1.1 scw sc->tx_free = npe->ix_next;
1270 1.1 scw
1271 1.1 scw #if NBPFILTER > 0
1272 1.1 scw /*
1273 1.1 scw * Tap off here if there is a bpf listener.
1274 1.1 scw */
1275 1.1 scw if (__predict_false(ifp->if_bpf))
1276 1.1 scw bpf_mtap(ifp->if_bpf, m);
1277 1.1 scw #endif
1278 1.1 scw
1279 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
1280 1.1 scw npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1281 1.1 scw
1282 1.1 scw npe->ix_m = m;
1283 1.1 scw hw = npe->ix_hw;
1284 1.1 scw len = m->m_pkthdr.len;
1285 1.1 scw nseg = npe->ix_map->dm_nsegs;
1286 1.1 scw segs = npe->ix_map->dm_segs;
1287 1.1 scw next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1288 1.1 scw for (i = 0; i < nseg; i++) {
1289 1.1 scw hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1290 1.1 scw hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1291 1.1 scw hw->ix_ne[i].next = htobe32(next);
1292 1.1 scw
1293 1.1 scw len = 0; /* zero for segments > 1 */
1294 1.1 scw next += sizeof(hw->ix_ne[0]);
1295 1.1 scw }
1296 1.1 scw hw->ix_ne[i-1].next = 0; /* zero last in chain */
1297 1.1 scw /* XXX flush descriptor instead of using uncached memory */
1298 1.1 scw
1299 1.1 scw DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1300 1.1 scw __func__, sc->tx_qid, npe->ix_neaddr,
1301 1.1 scw hw->ix_ne[0].data, hw->ix_ne[0].len);
1302 1.1 scw /* stick it on the tx q */
1303 1.1 scw /* XXX add vlan priority */
1304 1.1 scw ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1305 1.1 scw
1306 1.1 scw ifp->if_timer = 5;
1307 1.1 scw }
1308 1.1 scw if (sc->tx_free == NULL)
1309 1.1 scw ifp->if_flags |= IFF_OACTIVE;
1310 1.1 scw }
1311 1.1 scw
1312 1.1 scw static void
1313 1.1 scw npe_stopxmit(struct npe_softc *sc)
1314 1.1 scw {
1315 1.1 scw struct npedma *dma = &sc->txdma;
1316 1.1 scw int i;
1317 1.1 scw
1318 1.1 scw /* XXX qmgr */
1319 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1320 1.1 scw struct npebuf *npe = &dma->buf[i];
1321 1.1 scw
1322 1.1 scw if (npe->ix_m != NULL) {
1323 1.1 scw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1324 1.1 scw m_freem(npe->ix_m);
1325 1.1 scw npe->ix_m = NULL;
1326 1.1 scw }
1327 1.1 scw }
1328 1.1 scw }
1329 1.1 scw
1330 1.1 scw static void
1331 1.1 scw npe_stoprecv(struct npe_softc *sc)
1332 1.1 scw {
1333 1.1 scw struct npedma *dma = &sc->rxdma;
1334 1.1 scw int i;
1335 1.1 scw
1336 1.1 scw /* XXX qmgr */
1337 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1338 1.1 scw struct npebuf *npe = &dma->buf[i];
1339 1.1 scw
1340 1.1 scw if (npe->ix_m != NULL) {
1341 1.1 scw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1342 1.1 scw m_freem(npe->ix_m);
1343 1.1 scw npe->ix_m = NULL;
1344 1.1 scw }
1345 1.1 scw }
1346 1.1 scw }
1347 1.1 scw
1348 1.1 scw /*
1349 1.1 scw * Turn off interrupts, and stop the nic.
1350 1.1 scw */
1351 1.1 scw void
1352 1.1 scw npestop(struct ifnet *ifp, int disable)
1353 1.1 scw {
1354 1.1 scw struct npe_softc *sc = ifp->if_softc;
1355 1.1 scw
1356 1.1 scw /* disable transmitter and reciver in the MAC */
1357 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1,
1358 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1359 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1,
1360 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1361 1.1 scw
1362 1.1 scw callout_stop(&sc->sc_tick_ch);
1363 1.1 scw
1364 1.1 scw npe_stopxmit(sc);
1365 1.1 scw npe_stoprecv(sc);
1366 1.1 scw /* XXX go into loopback & drain q's? */
1367 1.1 scw /* XXX but beware of disabling tx above */
1368 1.1 scw
1369 1.1 scw /*
1370 1.1 scw * The MAC core rx/tx disable may leave the MAC hardware in an
1371 1.1 scw * unpredictable state. A hw reset is executed before resetting
1372 1.1 scw * all the MAC parameters to a known value.
1373 1.1 scw */
1374 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1375 1.1 scw DELAY(NPE_MAC_RESET_DELAY);
1376 1.1 scw WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1377 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1378 1.13 msaitoh
1379 1.13 msaitoh ifp->if_timer = 0;
1380 1.13 msaitoh ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1381 1.1 scw }
1382 1.1 scw
1383 1.1 scw void
1384 1.1 scw npewatchdog(struct ifnet *ifp)
1385 1.1 scw {
1386 1.1 scw struct npe_softc *sc = ifp->if_softc;
1387 1.1 scw int s;
1388 1.1 scw
1389 1.1 scw printf("%s: device timeout\n", sc->sc_dev.dv_xname);
1390 1.1 scw s = splnet();
1391 1.1 scw ifp->if_oerrors++;
1392 1.1 scw npeinit_locked(sc);
1393 1.1 scw splx(s);
1394 1.1 scw }
1395 1.1 scw
1396 1.1 scw static int
1397 1.3 christos npeioctl(struct ifnet *ifp, u_long cmd, void *data)
1398 1.1 scw {
1399 1.1 scw struct npe_softc *sc = ifp->if_softc;
1400 1.13 msaitoh struct ifreq *ifr = (struct ifreq *) data;
1401 1.1 scw int s, error = 0;
1402 1.1 scw
1403 1.1 scw s = splnet();
1404 1.1 scw
1405 1.13 msaitoh switch (cmd) {
1406 1.13 msaitoh case SIOCSIFMEDIA:
1407 1.13 msaitoh case SIOCGIFMEDIA:
1408 1.13 msaitoh #if 0 /* not yet */
1409 1.13 msaitoh /* Flow control requires full-duplex mode. */
1410 1.13 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1411 1.13 msaitoh (ifr->ifr_media & IFM_FDX) == 0)
1412 1.13 msaitoh ifr->ifr_media &= ~IFM_ETH_FMASK;
1413 1.13 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1414 1.13 msaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1415 1.13 msaitoh /* We can do both TXPAUSE and RXPAUSE. */
1416 1.13 msaitoh ifr->ifr_media |=
1417 1.13 msaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1418 1.13 msaitoh }
1419 1.13 msaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1420 1.13 msaitoh }
1421 1.13 msaitoh #endif
1422 1.13 msaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1423 1.13 msaitoh break;
1424 1.13 msaitoh case SIOCSIFFLAGS:
1425 1.13 msaitoh if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) {
1426 1.13 msaitoh /*
1427 1.13 msaitoh * If interface is marked down and it is running,
1428 1.13 msaitoh * then stop and disable it.
1429 1.13 msaitoh */
1430 1.13 msaitoh (*ifp->if_stop)(ifp, 1);
1431 1.13 msaitoh } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) {
1432 1.13 msaitoh /*
1433 1.13 msaitoh * If interface is marked up and it is stopped, then
1434 1.13 msaitoh * start it.
1435 1.13 msaitoh */
1436 1.13 msaitoh error = (*ifp->if_init)(ifp);
1437 1.13 msaitoh } else if ((ifp->if_flags & IFF_UP) != 0) {
1438 1.13 msaitoh int diff;
1439 1.13 msaitoh
1440 1.13 msaitoh /* Up (AND RUNNING). */
1441 1.13 msaitoh
1442 1.13 msaitoh diff = (ifp->if_flags ^ sc->sc_if_flags)
1443 1.13 msaitoh & (IFF_PROMISC|IFF_ALLMULTI);
1444 1.13 msaitoh if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) {
1445 1.13 msaitoh /*
1446 1.13 msaitoh * If the difference bettween last flag and
1447 1.13 msaitoh * new flag only IFF_PROMISC or IFF_ALLMULTI,
1448 1.13 msaitoh * set multicast filter only (don't reset to
1449 1.13 msaitoh * prevent link down).
1450 1.13 msaitoh */
1451 1.13 msaitoh npe_setmcast(sc);
1452 1.13 msaitoh } else {
1453 1.13 msaitoh /*
1454 1.13 msaitoh * Reset the interface to pick up changes in
1455 1.13 msaitoh * any other flags that affect the hardware
1456 1.13 msaitoh * state.
1457 1.13 msaitoh */
1458 1.13 msaitoh error = (*ifp->if_init)(ifp);
1459 1.13 msaitoh }
1460 1.13 msaitoh }
1461 1.13 msaitoh sc->sc_if_flags = ifp->if_flags;
1462 1.13 msaitoh break;
1463 1.13 msaitoh default:
1464 1.13 msaitoh error = ether_ioctl(ifp, cmd, data);
1465 1.13 msaitoh if (error == ENETRESET) {
1466 1.13 msaitoh /*
1467 1.13 msaitoh * Multicast list has changed; set the hardware filter
1468 1.13 msaitoh * accordingly.
1469 1.13 msaitoh */
1470 1.13 msaitoh npe_setmcast(sc);
1471 1.13 msaitoh error = 0;
1472 1.1 scw }
1473 1.1 scw }
1474 1.1 scw
1475 1.1 scw npestart(ifp);
1476 1.1 scw
1477 1.1 scw splx(s);
1478 1.1 scw return error;
1479 1.1 scw }
1480 1.1 scw
1481 1.1 scw /*
1482 1.1 scw * Setup a traffic class -> rx queue mapping.
1483 1.1 scw */
1484 1.1 scw static int
1485 1.1 scw npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1486 1.1 scw {
1487 1.1 scw int npeid = npeconfig[sc->sc_unit].npeid;
1488 1.1 scw uint32_t msg[2];
1489 1.1 scw
1490 1.1 scw msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix;
1491 1.1 scw msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1492 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1493 1.1 scw }
1494 1.1 scw
1495 1.1 scw /*
1496 1.1 scw * Update and reset the statistics in the NPE.
1497 1.1 scw */
1498 1.1 scw static int
1499 1.1 scw npe_updatestats(struct npe_softc *sc)
1500 1.1 scw {
1501 1.1 scw uint32_t msg[2];
1502 1.1 scw
1503 1.1 scw msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1504 1.1 scw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1505 1.1 scw return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */
1506 1.1 scw }
1507 1.1 scw
1508 1.1 scw #if 0
1509 1.1 scw /*
1510 1.1 scw * Get the current statistics block.
1511 1.1 scw */
1512 1.1 scw static int
1513 1.1 scw npe_getstats(struct npe_softc *sc)
1514 1.1 scw {
1515 1.1 scw uint32_t msg[2];
1516 1.1 scw
1517 1.1 scw msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1518 1.1 scw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1519 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1520 1.1 scw }
1521 1.1 scw
1522 1.1 scw /*
1523 1.1 scw * Query the image id of the loaded firmware.
1524 1.1 scw */
1525 1.1 scw static uint32_t
1526 1.1 scw npe_getimageid(struct npe_softc *sc)
1527 1.1 scw {
1528 1.1 scw uint32_t msg[2];
1529 1.1 scw
1530 1.1 scw msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1531 1.1 scw msg[1] = 0;
1532 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1533 1.1 scw }
1534 1.1 scw
1535 1.1 scw /*
1536 1.1 scw * Enable/disable loopback.
1537 1.1 scw */
1538 1.1 scw static int
1539 1.1 scw npe_setloopback(struct npe_softc *sc, int ena)
1540 1.1 scw {
1541 1.1 scw uint32_t msg[2];
1542 1.1 scw
1543 1.1 scw msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1544 1.1 scw msg[1] = 0;
1545 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1546 1.1 scw }
1547 1.1 scw #endif
1548 1.1 scw
1549 1.1 scw /*
1550 1.1 scw * MII bus support routines.
1551 1.1 scw *
1552 1.1 scw * NB: ixp425 has one PHY per NPE
1553 1.1 scw */
1554 1.1 scw static uint32_t
1555 1.1 scw npe_mii_mdio_read(struct npe_softc *sc, int reg)
1556 1.1 scw {
1557 1.1 scw #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1558 1.1 scw uint32_t v;
1559 1.1 scw
1560 1.1 scw /* NB: registers are known to be sequential */
1561 1.1 scw v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1562 1.1 scw v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1563 1.1 scw v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1564 1.1 scw v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1565 1.1 scw return v;
1566 1.1 scw #undef MII_RD4
1567 1.1 scw }
1568 1.1 scw
1569 1.1 scw static void
1570 1.1 scw npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1571 1.1 scw {
1572 1.1 scw #define MII_WR4(sc, reg, v) \
1573 1.1 scw bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1574 1.1 scw
1575 1.1 scw /* NB: registers are known to be sequential */
1576 1.1 scw MII_WR4(sc, reg+0, cmd & 0xff);
1577 1.1 scw MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1578 1.1 scw MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1579 1.1 scw MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1580 1.1 scw #undef MII_WR4
1581 1.1 scw }
1582 1.1 scw
1583 1.1 scw static int
1584 1.1 scw npe_mii_mdio_wait(struct npe_softc *sc)
1585 1.1 scw {
1586 1.1 scw #define MAXTRIES 100 /* XXX */
1587 1.1 scw uint32_t v;
1588 1.1 scw int i;
1589 1.1 scw
1590 1.1 scw for (i = 0; i < MAXTRIES; i++) {
1591 1.1 scw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1592 1.1 scw if ((v & NPE_MII_GO) == 0)
1593 1.1 scw return 1;
1594 1.1 scw }
1595 1.1 scw return 0; /* NB: timeout */
1596 1.1 scw #undef MAXTRIES
1597 1.1 scw }
1598 1.1 scw
1599 1.1 scw static int
1600 1.1 scw npe_miibus_readreg(struct device *self, int phy, int reg)
1601 1.1 scw {
1602 1.1 scw struct npe_softc *sc = (void *)self;
1603 1.1 scw uint32_t v;
1604 1.1 scw
1605 1.1 scw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1606 1.1 scw return 0xffff;
1607 1.1 scw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1608 1.1 scw | NPE_MII_GO;
1609 1.1 scw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1610 1.2 scw if (npe_mii_mdio_wait(sc))
1611 1.1 scw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1612 1.1 scw else
1613 1.1 scw v = 0xffff | NPE_MII_READ_FAIL;
1614 1.1 scw return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff);
1615 1.1 scw #undef MAXTRIES
1616 1.1 scw }
1617 1.1 scw
1618 1.1 scw static void
1619 1.1 scw npe_miibus_writereg(struct device *self, int phy, int reg, int data)
1620 1.1 scw {
1621 1.1 scw struct npe_softc *sc = (void *)self;
1622 1.1 scw uint32_t v;
1623 1.1 scw
1624 1.1 scw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1625 1.1 scw return;
1626 1.1 scw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1627 1.1 scw | data | NPE_MII_WRITE
1628 1.1 scw | NPE_MII_GO;
1629 1.1 scw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1630 1.1 scw /* XXX complain about timeout */
1631 1.1 scw (void) npe_mii_mdio_wait(sc);
1632 1.1 scw }
1633 1.1 scw
1634 1.1 scw static void
1635 1.1 scw npe_miibus_statchg(struct device *self)
1636 1.1 scw {
1637 1.1 scw struct npe_softc *sc = (void *)self;
1638 1.1 scw uint32_t tx1, rx1;
1639 1.1 scw
1640 1.1 scw /* sync MAC duplex state */
1641 1.1 scw tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1642 1.1 scw rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1643 1.1 scw if (sc->sc_mii.mii_media_active & IFM_FDX) {
1644 1.1 scw tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1645 1.1 scw rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1646 1.1 scw } else {
1647 1.1 scw tx1 |= NPE_TX_CNTRL1_DUPLEX;
1648 1.1 scw rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1649 1.1 scw }
1650 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1651 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1652 1.1 scw }
1653