ixp425_if_npe.c revision 1.41 1 1.41 msaitoh /* $NetBSD: ixp425_if_npe.c,v 1.41 2019/05/28 07:41:46 msaitoh Exp $ */
2 1.1 scw
3 1.1 scw /*-
4 1.1 scw * Copyright (c) 2006 Sam Leffler. All rights reserved.
5 1.1 scw *
6 1.1 scw * Redistribution and use in source and binary forms, with or without
7 1.1 scw * modification, are permitted provided that the following conditions
8 1.1 scw * are met:
9 1.1 scw * 1. Redistributions of source code must retain the above copyright
10 1.1 scw * notice, this list of conditions and the following disclaimer.
11 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 scw * notice, this list of conditions and the following disclaimer in the
13 1.1 scw * documentation and/or other materials provided with the distribution.
14 1.1 scw *
15 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 scw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 1.1 scw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 1.1 scw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 1.1 scw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 1.1 scw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 1.1 scw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 1.1 scw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 1.1 scw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 1.1 scw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 1.1 scw */
26 1.1 scw
27 1.1 scw #include <sys/cdefs.h>
28 1.1 scw #if 0
29 1.1 scw __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $");
30 1.1 scw #endif
31 1.41 msaitoh __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.41 2019/05/28 07:41:46 msaitoh Exp $");
32 1.1 scw
33 1.1 scw /*
34 1.1 scw * Intel XScale NPE Ethernet driver.
35 1.1 scw *
36 1.1 scw * This driver handles the two ports present on the IXP425.
37 1.1 scw * Packet processing is done by the Network Processing Engines
38 1.1 scw * (NPE's) that work together with a MAC and PHY. The MAC
39 1.1 scw * is also mapped to the XScale cpu; the PHY is accessed via
40 1.1 scw * the MAC. NPE-XScale communication happens through h/w
41 1.1 scw * queues managed by the Q Manager block.
42 1.1 scw *
43 1.1 scw * The code here replaces the ethAcc, ethMii, and ethDB classes
44 1.1 scw * in the Intel Access Library (IAL) and the OS-specific driver.
45 1.1 scw *
46 1.1 scw * XXX add vlan support
47 1.1 scw * XXX NPE-C port doesn't work yet
48 1.1 scw */
49 1.1 scw
50 1.1 scw #include <sys/param.h>
51 1.1 scw #include <sys/systm.h>
52 1.1 scw #include <sys/kernel.h>
53 1.1 scw #include <sys/device.h>
54 1.1 scw #include <sys/callout.h>
55 1.1 scw #include <sys/mbuf.h>
56 1.1 scw #include <sys/malloc.h>
57 1.1 scw #include <sys/socket.h>
58 1.1 scw #include <sys/endian.h>
59 1.1 scw #include <sys/ioctl.h>
60 1.11 msaitoh #include <sys/syslog.h>
61 1.20 dyoung #include <sys/bus.h>
62 1.39 msaitoh #include <sys/rndsource.h>
63 1.1 scw
64 1.1 scw #include <net/if.h>
65 1.1 scw #include <net/if_dl.h>
66 1.1 scw #include <net/if_media.h>
67 1.1 scw #include <net/if_ether.h>
68 1.1 scw #include <net/bpf.h>
69 1.1 scw
70 1.1 scw #include <arm/xscale/ixp425reg.h>
71 1.1 scw #include <arm/xscale/ixp425var.h>
72 1.1 scw #include <arm/xscale/ixp425_qmgr.h>
73 1.1 scw #include <arm/xscale/ixp425_npevar.h>
74 1.1 scw #include <arm/xscale/ixp425_if_npereg.h>
75 1.1 scw
76 1.1 scw #include <dev/mii/miivar.h>
77 1.1 scw
78 1.1 scw #include "locators.h"
79 1.1 scw
80 1.1 scw struct npebuf {
81 1.1 scw struct npebuf *ix_next; /* chain to next buffer */
82 1.1 scw void *ix_m; /* backpointer to mbuf */
83 1.1 scw bus_dmamap_t ix_map; /* bus dma map for associated data */
84 1.1 scw struct npehwbuf *ix_hw; /* associated h/w block */
85 1.1 scw uint32_t ix_neaddr; /* phys address of ix_hw */
86 1.1 scw };
87 1.1 scw
88 1.1 scw struct npedma {
89 1.1 scw const char* name;
90 1.1 scw int nbuf; /* # npebuf's allocated */
91 1.1 scw bus_dmamap_t m_map;
92 1.1 scw struct npehwbuf *hwbuf; /* NPE h/w buffers */
93 1.1 scw bus_dmamap_t buf_map;
94 1.1 scw bus_addr_t buf_phys; /* phys addr of buffers */
95 1.1 scw struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
96 1.1 scw };
97 1.1 scw
98 1.1 scw struct npe_softc {
99 1.23 matt device_t sc_dev;
100 1.1 scw struct ethercom sc_ethercom;
101 1.11 msaitoh uint8_t sc_enaddr[ETHER_ADDR_LEN];
102 1.1 scw struct mii_data sc_mii;
103 1.39 msaitoh bus_space_tag_t sc_iot;
104 1.1 scw bus_dma_tag_t sc_dt;
105 1.1 scw bus_space_handle_t sc_ioh; /* MAC register window */
106 1.1 scw bus_space_handle_t sc_miih; /* MII register window */
107 1.1 scw struct ixpnpe_softc *sc_npe; /* NPE support */
108 1.1 scw int sc_unit;
109 1.1 scw int sc_phy;
110 1.1 scw struct callout sc_tick_ch; /* Tick callout */
111 1.1 scw struct npedma txdma;
112 1.1 scw struct npebuf *tx_free; /* list of free tx buffers */
113 1.1 scw struct npedma rxdma;
114 1.1 scw int rx_qid; /* rx qid */
115 1.1 scw int rx_freeqid; /* rx free buffers qid */
116 1.1 scw int tx_qid; /* tx qid */
117 1.1 scw int tx_doneqid; /* tx completed qid */
118 1.1 scw struct npestats *sc_stats;
119 1.1 scw bus_dmamap_t sc_stats_map;
120 1.1 scw bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
121 1.13 msaitoh int sc_if_flags; /* keep last if_flags */
122 1.21 tls krndsource_t rnd_source; /* random source */
123 1.1 scw };
124 1.1 scw
125 1.1 scw /*
126 1.1 scw * Per-unit static configuration for IXP425. The tx and
127 1.1 scw * rx free Q id's are fixed by the NPE microcode. The
128 1.1 scw * rx Q id's are programmed to be separate to simplify
129 1.1 scw * multi-port processing. It may be better to handle
130 1.1 scw * all traffic through one Q (as done by the Intel drivers).
131 1.1 scw *
132 1.1 scw * Note that the PHY's are accessible only from MAC A
133 1.1 scw * on the IXP425. This and other platform-specific
134 1.1 scw * assumptions probably need to be handled through hints.
135 1.1 scw */
136 1.1 scw static const struct {
137 1.1 scw const char *desc; /* device description */
138 1.1 scw int npeid; /* NPE assignment */
139 1.16 msaitoh int macport; /* Port number of the MAC */
140 1.1 scw uint32_t imageid; /* NPE firmware image id */
141 1.1 scw uint32_t regbase;
142 1.1 scw int regsize;
143 1.1 scw uint32_t miibase;
144 1.1 scw int miisize;
145 1.1 scw uint8_t rx_qid;
146 1.1 scw uint8_t rx_freeqid;
147 1.1 scw uint8_t tx_qid;
148 1.1 scw uint8_t tx_doneqid;
149 1.1 scw } npeconfig[NPE_PORTS_MAX] = {
150 1.1 scw { .desc = "IXP NPE-B",
151 1.1 scw .npeid = NPE_B,
152 1.16 msaitoh .macport = 0x10,
153 1.1 scw .imageid = IXP425_NPE_B_IMAGEID,
154 1.1 scw .regbase = IXP425_MAC_A_HWBASE,
155 1.1 scw .regsize = IXP425_MAC_A_SIZE,
156 1.1 scw .miibase = IXP425_MAC_A_HWBASE,
157 1.1 scw .miisize = IXP425_MAC_A_SIZE,
158 1.1 scw .rx_qid = 4,
159 1.1 scw .rx_freeqid = 27,
160 1.1 scw .tx_qid = 24,
161 1.1 scw .tx_doneqid = 31
162 1.1 scw },
163 1.1 scw { .desc = "IXP NPE-C",
164 1.1 scw .npeid = NPE_C,
165 1.16 msaitoh .macport = 0x20,
166 1.1 scw .imageid = IXP425_NPE_C_IMAGEID,
167 1.1 scw .regbase = IXP425_MAC_B_HWBASE,
168 1.1 scw .regsize = IXP425_MAC_B_SIZE,
169 1.1 scw .miibase = IXP425_MAC_A_HWBASE,
170 1.1 scw .miisize = IXP425_MAC_A_SIZE,
171 1.1 scw .rx_qid = 12,
172 1.1 scw .rx_freeqid = 28,
173 1.1 scw .tx_qid = 25,
174 1.1 scw .tx_doneqid = 31
175 1.1 scw },
176 1.1 scw };
177 1.1 scw static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
178 1.1 scw
179 1.1 scw static __inline uint32_t
180 1.1 scw RD4(struct npe_softc *sc, bus_size_t off)
181 1.1 scw {
182 1.1 scw return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
183 1.1 scw }
184 1.1 scw
185 1.1 scw static __inline void
186 1.1 scw WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
187 1.1 scw {
188 1.1 scw bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
189 1.1 scw }
190 1.1 scw
191 1.1 scw static int npe_activate(struct npe_softc *);
192 1.1 scw #if 0
193 1.1 scw static void npe_deactivate(struct npe_softc *);
194 1.1 scw #endif
195 1.40 msaitoh static void npe_ifmedia_status(struct ifnet *, struct ifmediareq *);
196 1.40 msaitoh static void npe_setmac(struct npe_softc *, const u_char *);
197 1.40 msaitoh static void npe_getmac(struct npe_softc *);
198 1.40 msaitoh static void npe_txdone(int, void *);
199 1.1 scw static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
200 1.1 scw struct mbuf *);
201 1.40 msaitoh static void npe_rxdone(int, void *);
202 1.13 msaitoh static void npeinit_macreg(struct npe_softc *);
203 1.1 scw static int npeinit(struct ifnet *);
204 1.16 msaitoh static void npeinit_resetcb(void *);
205 1.13 msaitoh static void npeinit_locked(void *);
206 1.1 scw static void npestart(struct ifnet *);
207 1.1 scw static void npestop(struct ifnet *, int);
208 1.1 scw static void npewatchdog(struct ifnet *);
209 1.40 msaitoh static int npeioctl(struct ifnet *, u_long, void *);
210 1.1 scw
211 1.40 msaitoh static int npe_setrxqosentry(struct npe_softc *, int, int, int);
212 1.1 scw static int npe_updatestats(struct npe_softc *);
213 1.1 scw #if 0
214 1.1 scw static int npe_getstats(struct npe_softc *);
215 1.1 scw static uint32_t npe_getimageid(struct npe_softc *);
216 1.40 msaitoh static int npe_setloopback(struct npe_softc *, int);
217 1.1 scw #endif
218 1.1 scw
219 1.36 msaitoh static int npe_miibus_readreg(device_t, int, int, uint16_t *);
220 1.36 msaitoh static int npe_miibus_writereg(device_t, int, int, uint16_t);
221 1.23 matt static void npe_miibus_statchg(struct ifnet *);
222 1.1 scw
223 1.1 scw static int npe_debug;
224 1.1 scw #define DPRINTF(sc, fmt, ...) do { \
225 1.1 scw if (npe_debug) printf(fmt, __VA_ARGS__); \
226 1.1 scw } while (0)
227 1.1 scw #define DPRINTFn(n, sc, fmt, ...) do { \
228 1.1 scw if (npe_debug >= n) printf(fmt, __VA_ARGS__); \
229 1.1 scw } while (0)
230 1.1 scw
231 1.1 scw #define NPE_TXBUF 128
232 1.1 scw #define NPE_RXBUF 64
233 1.1 scw
234 1.11 msaitoh #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \
235 1.11 msaitoh + ((uint64_t)addr[1] << 32) \
236 1.11 msaitoh + ((uint64_t)addr[2] << 24) \
237 1.11 msaitoh + ((uint64_t)addr[3] << 16) \
238 1.11 msaitoh + ((uint64_t)addr[4] << 8) \
239 1.11 msaitoh + (uint64_t)addr[5])
240 1.11 msaitoh
241 1.1 scw /* NB: all tx done processing goes through one queue */
242 1.1 scw static int tx_doneqid = -1;
243 1.1 scw
244 1.11 msaitoh void (*npe_getmac_md)(int, uint8_t *);
245 1.11 msaitoh
246 1.23 matt static int npe_match(device_t, cfdata_t, void *);
247 1.23 matt static void npe_attach(device_t, device_t, void *);
248 1.1 scw
249 1.23 matt CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc),
250 1.1 scw npe_match, npe_attach, NULL, NULL);
251 1.1 scw
252 1.1 scw static int
253 1.23 matt npe_match(device_t parent, cfdata_t cf, void *arg)
254 1.1 scw {
255 1.1 scw struct ixpnpe_attach_args *na = arg;
256 1.1 scw
257 1.1 scw return (na->na_unit == NPE_B || na->na_unit == NPE_C);
258 1.1 scw }
259 1.1 scw
260 1.1 scw static void
261 1.23 matt npe_attach(device_t parent, device_t self, void *arg)
262 1.1 scw {
263 1.23 matt struct npe_softc *sc = device_private(self);
264 1.23 matt struct ixpnpe_softc *isc = device_private(parent);
265 1.1 scw struct ixpnpe_attach_args *na = arg;
266 1.1 scw struct ifnet *ifp;
267 1.40 msaitoh struct mii_data * const mii = &sc->sc_mii;
268 1.1 scw
269 1.1 scw aprint_naive("\n");
270 1.1 scw aprint_normal(": Ethernet co-processor\n");
271 1.1 scw
272 1.23 matt sc->sc_dev = self;
273 1.1 scw sc->sc_iot = na->na_iot;
274 1.1 scw sc->sc_dt = na->na_dt;
275 1.1 scw sc->sc_npe = na->na_npe;
276 1.1 scw sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1;
277 1.1 scw sc->sc_phy = na->na_phy;
278 1.1 scw
279 1.1 scw memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom));
280 1.40 msaitoh memset(mii, 0, sizeof(*mii));
281 1.1 scw
282 1.4 ad callout_init(&sc->sc_tick_ch, 0);
283 1.1 scw
284 1.1 scw if (npe_activate(sc)) {
285 1.23 matt aprint_error_dev(sc->sc_dev,
286 1.23 matt "Failed to activate NPE (missing microcode?)\n");
287 1.1 scw return;
288 1.1 scw }
289 1.1 scw
290 1.14 msaitoh npe_getmac(sc);
291 1.13 msaitoh npeinit_macreg(sc);
292 1.1 scw
293 1.23 matt aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
294 1.11 msaitoh ether_sprintf(sc->sc_enaddr));
295 1.1 scw
296 1.1 scw ifp = &sc->sc_ethercom.ec_if;
297 1.40 msaitoh mii->mii_ifp = ifp;
298 1.40 msaitoh mii->mii_readreg = npe_miibus_readreg;
299 1.40 msaitoh mii->mii_writereg = npe_miibus_writereg;
300 1.40 msaitoh mii->mii_statchg = npe_miibus_statchg;
301 1.40 msaitoh sc->sc_ethercom.ec_mii = mii;
302 1.15 msaitoh
303 1.40 msaitoh ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
304 1.1 scw npe_ifmedia_status);
305 1.1 scw
306 1.40 msaitoh mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
307 1.15 msaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
308 1.40 msaitoh if (LIST_FIRST(&mii->mii_phys) == NULL) {
309 1.40 msaitoh ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
310 1.40 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
311 1.15 msaitoh } else
312 1.40 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
313 1.1 scw
314 1.1 scw ifp->if_softc = sc;
315 1.23 matt strcpy(ifp->if_xname, device_xname(sc->sc_dev));
316 1.1 scw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
317 1.1 scw ifp->if_start = npestart;
318 1.1 scw ifp->if_ioctl = npeioctl;
319 1.1 scw ifp->if_watchdog = npewatchdog;
320 1.1 scw ifp->if_init = npeinit;
321 1.1 scw ifp->if_stop = npestop;
322 1.1 scw IFQ_SET_READY(&ifp->if_snd);
323 1.1 scw
324 1.10 msaitoh /* VLAN capable */
325 1.10 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
326 1.10 msaitoh
327 1.1 scw if_attach(ifp);
328 1.33 nonaka if_deferred_start_init(ifp, NULL);
329 1.11 msaitoh ether_ifattach(ifp, sc->sc_enaddr);
330 1.23 matt rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
331 1.26 tls RND_TYPE_NET, RND_FLAG_DEFAULT);
332 1.16 msaitoh
333 1.16 msaitoh /* callback function to reset MAC */
334 1.16 msaitoh isc->macresetcbfunc = npeinit_resetcb;
335 1.16 msaitoh isc->macresetcbarg = sc;
336 1.1 scw }
337 1.1 scw
338 1.1 scw /*
339 1.1 scw * Compute and install the multicast filter.
340 1.1 scw */
341 1.1 scw static void
342 1.1 scw npe_setmcast(struct npe_softc *sc)
343 1.1 scw {
344 1.40 msaitoh struct ethercom *ec = &sc->sc_ethercom;
345 1.40 msaitoh struct ifnet *ifp = &ec->ec_if;
346 1.1 scw uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
347 1.11 msaitoh uint32_t reg;
348 1.16 msaitoh uint32_t msg[2];
349 1.1 scw int i;
350 1.1 scw
351 1.11 msaitoh /* Always use filter. Is here a correct position? */
352 1.11 msaitoh reg = RD4(sc, NPE_MAC_RX_CNTRL1);
353 1.11 msaitoh WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN);
354 1.11 msaitoh
355 1.1 scw if (ifp->if_flags & IFF_PROMISC) {
356 1.1 scw memset(mask, 0, ETHER_ADDR_LEN);
357 1.1 scw memset(addr, 0, ETHER_ADDR_LEN);
358 1.1 scw } else if (ifp->if_flags & IFF_ALLMULTI) {
359 1.1 scw static const uint8_t allmulti[ETHER_ADDR_LEN] =
360 1.1 scw { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
361 1.1 scw all_multi:
362 1.1 scw memcpy(mask, allmulti, ETHER_ADDR_LEN);
363 1.1 scw memcpy(addr, allmulti, ETHER_ADDR_LEN);
364 1.1 scw } else {
365 1.1 scw uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
366 1.1 scw struct ether_multistep step;
367 1.1 scw struct ether_multi *enm;
368 1.1 scw
369 1.1 scw memset(clr, 0, ETHER_ADDR_LEN);
370 1.1 scw memset(set, 0xff, ETHER_ADDR_LEN);
371 1.1 scw
372 1.41 msaitoh ETHER_LOCK(ec);
373 1.40 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
374 1.1 scw while (enm != NULL) {
375 1.39 msaitoh if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
376 1.39 msaitoh ETHER_ADDR_LEN)) {
377 1.1 scw ifp->if_flags |= IFF_ALLMULTI;
378 1.41 msaitoh ETHER_UNLOCK(ec);
379 1.1 scw goto all_multi;
380 1.1 scw }
381 1.1 scw
382 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
383 1.1 scw clr[i] |= enm->enm_addrlo[i];
384 1.1 scw set[i] &= enm->enm_addrlo[i];
385 1.1 scw }
386 1.1 scw
387 1.1 scw ETHER_NEXT_MULTI(step, enm);
388 1.1 scw }
389 1.41 msaitoh ETHER_UNLOCK(ec);
390 1.1 scw
391 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
392 1.1 scw mask[i] = set[i] | ~clr[i];
393 1.1 scw addr[i] = set[i];
394 1.1 scw }
395 1.1 scw }
396 1.1 scw
397 1.1 scw /*
398 1.1 scw * Write the mask and address registers.
399 1.1 scw */
400 1.1 scw for (i = 0; i < ETHER_ADDR_LEN; i++) {
401 1.1 scw WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
402 1.1 scw WR4(sc, NPE_MAC_ADDR(i), addr[i]);
403 1.1 scw }
404 1.16 msaitoh
405 1.16 msaitoh msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL
406 1.16 msaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL);
407 1.16 msaitoh msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24
408 1.16 msaitoh | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16)
409 1.16 msaitoh | (addr[5] << 8) | mask[5];
410 1.16 msaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
411 1.1 scw }
412 1.1 scw
413 1.1 scw static int
414 1.1 scw npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
415 1.1 scw const char *name, int nbuf, int maxseg)
416 1.1 scw {
417 1.1 scw bus_dma_segment_t seg;
418 1.1 scw int rseg, error, i;
419 1.3 christos void *hwbuf;
420 1.1 scw size_t size;
421 1.1 scw
422 1.10 msaitoh memset(dma, 0, sizeof(*dma));
423 1.1 scw
424 1.1 scw dma->name = name;
425 1.1 scw dma->nbuf = nbuf;
426 1.1 scw
427 1.1 scw size = nbuf * sizeof(struct npehwbuf);
428 1.1 scw
429 1.1 scw /* XXX COHERENT for now */
430 1.1 scw error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg,
431 1.1 scw 1, &rseg, BUS_DMA_NOWAIT);
432 1.1 scw if (error) {
433 1.23 matt aprint_error_dev(sc->sc_dev,
434 1.23 matt "unable to %s for %s %s buffers, error %u\n",
435 1.23 matt "allocate memory", dma->name, "h/w", error);
436 1.1 scw }
437 1.1 scw
438 1.1 scw error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf,
439 1.1 scw BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
440 1.1 scw if (error) {
441 1.23 matt aprint_error_dev(sc->sc_dev,
442 1.23 matt "unable to %s for %s %s buffers, error %u\n",
443 1.23 matt "map memory", dma->name, "h/w", error);
444 1.1 scw free_dmamem:
445 1.1 scw bus_dmamem_free(sc->sc_dt, &seg, rseg);
446 1.1 scw return error;
447 1.1 scw }
448 1.1 scw dma->hwbuf = (void *)hwbuf;
449 1.1 scw
450 1.1 scw error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0,
451 1.1 scw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map);
452 1.1 scw if (error) {
453 1.23 matt aprint_error_dev(sc->sc_dev,
454 1.23 matt "unable to %s for %s %s buffers, error %u\n",
455 1.23 matt "create map", dma->name, "h/w", error);
456 1.1 scw unmap_dmamem:
457 1.1 scw dma->hwbuf = NULL;
458 1.1 scw bus_dmamem_unmap(sc->sc_dt, hwbuf, size);
459 1.1 scw goto free_dmamem;
460 1.1 scw }
461 1.1 scw
462 1.1 scw error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL,
463 1.1 scw BUS_DMA_NOWAIT);
464 1.1 scw if (error) {
465 1.23 matt aprint_error_dev(sc->sc_dev,
466 1.23 matt "unable to %s for %s %s buffers, error %u\n",
467 1.23 matt "load map", dma->name, "h/w", error);
468 1.1 scw destroy_dmamap:
469 1.1 scw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
470 1.1 scw goto unmap_dmamem;
471 1.1 scw }
472 1.1 scw
473 1.1 scw /* XXX M_TEMP */
474 1.39 msaitoh dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP,
475 1.39 msaitoh M_NOWAIT | M_ZERO);
476 1.1 scw if (dma->buf == NULL) {
477 1.23 matt aprint_error_dev(sc->sc_dev,
478 1.23 matt "unable to %s for %s %s buffers, error %u\n",
479 1.23 matt "allocate memory", dma->name, "h/w", error);
480 1.1 scw bus_dmamap_unload(sc->sc_dt, dma->buf_map);
481 1.1 scw error = ENOMEM;
482 1.1 scw goto destroy_dmamap;
483 1.1 scw }
484 1.1 scw
485 1.1 scw dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr;
486 1.1 scw for (i = 0; i < dma->nbuf; i++) {
487 1.1 scw struct npebuf *npe = &dma->buf[i];
488 1.1 scw struct npehwbuf *hw = &dma->hwbuf[i];
489 1.1 scw
490 1.39 msaitoh /* Calculate offset to shared area */
491 1.1 scw npe->ix_neaddr = dma->buf_phys +
492 1.1 scw ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
493 1.1 scw KASSERT((npe->ix_neaddr & 0x1f) == 0);
494 1.10 msaitoh error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg,
495 1.1 scw MCLBYTES, 0, 0, &npe->ix_map);
496 1.1 scw if (error != 0) {
497 1.23 matt aprint_error_dev(sc->sc_dev,
498 1.23 matt "unable to %s for %s buffer %u, error %u\n",
499 1.23 matt "create dmamap", dma->name, i, error);
500 1.1 scw /* XXXSCW: Free up maps... */
501 1.1 scw return error;
502 1.1 scw }
503 1.1 scw npe->ix_hw = hw;
504 1.1 scw }
505 1.1 scw bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize,
506 1.1 scw BUS_DMASYNC_PREWRITE);
507 1.1 scw return 0;
508 1.1 scw }
509 1.1 scw
510 1.1 scw #if 0
511 1.1 scw static void
512 1.1 scw npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
513 1.1 scw {
514 1.1 scw int i;
515 1.1 scw
516 1.1 scw /* XXXSCW: Clean this up */
517 1.1 scw
518 1.1 scw if (dma->hwbuf != NULL) {
519 1.1 scw for (i = 0; i < dma->nbuf; i++) {
520 1.1 scw struct npebuf *npe = &dma->buf[i];
521 1.1 scw bus_dmamap_destroy(sc->sc_dt, npe->ix_map);
522 1.1 scw }
523 1.1 scw bus_dmamap_unload(sc->sc_dt, dma->buf_map);
524 1.3 christos bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map);
525 1.1 scw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
526 1.1 scw }
527 1.1 scw if (dma->buf != NULL)
528 1.1 scw free(dma->buf, M_TEMP);
529 1.1 scw memset(dma, 0, sizeof(*dma));
530 1.1 scw }
531 1.1 scw #endif
532 1.1 scw
533 1.1 scw static int
534 1.1 scw npe_activate(struct npe_softc *sc)
535 1.1 scw {
536 1.1 scw bus_dma_segment_t seg;
537 1.1 scw int unit = sc->sc_unit;
538 1.1 scw int error, i, rseg;
539 1.3 christos void *statbuf;
540 1.1 scw
541 1.1 scw /* load NPE firmware and start it running */
542 1.1 scw error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid);
543 1.1 scw if (error != 0)
544 1.1 scw return error;
545 1.1 scw
546 1.1 scw if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase,
547 1.1 scw npeconfig[unit].regsize, 0, &sc->sc_ioh)) {
548 1.23 matt aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n",
549 1.23 matt npeconfig[unit].regbase, npeconfig[unit].regsize);
550 1.1 scw return ENOMEM;
551 1.1 scw }
552 1.1 scw
553 1.1 scw if (npeconfig[unit].miibase != npeconfig[unit].regbase) {
554 1.1 scw /*
555 1.1 scw * The PHY's are only accessible from one MAC (it appears)
556 1.1 scw * so for other MAC's setup an additional mapping for
557 1.1 scw * frobbing the PHY registers.
558 1.1 scw */
559 1.1 scw if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase,
560 1.1 scw npeconfig[unit].miisize, 0, &sc->sc_miih)) {
561 1.23 matt aprint_error_dev(sc->sc_dev,
562 1.23 matt "Cannot map MII registers 0x%x:0x%x\n",
563 1.23 matt npeconfig[unit].miibase, npeconfig[unit].miisize);
564 1.1 scw return ENOMEM;
565 1.1 scw }
566 1.1 scw } else
567 1.1 scw sc->sc_miih = sc->sc_ioh;
568 1.1 scw error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG);
569 1.1 scw if (error != 0)
570 1.1 scw return error;
571 1.1 scw error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1);
572 1.1 scw if (error != 0)
573 1.1 scw return error;
574 1.1 scw
575 1.1 scw /* setup statistics block */
576 1.1 scw error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats),
577 1.1 scw sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);
578 1.1 scw if (error) {
579 1.23 matt aprint_error_dev(sc->sc_dev,
580 1.23 matt "unable to %s for %s, error %u\n",
581 1.23 matt "allocate memory", "stats block", error);
582 1.1 scw return error;
583 1.1 scw }
584 1.1 scw
585 1.1 scw error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats),
586 1.1 scw &statbuf, BUS_DMA_NOWAIT);
587 1.1 scw if (error) {
588 1.23 matt aprint_error_dev(sc->sc_dev,
589 1.23 matt "unable to %s for %s, error %u\n",
590 1.23 matt "map memory", "stats block", error);
591 1.1 scw return error;
592 1.1 scw }
593 1.1 scw sc->sc_stats = (void *)statbuf;
594 1.1 scw
595 1.1 scw error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1,
596 1.1 scw sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
597 1.1 scw &sc->sc_stats_map);
598 1.1 scw if (error) {
599 1.23 matt aprint_error_dev(sc->sc_dev,
600 1.23 matt "unable to %s for %s, error %u\n",
601 1.23 matt "create map", "stats block", error);
602 1.1 scw return error;
603 1.1 scw }
604 1.1 scw
605 1.29 maxv error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats,
606 1.29 maxv sizeof(struct npestats), NULL, BUS_DMA_NOWAIT);
607 1.29 maxv if (error) {
608 1.23 matt aprint_error_dev(sc->sc_dev,
609 1.23 matt "unable to %s for %s, error %u\n",
610 1.23 matt "load map", "stats block", error);
611 1.1 scw return error;
612 1.1 scw }
613 1.1 scw sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr;
614 1.1 scw
615 1.1 scw /* XXX disable half-bridge LEARNING+FILTERING feature */
616 1.1 scw
617 1.1 scw /*
618 1.1 scw * Setup h/w rx/tx queues. There are four q's:
619 1.1 scw * rx inbound q of rx'd frames
620 1.1 scw * rx_free pool of ixpbuf's for receiving frames
621 1.1 scw * tx outbound q of frames to send
622 1.1 scw * tx_done q of tx frames that have been processed
623 1.1 scw *
624 1.1 scw * The NPE handles the actual tx/rx process and the q manager
625 1.1 scw * handles the queues. The driver just writes entries to the
626 1.1 scw * q manager mailbox's and gets callbacks when there are rx'd
627 1.1 scw * frames to process or tx'd frames to reap. These callbacks
628 1.1 scw * are controlled by the q configurations; e.g. we get a
629 1.1 scw * callback when tx_done has 2 or more frames to process and
630 1.1 scw * when the rx q has at least one frame. These setings can
631 1.1 scw * changed at the time the q is configured.
632 1.1 scw */
633 1.1 scw sc->rx_qid = npeconfig[unit].rx_qid;
634 1.1 scw ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1,
635 1.1 scw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc);
636 1.1 scw sc->rx_freeqid = npeconfig[unit].rx_freeqid;
637 1.1 scw ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc);
638 1.1 scw /* tell the NPE to direct all traffic to rx_qid */
639 1.1 scw #if 0
640 1.1 scw for (i = 0; i < 8; i++)
641 1.1 scw #else
642 1.23 matt printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev));
643 1.1 scw for (i = 0; i < 4; i++)
644 1.1 scw #endif
645 1.1 scw npe_setrxqosentry(sc, i, 0, sc->rx_qid);
646 1.1 scw
647 1.1 scw sc->tx_qid = npeconfig[unit].tx_qid;
648 1.1 scw sc->tx_doneqid = npeconfig[unit].tx_doneqid;
649 1.1 scw ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc);
650 1.1 scw if (tx_doneqid == -1) {
651 1.1 scw ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2,
652 1.1 scw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
653 1.1 scw tx_doneqid = sc->tx_doneqid;
654 1.1 scw }
655 1.1 scw
656 1.1 scw KASSERT(npes[npeconfig[unit].npeid] == NULL);
657 1.1 scw npes[npeconfig[unit].npeid] = sc;
658 1.1 scw
659 1.1 scw return 0;
660 1.1 scw }
661 1.1 scw
662 1.1 scw #if 0
663 1.1 scw static void
664 1.1 scw npe_deactivate(struct npe_softc *sc);
665 1.1 scw {
666 1.1 scw int unit = sc->sc_unit;
667 1.1 scw
668 1.1 scw npes[npeconfig[unit].npeid] = NULL;
669 1.1 scw
670 1.1 scw /* XXX disable q's */
671 1.1 scw if (sc->sc_npe != NULL)
672 1.1 scw ixpnpe_stop(sc->sc_npe);
673 1.1 scw if (sc->sc_stats != NULL) {
674 1.1 scw bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
675 1.1 scw bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
676 1.1 scw sc->sc_stats_map);
677 1.1 scw bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map);
678 1.1 scw }
679 1.1 scw if (sc->sc_stats_tag != NULL)
680 1.1 scw bus_dma_tag_destroy(sc->sc_stats_tag);
681 1.1 scw npe_dma_destroy(sc, &sc->txdma);
682 1.1 scw npe_dma_destroy(sc, &sc->rxdma);
683 1.1 scw bus_generic_detach(sc->sc_dev);
684 1.1 scw if (sc->sc_mii)
685 1.1 scw device_delete_child(sc->sc_dev, sc->sc_mii);
686 1.1 scw #if 0
687 1.1 scw /* XXX sc_ioh and sc_miih */
688 1.1 scw if (sc->mem_res)
689 1.1 scw bus_release_resource(dev, SYS_RES_IOPORT,
690 1.1 scw rman_get_rid(sc->mem_res), sc->mem_res);
691 1.1 scw sc->mem_res = 0;
692 1.1 scw #endif
693 1.1 scw }
694 1.1 scw #endif
695 1.1 scw
696 1.1 scw /*
697 1.1 scw * Notify the world which media we're using.
698 1.1 scw */
699 1.1 scw static void
700 1.1 scw npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
701 1.1 scw {
702 1.1 scw struct npe_softc *sc = ifp->if_softc;
703 1.1 scw
704 1.15 msaitoh mii_pollstat(&sc->sc_mii);
705 1.1 scw
706 1.1 scw ifmr->ifm_active = sc->sc_mii.mii_media_active;
707 1.1 scw ifmr->ifm_status = sc->sc_mii.mii_media_status;
708 1.1 scw }
709 1.1 scw
710 1.1 scw static void
711 1.1 scw npe_addstats(struct npe_softc *sc)
712 1.1 scw {
713 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
714 1.1 scw struct npestats *ns = sc->sc_stats;
715 1.1 scw
716 1.1 scw ifp->if_oerrors +=
717 1.1 scw be32toh(ns->dot3StatsInternalMacTransmitErrors)
718 1.1 scw + be32toh(ns->dot3StatsCarrierSenseErrors)
719 1.1 scw + be32toh(ns->TxVLANIdFilterDiscards)
720 1.1 scw ;
721 1.1 scw ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors)
722 1.1 scw + be32toh(ns->dot3StatsInternalMacReceiveErrors)
723 1.1 scw + be32toh(ns->RxOverrunDiscards)
724 1.1 scw + be32toh(ns->RxUnderflowEntryDiscards)
725 1.1 scw ;
726 1.1 scw ifp->if_collisions +=
727 1.1 scw be32toh(ns->dot3StatsSingleCollisionFrames)
728 1.1 scw + be32toh(ns->dot3StatsMultipleCollisionFrames)
729 1.1 scw ;
730 1.1 scw }
731 1.1 scw
732 1.1 scw static void
733 1.1 scw npe_tick(void *xsc)
734 1.1 scw {
735 1.1 scw #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
736 1.1 scw struct npe_softc *sc = xsc;
737 1.1 scw uint32_t msg[2];
738 1.1 scw
739 1.1 scw /*
740 1.1 scw * NB: to avoid sleeping with the softc lock held we
741 1.1 scw * split the NPE msg processing into two parts. The
742 1.1 scw * request for statistics is sent w/o waiting for a
743 1.1 scw * reply and then on the next tick we retrieve the
744 1.1 scw * results. This works because npe_tick is the only
745 1.1 scw * code that talks via the mailbox's (except at setup).
746 1.1 scw * This likely can be handled better.
747 1.1 scw */
748 1.1 scw if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
749 1.1 scw bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0,
750 1.1 scw sizeof(struct npestats), BUS_DMASYNC_POSTREAD);
751 1.1 scw npe_addstats(sc);
752 1.1 scw }
753 1.1 scw npe_updatestats(sc);
754 1.1 scw mii_tick(&sc->sc_mii);
755 1.1 scw
756 1.39 msaitoh /* Schedule next poll */
757 1.1 scw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
758 1.1 scw #undef ACK
759 1.1 scw }
760 1.1 scw
761 1.1 scw static void
762 1.6 matt npe_setmac(struct npe_softc *sc, const u_char *eaddr)
763 1.1 scw {
764 1.11 msaitoh
765 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
766 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
767 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
768 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
769 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
770 1.1 scw WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
771 1.1 scw }
772 1.1 scw
773 1.1 scw static void
774 1.11 msaitoh npe_getmac(struct npe_softc *sc)
775 1.1 scw {
776 1.11 msaitoh uint8_t *eaddr = sc->sc_enaddr;
777 1.11 msaitoh
778 1.11 msaitoh if (npe_getmac_md != NULL) {
779 1.23 matt (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr);
780 1.11 msaitoh } else {
781 1.11 msaitoh /*
782 1.11 msaitoh * Some system's unicast address appears to be loaded from
783 1.11 msaitoh * EEPROM on reset
784 1.11 msaitoh */
785 1.11 msaitoh eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
786 1.11 msaitoh eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
787 1.11 msaitoh eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
788 1.11 msaitoh eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
789 1.11 msaitoh eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
790 1.11 msaitoh eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
791 1.11 msaitoh }
792 1.1 scw }
793 1.1 scw
794 1.1 scw struct txdone {
795 1.1 scw struct npebuf *head;
796 1.1 scw struct npebuf **tail;
797 1.1 scw int count;
798 1.1 scw };
799 1.1 scw
800 1.1 scw static __inline void
801 1.1 scw npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
802 1.1 scw {
803 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
804 1.1 scw
805 1.1 scw *td->tail = sc->tx_free;
806 1.1 scw sc->tx_free = td->head;
807 1.1 scw /*
808 1.1 scw * We're no longer busy, so clear the busy flag and call the
809 1.1 scw * start routine to xmit more packets.
810 1.1 scw */
811 1.1 scw ifp->if_opackets += td->count;
812 1.1 scw ifp->if_flags &= ~IFF_OACTIVE;
813 1.1 scw ifp->if_timer = 0;
814 1.33 nonaka if_schedule_deferred_start(ifp);
815 1.1 scw }
816 1.1 scw
817 1.1 scw /*
818 1.1 scw * Q manager callback on tx done queue. Reap mbufs
819 1.1 scw * and return tx buffers to the free list. Finally
820 1.1 scw * restart output. Note the microcode has only one
821 1.1 scw * txdone q wired into it so we must use the NPE ID
822 1.1 scw * returned with each npehwbuf to decide where to
823 1.1 scw * send buffers.
824 1.1 scw */
825 1.1 scw static void
826 1.1 scw npe_txdone(int qid, void *arg)
827 1.1 scw {
828 1.1 scw #define P2V(a, dma) \
829 1.1 scw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
830 1.1 scw struct npe_softc *sc;
831 1.1 scw struct npebuf *npe;
832 1.1 scw struct txdone *td, q[NPE_MAX];
833 1.1 scw uint32_t entry;
834 1.1 scw
835 1.1 scw /* XXX no NPE-A support */
836 1.1 scw q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
837 1.1 scw q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
838 1.1 scw /* XXX max # at a time? */
839 1.1 scw while (ixpqmgr_qread(qid, &entry) == 0) {
840 1.1 scw sc = npes[NPE_QM_Q_NPE(entry)];
841 1.1 scw DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n",
842 1.1 scw __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
843 1.22 tls rnd_add_uint32(&sc->rnd_source, entry);
844 1.1 scw
845 1.1 scw npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
846 1.1 scw m_freem(npe->ix_m);
847 1.1 scw npe->ix_m = NULL;
848 1.1 scw
849 1.1 scw td = &q[NPE_QM_Q_NPE(entry)];
850 1.1 scw *td->tail = npe;
851 1.1 scw td->tail = &npe->ix_next;
852 1.1 scw td->count++;
853 1.1 scw }
854 1.1 scw
855 1.1 scw if (q[NPE_B].count)
856 1.1 scw npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
857 1.1 scw if (q[NPE_C].count)
858 1.1 scw npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
859 1.1 scw #undef P2V
860 1.1 scw }
861 1.1 scw
862 1.1 scw static __inline struct mbuf *
863 1.1 scw npe_getcl(void)
864 1.1 scw {
865 1.1 scw struct mbuf *m;
866 1.1 scw
867 1.1 scw MGETHDR(m, M_DONTWAIT, MT_DATA);
868 1.1 scw if (m != NULL) {
869 1.1 scw MCLGET(m, M_DONTWAIT);
870 1.1 scw if ((m->m_flags & M_EXT) == 0) {
871 1.1 scw m_freem(m);
872 1.1 scw m = NULL;
873 1.1 scw }
874 1.1 scw }
875 1.39 msaitoh return m;
876 1.1 scw }
877 1.1 scw
878 1.1 scw static int
879 1.1 scw npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
880 1.1 scw {
881 1.1 scw struct npehwbuf *hw;
882 1.1 scw int error;
883 1.1 scw
884 1.1 scw if (m == NULL) {
885 1.1 scw m = npe_getcl();
886 1.1 scw if (m == NULL)
887 1.1 scw return ENOBUFS;
888 1.1 scw }
889 1.11 msaitoh KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
890 1.11 msaitoh m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT;
891 1.1 scw /* backload payload and align ip hdr */
892 1.11 msaitoh m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size
893 1.11 msaitoh - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
894 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
895 1.40 msaitoh BUS_DMA_READ | BUS_DMA_NOWAIT);
896 1.1 scw if (error != 0) {
897 1.1 scw m_freem(m);
898 1.1 scw return error;
899 1.1 scw }
900 1.1 scw hw = npe->ix_hw;
901 1.1 scw hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr);
902 1.1 scw /* NB: NPE requires length be a multiple of 64 */
903 1.1 scw /* NB: buffer length is shifted in word */
904 1.1 scw hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16);
905 1.1 scw hw->ix_ne[0].next = 0;
906 1.1 scw npe->ix_m = m;
907 1.1 scw /* Flush the memory in the mbuf */
908 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize,
909 1.1 scw BUS_DMASYNC_PREREAD);
910 1.1 scw return 0;
911 1.1 scw }
912 1.1 scw
913 1.1 scw /*
914 1.1 scw * RX q processing for a specific NPE. Claim entries
915 1.1 scw * from the hardware queue and pass the frames up the
916 1.1 scw * stack. Pass the rx buffers to the free list.
917 1.1 scw */
918 1.1 scw static void
919 1.1 scw npe_rxdone(int qid, void *arg)
920 1.1 scw {
921 1.1 scw #define P2V(a, dma) \
922 1.1 scw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
923 1.1 scw struct npe_softc *sc = arg;
924 1.1 scw struct npedma *dma = &sc->rxdma;
925 1.1 scw uint32_t entry;
926 1.1 scw
927 1.1 scw while (ixpqmgr_qread(qid, &entry) == 0) {
928 1.1 scw struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
929 1.1 scw struct mbuf *m;
930 1.1 scw
931 1.1 scw DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
932 1.1 scw __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
933 1.22 tls rnd_add_uint32(&sc->rnd_source, entry);
934 1.1 scw /*
935 1.1 scw * Allocate a new mbuf to replenish the rx buffer.
936 1.1 scw * If doing so fails we drop the rx'd frame so we
937 1.1 scw * can reuse the previous mbuf. When we're able to
938 1.1 scw * allocate a new mbuf dispatch the mbuf w/ rx'd
939 1.1 scw * data up the stack and replace it with the newly
940 1.1 scw * allocated one.
941 1.1 scw */
942 1.1 scw m = npe_getcl();
943 1.1 scw if (m != NULL) {
944 1.1 scw struct mbuf *mrx = npe->ix_m;
945 1.1 scw struct npehwbuf *hw = npe->ix_hw;
946 1.1 scw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
947 1.1 scw
948 1.1 scw /* Flush mbuf memory for rx'd data */
949 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
950 1.1 scw npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
951 1.1 scw
952 1.1 scw /* XXX flush hw buffer; works now 'cuz coherent */
953 1.1 scw /* set m_len etc. per rx frame size */
954 1.1 scw mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
955 1.1 scw mrx->m_pkthdr.len = mrx->m_len;
956 1.31 ozaki m_set_rcvif(mrx, ifp);
957 1.11 msaitoh /* Don't add M_HASFCS. See below */
958 1.11 msaitoh
959 1.11 msaitoh #if 1
960 1.11 msaitoh if (mrx->m_pkthdr.len < sizeof(struct ether_header)) {
961 1.11 msaitoh log(LOG_INFO, "%s: too short frame (len=%d)\n",
962 1.39 msaitoh device_xname(sc->sc_dev),
963 1.39 msaitoh mrx->m_pkthdr.len);
964 1.11 msaitoh /* Back out "newly allocated" mbuf. */
965 1.11 msaitoh m_freem(m);
966 1.11 msaitoh ifp->if_ierrors++;
967 1.11 msaitoh goto fail;
968 1.11 msaitoh }
969 1.11 msaitoh if ((ifp->if_flags & IFF_PROMISC) == 0) {
970 1.11 msaitoh struct ether_header *eh;
971 1.11 msaitoh
972 1.11 msaitoh /*
973 1.11 msaitoh * Workaround for "Non-Intel XScale Technology
974 1.11 msaitoh * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet
975 1.11 msaitoh * matches the filter (both unicast and
976 1.11 msaitoh * multicast).
977 1.11 msaitoh */
978 1.11 msaitoh eh = mtod(mrx, struct ether_header *);
979 1.11 msaitoh if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) {
980 1.39 msaitoh /* Unicast */
981 1.11 msaitoh
982 1.11 msaitoh if (sc->sc_enaddr[5] != eh->ether_dhost[5]) {
983 1.39 msaitoh /* Discard it */
984 1.11 msaitoh #if 0
985 1.11 msaitoh printf("discard it\n");
986 1.11 msaitoh #endif
987 1.11 msaitoh /*
988 1.11 msaitoh * Back out "newly allocated"
989 1.11 msaitoh * mbuf.
990 1.11 msaitoh */
991 1.11 msaitoh m_freem(m);
992 1.11 msaitoh goto fail;
993 1.11 msaitoh }
994 1.11 msaitoh } else if (memcmp(eh->ether_dhost,
995 1.11 msaitoh etherbroadcastaddr, 6) == 0) {
996 1.11 msaitoh /* Always accept broadcast packet*/
997 1.11 msaitoh } else {
998 1.11 msaitoh struct ethercom *ec = &sc->sc_ethercom;
999 1.11 msaitoh struct ether_multi *enm;
1000 1.11 msaitoh struct ether_multistep step;
1001 1.11 msaitoh int match = 0;
1002 1.11 msaitoh
1003 1.39 msaitoh /* Multicast */
1004 1.11 msaitoh
1005 1.41 msaitoh ETHER_LOCK(ec);
1006 1.11 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
1007 1.11 msaitoh while (enm != NULL) {
1008 1.11 msaitoh uint64_t lowint, highint, dest;
1009 1.11 msaitoh
1010 1.11 msaitoh lowint = MAC2UINT64(enm->enm_addrlo);
1011 1.11 msaitoh highint = MAC2UINT64(enm->enm_addrhi);
1012 1.11 msaitoh dest = MAC2UINT64(eh->ether_dhost);
1013 1.11 msaitoh #if 0
1014 1.11 msaitoh printf("%llx\n", lowint);
1015 1.11 msaitoh printf("%llx\n", dest);
1016 1.11 msaitoh printf("%llx\n", highint);
1017 1.11 msaitoh #endif
1018 1.11 msaitoh if ((lowint <= dest) && (dest <= highint)) {
1019 1.11 msaitoh match = 1;
1020 1.11 msaitoh break;
1021 1.11 msaitoh }
1022 1.11 msaitoh ETHER_NEXT_MULTI(step, enm);
1023 1.11 msaitoh }
1024 1.41 msaitoh ETHER_UNLOCK(ec);
1025 1.41 msaitoh
1026 1.11 msaitoh if (match == 0) {
1027 1.39 msaitoh /* Discard it */
1028 1.11 msaitoh #if 0
1029 1.11 msaitoh printf("discard it(M)\n");
1030 1.11 msaitoh #endif
1031 1.11 msaitoh /*
1032 1.11 msaitoh * Back out "newly allocated"
1033 1.11 msaitoh * mbuf.
1034 1.11 msaitoh */
1035 1.11 msaitoh m_freem(m);
1036 1.11 msaitoh goto fail;
1037 1.11 msaitoh }
1038 1.11 msaitoh }
1039 1.11 msaitoh }
1040 1.11 msaitoh if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) {
1041 1.11 msaitoh log(LOG_INFO, "%s: oversized frame (len=%d)\n",
1042 1.23 matt device_xname(sc->sc_dev), mrx->m_pkthdr.len);
1043 1.11 msaitoh /* Back out "newly allocated" mbuf. */
1044 1.11 msaitoh m_freem(m);
1045 1.11 msaitoh ifp->if_ierrors++;
1046 1.11 msaitoh goto fail;
1047 1.11 msaitoh }
1048 1.11 msaitoh #endif
1049 1.11 msaitoh
1050 1.11 msaitoh /*
1051 1.11 msaitoh * Trim FCS!
1052 1.11 msaitoh * NPE always adds the FCS by this driver's setting,
1053 1.11 msaitoh * so we always trim it here and not add M_HASFCS.
1054 1.11 msaitoh */
1055 1.11 msaitoh m_adj(mrx, -ETHER_CRC_LEN);
1056 1.1 scw
1057 1.10 msaitoh /*
1058 1.10 msaitoh * Tap off here if there is a bpf listener.
1059 1.10 msaitoh */
1060 1.32 ozaki
1061 1.30 ozaki if_percpuq_enqueue(ifp->if_percpuq, mrx);
1062 1.1 scw } else {
1063 1.11 msaitoh fail:
1064 1.1 scw /* discard frame and re-use mbuf */
1065 1.1 scw m = npe->ix_m;
1066 1.1 scw }
1067 1.1 scw if (npe_rxbuf_init(sc, npe, m) == 0) {
1068 1.1 scw /* return npe buf to rx free list */
1069 1.1 scw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1070 1.1 scw } else {
1071 1.1 scw /* XXX should not happen */
1072 1.1 scw }
1073 1.1 scw }
1074 1.1 scw #undef P2V
1075 1.1 scw }
1076 1.1 scw
1077 1.1 scw static void
1078 1.1 scw npe_startxmit(struct npe_softc *sc)
1079 1.1 scw {
1080 1.1 scw struct npedma *dma = &sc->txdma;
1081 1.1 scw int i;
1082 1.1 scw
1083 1.1 scw sc->tx_free = NULL;
1084 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1085 1.1 scw struct npebuf *npe = &dma->buf[i];
1086 1.1 scw if (npe->ix_m != NULL) {
1087 1.1 scw /* NB: should not happen */
1088 1.1 scw printf("%s: %s: free mbuf at entry %u\n",
1089 1.23 matt device_xname(sc->sc_dev), __func__, i);
1090 1.1 scw m_freem(npe->ix_m);
1091 1.1 scw }
1092 1.1 scw npe->ix_m = NULL;
1093 1.1 scw npe->ix_next = sc->tx_free;
1094 1.1 scw sc->tx_free = npe;
1095 1.1 scw }
1096 1.1 scw }
1097 1.1 scw
1098 1.1 scw static void
1099 1.1 scw npe_startrecv(struct npe_softc *sc)
1100 1.1 scw {
1101 1.1 scw struct npedma *dma = &sc->rxdma;
1102 1.1 scw struct npebuf *npe;
1103 1.1 scw int i;
1104 1.1 scw
1105 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1106 1.1 scw npe = &dma->buf[i];
1107 1.1 scw npe_rxbuf_init(sc, npe, npe->ix_m);
1108 1.39 msaitoh /* Set npe buf on rx free list */
1109 1.1 scw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1110 1.1 scw }
1111 1.1 scw }
1112 1.1 scw
1113 1.1 scw static void
1114 1.13 msaitoh npeinit_macreg(struct npe_softc *sc)
1115 1.1 scw {
1116 1.1 scw
1117 1.1 scw /*
1118 1.1 scw * Reset MAC core.
1119 1.1 scw */
1120 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1121 1.1 scw DELAY(NPE_MAC_RESET_DELAY);
1122 1.39 msaitoh /* Configure MAC to generate MDC clock */
1123 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1124 1.1 scw
1125 1.39 msaitoh /* Disable transmitter and reciver in the MAC */
1126 1.39 msaitoh WR4(sc, NPE_MAC_RX_CNTRL1,
1127 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1128 1.39 msaitoh WR4(sc, NPE_MAC_TX_CNTRL1,
1129 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1130 1.1 scw
1131 1.1 scw /*
1132 1.1 scw * Set the MAC core registers.
1133 1.1 scw */
1134 1.1 scw WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1135 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1136 1.1 scw WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
1137 1.39 msaitoh /* Thresholds determined by NPE firmware FS */
1138 1.1 scw WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1139 1.1 scw WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1140 1.12 msaitoh WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT);
1141 1.12 msaitoh /* tx fifo threshold (bytes) */
1142 1.1 scw WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1143 1.1 scw WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1144 1.1 scw WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1145 1.1 scw WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1146 1.12 msaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
1147 1.12 msaitoh /* assumes MII mode */
1148 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1,
1149 1.1 scw NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1150 1.1 scw | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1151 1.1 scw | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1152 1.1 scw | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1153 1.1 scw /* XXX pad strip? */
1154 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1,
1155 1.1 scw NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */
1156 1.1 scw | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */
1157 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1158 1.13 msaitoh }
1159 1.1 scw
1160 1.16 msaitoh static void
1161 1.16 msaitoh npeinit_resetcb(void *xsc)
1162 1.16 msaitoh {
1163 1.16 msaitoh struct npe_softc *sc = xsc;
1164 1.16 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1165 1.16 msaitoh uint32_t msg[2];
1166 1.16 msaitoh
1167 1.16 msaitoh ifp->if_oerrors++;
1168 1.16 msaitoh npeinit_locked(sc);
1169 1.16 msaitoh
1170 1.16 msaitoh msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL
1171 1.16 msaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL);
1172 1.16 msaitoh msg[1] = 0;
1173 1.16 msaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1174 1.16 msaitoh }
1175 1.16 msaitoh
1176 1.13 msaitoh /*
1177 1.13 msaitoh * Reset and initialize the chip
1178 1.13 msaitoh */
1179 1.13 msaitoh static void
1180 1.13 msaitoh npeinit_locked(void *xsc)
1181 1.13 msaitoh {
1182 1.13 msaitoh struct npe_softc *sc = xsc;
1183 1.13 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1184 1.13 msaitoh
1185 1.13 msaitoh /* Cancel any pending I/O. */
1186 1.13 msaitoh npestop(ifp, 0);
1187 1.13 msaitoh
1188 1.13 msaitoh /* Reset the chip to a known state. */
1189 1.13 msaitoh npeinit_macreg(sc);
1190 1.6 matt npe_setmac(sc, CLLADDR(ifp->if_sadl));
1191 1.15 msaitoh ether_mediachange(ifp);
1192 1.1 scw npe_setmcast(sc);
1193 1.1 scw
1194 1.1 scw npe_startxmit(sc);
1195 1.1 scw npe_startrecv(sc);
1196 1.1 scw
1197 1.1 scw ifp->if_flags |= IFF_RUNNING;
1198 1.1 scw ifp->if_flags &= ~IFF_OACTIVE;
1199 1.1 scw ifp->if_timer = 0; /* just in case */
1200 1.1 scw
1201 1.39 msaitoh /* Enable transmitter and reciver in the MAC */
1202 1.39 msaitoh WR4(sc, NPE_MAC_RX_CNTRL1,
1203 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1204 1.39 msaitoh WR4(sc, NPE_MAC_TX_CNTRL1,
1205 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1206 1.1 scw
1207 1.1 scw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
1208 1.1 scw }
1209 1.1 scw
1210 1.1 scw static int
1211 1.1 scw npeinit(struct ifnet *ifp)
1212 1.1 scw {
1213 1.1 scw struct npe_softc *sc = ifp->if_softc;
1214 1.1 scw int s;
1215 1.1 scw
1216 1.1 scw s = splnet();
1217 1.1 scw npeinit_locked(sc);
1218 1.1 scw splx(s);
1219 1.1 scw
1220 1.39 msaitoh return 0;
1221 1.1 scw }
1222 1.1 scw
1223 1.1 scw /*
1224 1.1 scw * Defragment an mbuf chain, returning at most maxfrags separate
1225 1.1 scw * mbufs+clusters. If this is not possible NULL is returned and
1226 1.27 snj * the original mbuf chain is left in its present (potentially
1227 1.1 scw * modified) state. We use two techniques: collapsing consecutive
1228 1.1 scw * mbufs and replacing consecutive mbufs by a cluster.
1229 1.1 scw */
1230 1.1 scw static __inline struct mbuf *
1231 1.1 scw npe_defrag(struct mbuf *m0)
1232 1.1 scw {
1233 1.1 scw struct mbuf *m;
1234 1.1 scw
1235 1.1 scw MGETHDR(m, M_DONTWAIT, MT_DATA);
1236 1.1 scw if (m == NULL)
1237 1.39 msaitoh return NULL;
1238 1.35 maxv m_copy_pkthdr(m, m0);
1239 1.1 scw
1240 1.1 scw if ((m->m_len = m0->m_pkthdr.len) > MHLEN) {
1241 1.1 scw MCLGET(m, M_DONTWAIT);
1242 1.1 scw if ((m->m_flags & M_EXT) == 0) {
1243 1.1 scw m_freem(m);
1244 1.39 msaitoh return NULL;
1245 1.1 scw }
1246 1.1 scw }
1247 1.1 scw
1248 1.3 christos m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
1249 1.1 scw m_freem(m0);
1250 1.1 scw
1251 1.39 msaitoh return m;
1252 1.1 scw }
1253 1.1 scw
1254 1.1 scw /*
1255 1.1 scw * Dequeue packets and place on the h/w transmit queue.
1256 1.1 scw */
1257 1.1 scw static void
1258 1.1 scw npestart(struct ifnet *ifp)
1259 1.1 scw {
1260 1.1 scw struct npe_softc *sc = ifp->if_softc;
1261 1.1 scw struct npebuf *npe;
1262 1.1 scw struct npehwbuf *hw;
1263 1.1 scw struct mbuf *m, *n;
1264 1.1 scw bus_dma_segment_t *segs;
1265 1.1 scw int nseg, len, error, i;
1266 1.1 scw uint32_t next;
1267 1.1 scw
1268 1.40 msaitoh if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1269 1.1 scw return;
1270 1.1 scw
1271 1.1 scw while (sc->tx_free != NULL) {
1272 1.1 scw IFQ_DEQUEUE(&ifp->if_snd, m);
1273 1.13 msaitoh if (m == NULL)
1274 1.13 msaitoh break;
1275 1.1 scw npe = sc->tx_free;
1276 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
1277 1.40 msaitoh BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1278 1.1 scw if (error == EFBIG) {
1279 1.1 scw n = npe_defrag(m);
1280 1.1 scw if (n == NULL) {
1281 1.1 scw printf("%s: %s: too many fragments\n",
1282 1.23 matt device_xname(sc->sc_dev), __func__);
1283 1.1 scw m_freem(m);
1284 1.1 scw return; /* XXX? */
1285 1.1 scw }
1286 1.1 scw m = n;
1287 1.1 scw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map,
1288 1.40 msaitoh m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1289 1.1 scw }
1290 1.1 scw if (error != 0) {
1291 1.1 scw printf("%s: %s: error %u\n",
1292 1.23 matt device_xname(sc->sc_dev), __func__, error);
1293 1.1 scw m_freem(m);
1294 1.1 scw return; /* XXX? */
1295 1.1 scw }
1296 1.1 scw sc->tx_free = npe->ix_next;
1297 1.1 scw
1298 1.1 scw /*
1299 1.1 scw * Tap off here if there is a bpf listener.
1300 1.1 scw */
1301 1.34 msaitoh bpf_mtap(ifp, m, BPF_D_OUT);
1302 1.1 scw
1303 1.1 scw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
1304 1.1 scw npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1305 1.1 scw
1306 1.1 scw npe->ix_m = m;
1307 1.1 scw hw = npe->ix_hw;
1308 1.1 scw len = m->m_pkthdr.len;
1309 1.1 scw nseg = npe->ix_map->dm_nsegs;
1310 1.1 scw segs = npe->ix_map->dm_segs;
1311 1.1 scw next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1312 1.1 scw for (i = 0; i < nseg; i++) {
1313 1.1 scw hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1314 1.1 scw hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1315 1.1 scw hw->ix_ne[i].next = htobe32(next);
1316 1.1 scw
1317 1.1 scw len = 0; /* zero for segments > 1 */
1318 1.1 scw next += sizeof(hw->ix_ne[0]);
1319 1.1 scw }
1320 1.1 scw hw->ix_ne[i-1].next = 0; /* zero last in chain */
1321 1.1 scw /* XXX flush descriptor instead of using uncached memory */
1322 1.1 scw
1323 1.1 scw DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1324 1.1 scw __func__, sc->tx_qid, npe->ix_neaddr,
1325 1.1 scw hw->ix_ne[0].data, hw->ix_ne[0].len);
1326 1.1 scw /* stick it on the tx q */
1327 1.1 scw /* XXX add vlan priority */
1328 1.1 scw ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1329 1.1 scw
1330 1.1 scw ifp->if_timer = 5;
1331 1.1 scw }
1332 1.1 scw if (sc->tx_free == NULL)
1333 1.1 scw ifp->if_flags |= IFF_OACTIVE;
1334 1.1 scw }
1335 1.1 scw
1336 1.1 scw static void
1337 1.1 scw npe_stopxmit(struct npe_softc *sc)
1338 1.1 scw {
1339 1.1 scw struct npedma *dma = &sc->txdma;
1340 1.1 scw int i;
1341 1.1 scw
1342 1.1 scw /* XXX qmgr */
1343 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1344 1.1 scw struct npebuf *npe = &dma->buf[i];
1345 1.1 scw
1346 1.1 scw if (npe->ix_m != NULL) {
1347 1.1 scw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1348 1.1 scw m_freem(npe->ix_m);
1349 1.1 scw npe->ix_m = NULL;
1350 1.1 scw }
1351 1.1 scw }
1352 1.1 scw }
1353 1.1 scw
1354 1.1 scw static void
1355 1.1 scw npe_stoprecv(struct npe_softc *sc)
1356 1.1 scw {
1357 1.1 scw struct npedma *dma = &sc->rxdma;
1358 1.1 scw int i;
1359 1.1 scw
1360 1.1 scw /* XXX qmgr */
1361 1.1 scw for (i = 0; i < dma->nbuf; i++) {
1362 1.1 scw struct npebuf *npe = &dma->buf[i];
1363 1.1 scw
1364 1.1 scw if (npe->ix_m != NULL) {
1365 1.1 scw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1366 1.1 scw m_freem(npe->ix_m);
1367 1.1 scw npe->ix_m = NULL;
1368 1.1 scw }
1369 1.1 scw }
1370 1.1 scw }
1371 1.1 scw
1372 1.1 scw /*
1373 1.1 scw * Turn off interrupts, and stop the nic.
1374 1.1 scw */
1375 1.1 scw void
1376 1.1 scw npestop(struct ifnet *ifp, int disable)
1377 1.1 scw {
1378 1.1 scw struct npe_softc *sc = ifp->if_softc;
1379 1.1 scw
1380 1.39 msaitoh /* Disable transmitter and reciver in the MAC */
1381 1.39 msaitoh WR4(sc, NPE_MAC_RX_CNTRL1,
1382 1.1 scw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1383 1.39 msaitoh WR4(sc, NPE_MAC_TX_CNTRL1,
1384 1.1 scw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1385 1.1 scw
1386 1.1 scw callout_stop(&sc->sc_tick_ch);
1387 1.1 scw
1388 1.1 scw npe_stopxmit(sc);
1389 1.1 scw npe_stoprecv(sc);
1390 1.1 scw /* XXX go into loopback & drain q's? */
1391 1.1 scw /* XXX but beware of disabling tx above */
1392 1.1 scw
1393 1.1 scw /*
1394 1.1 scw * The MAC core rx/tx disable may leave the MAC hardware in an
1395 1.39 msaitoh * unpredictable state. A hw reset is executed before resetting
1396 1.1 scw * all the MAC parameters to a known value.
1397 1.1 scw */
1398 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1399 1.1 scw DELAY(NPE_MAC_RESET_DELAY);
1400 1.1 scw WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1401 1.1 scw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1402 1.13 msaitoh
1403 1.13 msaitoh ifp->if_timer = 0;
1404 1.13 msaitoh ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1405 1.1 scw }
1406 1.1 scw
1407 1.1 scw void
1408 1.1 scw npewatchdog(struct ifnet *ifp)
1409 1.1 scw {
1410 1.1 scw struct npe_softc *sc = ifp->if_softc;
1411 1.1 scw int s;
1412 1.1 scw
1413 1.23 matt aprint_error_dev(sc->sc_dev, "device timeout\n");
1414 1.1 scw s = splnet();
1415 1.1 scw ifp->if_oerrors++;
1416 1.1 scw npeinit_locked(sc);
1417 1.1 scw splx(s);
1418 1.1 scw }
1419 1.1 scw
1420 1.1 scw static int
1421 1.3 christos npeioctl(struct ifnet *ifp, u_long cmd, void *data)
1422 1.1 scw {
1423 1.1 scw struct npe_softc *sc = ifp->if_softc;
1424 1.13 msaitoh struct ifreq *ifr = (struct ifreq *) data;
1425 1.1 scw int s, error = 0;
1426 1.1 scw
1427 1.1 scw s = splnet();
1428 1.1 scw
1429 1.13 msaitoh switch (cmd) {
1430 1.13 msaitoh case SIOCSIFMEDIA:
1431 1.13 msaitoh #if 0 /* not yet */
1432 1.13 msaitoh /* Flow control requires full-duplex mode. */
1433 1.13 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1434 1.13 msaitoh (ifr->ifr_media & IFM_FDX) == 0)
1435 1.13 msaitoh ifr->ifr_media &= ~IFM_ETH_FMASK;
1436 1.13 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1437 1.13 msaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1438 1.13 msaitoh /* We can do both TXPAUSE and RXPAUSE. */
1439 1.13 msaitoh ifr->ifr_media |=
1440 1.13 msaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1441 1.13 msaitoh }
1442 1.13 msaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1443 1.13 msaitoh }
1444 1.13 msaitoh #endif
1445 1.13 msaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1446 1.13 msaitoh break;
1447 1.13 msaitoh case SIOCSIFFLAGS:
1448 1.40 msaitoh if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) {
1449 1.13 msaitoh /*
1450 1.13 msaitoh * If interface is marked down and it is running,
1451 1.13 msaitoh * then stop and disable it.
1452 1.13 msaitoh */
1453 1.13 msaitoh (*ifp->if_stop)(ifp, 1);
1454 1.40 msaitoh } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) {
1455 1.13 msaitoh /*
1456 1.13 msaitoh * If interface is marked up and it is stopped, then
1457 1.13 msaitoh * start it.
1458 1.13 msaitoh */
1459 1.13 msaitoh error = (*ifp->if_init)(ifp);
1460 1.13 msaitoh } else if ((ifp->if_flags & IFF_UP) != 0) {
1461 1.13 msaitoh int diff;
1462 1.13 msaitoh
1463 1.13 msaitoh /* Up (AND RUNNING). */
1464 1.13 msaitoh
1465 1.13 msaitoh diff = (ifp->if_flags ^ sc->sc_if_flags)
1466 1.40 msaitoh & (IFF_PROMISC | IFF_ALLMULTI);
1467 1.40 msaitoh if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1468 1.13 msaitoh /*
1469 1.13 msaitoh * If the difference bettween last flag and
1470 1.13 msaitoh * new flag only IFF_PROMISC or IFF_ALLMULTI,
1471 1.13 msaitoh * set multicast filter only (don't reset to
1472 1.13 msaitoh * prevent link down).
1473 1.13 msaitoh */
1474 1.13 msaitoh npe_setmcast(sc);
1475 1.13 msaitoh } else {
1476 1.13 msaitoh /*
1477 1.13 msaitoh * Reset the interface to pick up changes in
1478 1.13 msaitoh * any other flags that affect the hardware
1479 1.13 msaitoh * state.
1480 1.13 msaitoh */
1481 1.13 msaitoh error = (*ifp->if_init)(ifp);
1482 1.13 msaitoh }
1483 1.13 msaitoh }
1484 1.13 msaitoh sc->sc_if_flags = ifp->if_flags;
1485 1.13 msaitoh break;
1486 1.13 msaitoh default:
1487 1.13 msaitoh error = ether_ioctl(ifp, cmd, data);
1488 1.13 msaitoh if (error == ENETRESET) {
1489 1.13 msaitoh /*
1490 1.13 msaitoh * Multicast list has changed; set the hardware filter
1491 1.13 msaitoh * accordingly.
1492 1.13 msaitoh */
1493 1.13 msaitoh npe_setmcast(sc);
1494 1.13 msaitoh error = 0;
1495 1.1 scw }
1496 1.1 scw }
1497 1.1 scw
1498 1.1 scw npestart(ifp);
1499 1.1 scw
1500 1.1 scw splx(s);
1501 1.1 scw return error;
1502 1.1 scw }
1503 1.1 scw
1504 1.1 scw /*
1505 1.1 scw * Setup a traffic class -> rx queue mapping.
1506 1.1 scw */
1507 1.1 scw static int
1508 1.1 scw npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1509 1.1 scw {
1510 1.1 scw int npeid = npeconfig[sc->sc_unit].npeid;
1511 1.1 scw uint32_t msg[2];
1512 1.1 scw
1513 1.15 msaitoh msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20)
1514 1.15 msaitoh | classix;
1515 1.1 scw msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1516 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1517 1.1 scw }
1518 1.1 scw
1519 1.1 scw /*
1520 1.1 scw * Update and reset the statistics in the NPE.
1521 1.1 scw */
1522 1.1 scw static int
1523 1.1 scw npe_updatestats(struct npe_softc *sc)
1524 1.1 scw {
1525 1.1 scw uint32_t msg[2];
1526 1.1 scw
1527 1.1 scw msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1528 1.1 scw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1529 1.1 scw return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */
1530 1.1 scw }
1531 1.1 scw
1532 1.1 scw #if 0
1533 1.1 scw /*
1534 1.1 scw * Get the current statistics block.
1535 1.1 scw */
1536 1.1 scw static int
1537 1.1 scw npe_getstats(struct npe_softc *sc)
1538 1.1 scw {
1539 1.1 scw uint32_t msg[2];
1540 1.1 scw
1541 1.1 scw msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1542 1.1 scw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1543 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1544 1.1 scw }
1545 1.1 scw
1546 1.1 scw /*
1547 1.1 scw * Query the image id of the loaded firmware.
1548 1.1 scw */
1549 1.1 scw static uint32_t
1550 1.1 scw npe_getimageid(struct npe_softc *sc)
1551 1.1 scw {
1552 1.1 scw uint32_t msg[2];
1553 1.1 scw
1554 1.1 scw msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1555 1.1 scw msg[1] = 0;
1556 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1557 1.1 scw }
1558 1.1 scw
1559 1.1 scw /*
1560 1.1 scw * Enable/disable loopback.
1561 1.1 scw */
1562 1.1 scw static int
1563 1.1 scw npe_setloopback(struct npe_softc *sc, int ena)
1564 1.1 scw {
1565 1.1 scw uint32_t msg[2];
1566 1.1 scw
1567 1.1 scw msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1568 1.1 scw msg[1] = 0;
1569 1.1 scw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1570 1.1 scw }
1571 1.1 scw #endif
1572 1.1 scw
1573 1.1 scw /*
1574 1.1 scw * MII bus support routines.
1575 1.1 scw *
1576 1.1 scw * NB: ixp425 has one PHY per NPE
1577 1.1 scw */
1578 1.1 scw static uint32_t
1579 1.1 scw npe_mii_mdio_read(struct npe_softc *sc, int reg)
1580 1.1 scw {
1581 1.1 scw #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1582 1.1 scw uint32_t v;
1583 1.1 scw
1584 1.1 scw /* NB: registers are known to be sequential */
1585 1.1 scw v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1586 1.1 scw v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1587 1.1 scw v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1588 1.1 scw v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1589 1.1 scw return v;
1590 1.1 scw #undef MII_RD4
1591 1.1 scw }
1592 1.1 scw
1593 1.1 scw static void
1594 1.1 scw npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1595 1.1 scw {
1596 1.1 scw #define MII_WR4(sc, reg, v) \
1597 1.1 scw bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1598 1.1 scw
1599 1.1 scw /* NB: registers are known to be sequential */
1600 1.1 scw MII_WR4(sc, reg+0, cmd & 0xff);
1601 1.1 scw MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1602 1.1 scw MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1603 1.1 scw MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1604 1.1 scw #undef MII_WR4
1605 1.1 scw }
1606 1.1 scw
1607 1.1 scw static int
1608 1.1 scw npe_mii_mdio_wait(struct npe_softc *sc)
1609 1.1 scw {
1610 1.1 scw #define MAXTRIES 100 /* XXX */
1611 1.1 scw uint32_t v;
1612 1.1 scw int i;
1613 1.1 scw
1614 1.1 scw for (i = 0; i < MAXTRIES; i++) {
1615 1.1 scw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1616 1.1 scw if ((v & NPE_MII_GO) == 0)
1617 1.36 msaitoh return 0;
1618 1.1 scw }
1619 1.36 msaitoh return ETIMEDOUT;
1620 1.1 scw #undef MAXTRIES
1621 1.1 scw }
1622 1.1 scw
1623 1.1 scw static int
1624 1.36 msaitoh npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val)
1625 1.1 scw {
1626 1.23 matt struct npe_softc *sc = device_private(self);
1627 1.1 scw uint32_t v;
1628 1.1 scw
1629 1.1 scw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1630 1.36 msaitoh return -1;
1631 1.1 scw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1632 1.1 scw | NPE_MII_GO;
1633 1.1 scw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1634 1.36 msaitoh if (npe_mii_mdio_wait(sc) == 0)
1635 1.1 scw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1636 1.1 scw else
1637 1.1 scw v = 0xffff | NPE_MII_READ_FAIL;
1638 1.36 msaitoh
1639 1.36 msaitoh if ((v & NPE_MII_READ_FAIL) != 0)
1640 1.36 msaitoh return -1;
1641 1.36 msaitoh
1642 1.36 msaitoh *val = v & 0xffff;
1643 1.36 msaitoh return 0;
1644 1.1 scw #undef MAXTRIES
1645 1.1 scw }
1646 1.1 scw
1647 1.36 msaitoh static int
1648 1.36 msaitoh npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val)
1649 1.1 scw {
1650 1.23 matt struct npe_softc *sc = device_private(self);
1651 1.1 scw uint32_t v;
1652 1.1 scw
1653 1.1 scw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1654 1.36 msaitoh return -1;
1655 1.1 scw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1656 1.36 msaitoh | val | NPE_MII_WRITE
1657 1.1 scw | NPE_MII_GO;
1658 1.1 scw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1659 1.36 msaitoh
1660 1.36 msaitoh return npe_mii_mdio_wait(sc);
1661 1.1 scw }
1662 1.1 scw
1663 1.1 scw static void
1664 1.23 matt npe_miibus_statchg(struct ifnet *ifp)
1665 1.1 scw {
1666 1.23 matt struct npe_softc *sc = ifp->if_softc;
1667 1.1 scw uint32_t tx1, rx1;
1668 1.16 msaitoh uint32_t randoff;
1669 1.1 scw
1670 1.39 msaitoh /* Sync MAC duplex state */
1671 1.1 scw tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1672 1.1 scw rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1673 1.1 scw if (sc->sc_mii.mii_media_active & IFM_FDX) {
1674 1.16 msaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
1675 1.1 scw tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1676 1.1 scw rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1677 1.1 scw } else {
1678 1.16 msaitoh struct timeval now;
1679 1.16 msaitoh getmicrotime(&now);
1680 1.16 msaitoh randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec)
1681 1.16 msaitoh & 0x7f;
1682 1.16 msaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT
1683 1.16 msaitoh + randoff);
1684 1.1 scw tx1 |= NPE_TX_CNTRL1_DUPLEX;
1685 1.1 scw rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1686 1.1 scw }
1687 1.1 scw WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1688 1.1 scw WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1689 1.1 scw }
1690