ixp425_if_npe.c revision 1.1
1 /* $NetBSD: ixp425_if_npe.c,v 1.1 2006/12/10 10:01:49 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.1 2006/12/10 10:01:49 scw Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include "bpfilter.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/device.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/socket.h> 60 #include <sys/endian.h> 61 #include <sys/ioctl.h> 62 63 #include <machine/bus.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <arm/xscale/ixp425reg.h> 75 #include <arm/xscale/ixp425var.h> 76 #include <arm/xscale/ixp425_qmgr.h> 77 #include <arm/xscale/ixp425_npevar.h> 78 #include <arm/xscale/ixp425_if_npereg.h> 79 80 #include <dev/mii/miivar.h> 81 82 #include "locators.h" 83 84 struct npebuf { 85 struct npebuf *ix_next; /* chain to next buffer */ 86 void *ix_m; /* backpointer to mbuf */ 87 bus_dmamap_t ix_map; /* bus dma map for associated data */ 88 struct npehwbuf *ix_hw; /* associated h/w block */ 89 uint32_t ix_neaddr; /* phys address of ix_hw */ 90 }; 91 92 struct npedma { 93 const char* name; 94 int nbuf; /* # npebuf's allocated */ 95 bus_dmamap_t m_map; 96 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 97 bus_dmamap_t buf_map; 98 bus_addr_t buf_phys; /* phys addr of buffers */ 99 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 100 }; 101 102 struct npe_softc { 103 struct device sc_dev; 104 struct ethercom sc_ethercom; 105 struct mii_data sc_mii; 106 bus_space_tag_t sc_iot; 107 bus_dma_tag_t sc_dt; 108 bus_space_handle_t sc_ioh; /* MAC register window */ 109 bus_space_handle_t sc_miih; /* MII register window */ 110 struct ixpnpe_softc *sc_npe; /* NPE support */ 111 int sc_unit; 112 int sc_phy; 113 struct callout sc_tick_ch; /* Tick callout */ 114 struct npedma txdma; 115 struct npebuf *tx_free; /* list of free tx buffers */ 116 struct npedma rxdma; 117 int rx_qid; /* rx qid */ 118 int rx_freeqid; /* rx free buffers qid */ 119 int tx_qid; /* tx qid */ 120 int tx_doneqid; /* tx completed qid */ 121 struct npestats *sc_stats; 122 bus_dmamap_t sc_stats_map; 123 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 124 }; 125 126 /* 127 * Per-unit static configuration for IXP425. The tx and 128 * rx free Q id's are fixed by the NPE microcode. The 129 * rx Q id's are programmed to be separate to simplify 130 * multi-port processing. It may be better to handle 131 * all traffic through one Q (as done by the Intel drivers). 132 * 133 * Note that the PHY's are accessible only from MAC A 134 * on the IXP425. This and other platform-specific 135 * assumptions probably need to be handled through hints. 136 */ 137 static const struct { 138 const char *desc; /* device description */ 139 int npeid; /* NPE assignment */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .imageid = IXP425_NPE_B_IMAGEID, 153 .regbase = IXP425_MAC_A_HWBASE, 154 .regsize = IXP425_MAC_A_SIZE, 155 .miibase = IXP425_MAC_A_HWBASE, 156 .miisize = IXP425_MAC_A_SIZE, 157 .rx_qid = 4, 158 .rx_freeqid = 27, 159 .tx_qid = 24, 160 .tx_doneqid = 31 161 }, 162 { .desc = "IXP NPE-C", 163 .npeid = NPE_C, 164 .imageid = IXP425_NPE_C_IMAGEID, 165 .regbase = IXP425_MAC_B_HWBASE, 166 .regsize = IXP425_MAC_B_SIZE, 167 .miibase = IXP425_MAC_A_HWBASE, 168 .miisize = IXP425_MAC_A_SIZE, 169 .rx_qid = 12, 170 .rx_freeqid = 28, 171 .tx_qid = 25, 172 .tx_doneqid = 31 173 }, 174 }; 175 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 176 177 static __inline uint32_t 178 RD4(struct npe_softc *sc, bus_size_t off) 179 { 180 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 181 } 182 183 static __inline void 184 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 185 { 186 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 187 } 188 189 static int npe_activate(struct npe_softc *); 190 #if 0 191 static void npe_deactivate(struct npe_softc *); 192 #endif 193 static int npe_ifmedia_change(struct ifnet *ifp); 194 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 195 static void npe_setmac(struct npe_softc *sc, u_char *eaddr); 196 static void npe_getmac(struct npe_softc *sc, u_char *eaddr); 197 static void npe_txdone(int qid, void *arg); 198 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 199 struct mbuf *); 200 static void npe_rxdone(int qid, void *arg); 201 static int npeinit(struct ifnet *); 202 static void npestart(struct ifnet *); 203 static void npestop(struct ifnet *, int); 204 static void npewatchdog(struct ifnet *); 205 static int npeioctl(struct ifnet * ifp, u_long, caddr_t); 206 207 static int npe_setrxqosentry(struct npe_softc *, int classix, 208 int trafclass, int qid); 209 static int npe_updatestats(struct npe_softc *); 210 #if 0 211 static int npe_getstats(struct npe_softc *); 212 static uint32_t npe_getimageid(struct npe_softc *); 213 static int npe_setloopback(struct npe_softc *, int ena); 214 #endif 215 216 static int npe_miibus_readreg(struct device *, int, int); 217 static void npe_miibus_writereg(struct device *, int, int, int); 218 static void npe_miibus_statchg(struct device *); 219 220 static int npe_debug; 221 #define DPRINTF(sc, fmt, ...) do { \ 222 if (npe_debug) printf(fmt, __VA_ARGS__); \ 223 } while (0) 224 #define DPRINTFn(n, sc, fmt, ...) do { \ 225 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 228 #define NPE_TXBUF 128 229 #define NPE_RXBUF 64 230 231 #ifndef ETHER_ALIGN 232 #define ETHER_ALIGN 2 /* XXX: Ditch this */ 233 #endif 234 235 /* NB: all tx done processing goes through one queue */ 236 static int tx_doneqid = -1; 237 238 static int npe_match(struct device *, struct cfdata *, void *); 239 static void npe_attach(struct device *, struct device *, void *); 240 241 CFATTACH_DECL(npe, sizeof(struct npe_softc), 242 npe_match, npe_attach, NULL, NULL); 243 244 static int 245 npe_match(struct device *parent, struct cfdata *cf, void *arg) 246 { 247 struct ixpnpe_attach_args *na = arg; 248 249 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 250 } 251 252 static void 253 npe_attach(struct device *parent, struct device *self, void *arg) 254 { 255 struct npe_softc *sc = (void *)self; 256 struct ixpnpe_attach_args *na = arg; 257 struct ifnet *ifp; 258 u_char eaddr[6]; 259 260 aprint_naive("\n"); 261 aprint_normal(": Ethernet co-processor\n"); 262 263 sc->sc_iot = na->na_iot; 264 sc->sc_dt = na->na_dt; 265 sc->sc_npe = na->na_npe; 266 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 267 sc->sc_phy = na->na_phy; 268 269 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 270 memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 271 272 callout_init(&sc->sc_tick_ch); 273 274 if (npe_activate(sc)) { 275 aprint_error("%s: Failed to activate NPE (missing " 276 "microcode?)\n", sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* 281 * XXXSCW: This is bogus - the NPE may not have been configured for 282 * XXXSCW: Ethernet yet. We must check for a property set by 283 * XXXSCW: board-specific code. 284 */ 285 npe_getmac(sc, eaddr); 286 287 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 288 ether_sprintf(eaddr)); 289 290 ifp = &sc->sc_ethercom.ec_if; 291 ifmedia_init(&sc->sc_mii.mii_media, 0, npe_ifmedia_change, 292 npe_ifmedia_status); 293 294 if (sc->sc_phy != IXPNPECF_PHY_DEFAULT) { 295 sc->sc_mii.mii_ifp = ifp; 296 sc->sc_mii.mii_readreg = npe_miibus_readreg; 297 sc->sc_mii.mii_writereg = npe_miibus_writereg; 298 sc->sc_mii.mii_statchg = npe_miibus_statchg; 299 300 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 301 (sc->sc_phy > IXPNPECF_PHY_DEFAULT) ? 302 sc->sc_phy : MII_PHY_ANY, 303 MII_OFFSET_ANY, MIIF_NOISOLATE); 304 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 305 } else { 306 /* Assume direct connection to a 100mbit switch */ 307 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX, 0,0); 308 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX); 309 } 310 311 ifp->if_softc = sc; 312 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 313 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 314 ifp->if_start = npestart; 315 ifp->if_ioctl = npeioctl; 316 ifp->if_watchdog = npewatchdog; 317 ifp->if_init = npeinit; 318 ifp->if_stop = npestop; 319 IFQ_SET_READY(&ifp->if_snd); 320 321 if_attach(ifp); 322 ether_ifattach(ifp, eaddr); 323 } 324 325 /* 326 * Compute and install the multicast filter. 327 */ 328 static void 329 npe_setmcast(struct npe_softc *sc) 330 { 331 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 332 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 333 int i; 334 335 if (ifp->if_flags & IFF_PROMISC) { 336 memset(mask, 0, ETHER_ADDR_LEN); 337 memset(addr, 0, ETHER_ADDR_LEN); 338 } else if (ifp->if_flags & IFF_ALLMULTI) { 339 static const uint8_t allmulti[ETHER_ADDR_LEN] = 340 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 341 all_multi: 342 memcpy(mask, allmulti, ETHER_ADDR_LEN); 343 memcpy(addr, allmulti, ETHER_ADDR_LEN); 344 } else { 345 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 346 struct ether_multistep step; 347 struct ether_multi *enm; 348 349 memset(clr, 0, ETHER_ADDR_LEN); 350 memset(set, 0xff, ETHER_ADDR_LEN); 351 352 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 353 while (enm != NULL) { 354 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 355 ifp->if_flags |= IFF_ALLMULTI; 356 goto all_multi; 357 } 358 359 for (i = 0; i < ETHER_ADDR_LEN; i++) { 360 clr[i] |= enm->enm_addrlo[i]; 361 set[i] &= enm->enm_addrlo[i]; 362 } 363 364 ETHER_NEXT_MULTI(step, enm); 365 } 366 367 for (i = 0; i < ETHER_ADDR_LEN; i++) { 368 mask[i] = set[i] | ~clr[i]; 369 addr[i] = set[i]; 370 } 371 } 372 373 /* 374 * Write the mask and address registers. 375 */ 376 for (i = 0; i < ETHER_ADDR_LEN; i++) { 377 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 378 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 379 } 380 } 381 382 static int 383 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 384 const char *name, int nbuf, int maxseg) 385 { 386 bus_dma_segment_t seg; 387 int rseg, error, i; 388 caddr_t hwbuf; 389 size_t size; 390 391 memset(dma, 0, sizeof(dma)); 392 393 dma->name = name; 394 dma->nbuf = nbuf; 395 396 size = nbuf * sizeof(struct npehwbuf); 397 398 /* XXX COHERENT for now */ 399 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 400 1, &rseg, BUS_DMA_NOWAIT); 401 if (error) { 402 printf("%s: unable to allocate memory for %s h/w buffers, " 403 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 404 } 405 406 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 407 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 408 if (error) { 409 printf("%s: unable to map memory for %s h/w buffers, " 410 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 411 free_dmamem: 412 bus_dmamem_free(sc->sc_dt, &seg, rseg); 413 return error; 414 } 415 dma->hwbuf = (void *)hwbuf; 416 417 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 418 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 419 if (error) { 420 printf("%s: unable to create map for %s h/w buffers, " 421 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 422 unmap_dmamem: 423 dma->hwbuf = NULL; 424 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 425 goto free_dmamem; 426 } 427 428 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 429 BUS_DMA_NOWAIT); 430 if (error) { 431 printf("%s: unable to load map for %s h/w buffers, " 432 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 433 destroy_dmamap: 434 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 435 goto unmap_dmamem; 436 } 437 438 /* XXX M_TEMP */ 439 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 440 if (dma->buf == NULL) { 441 printf("%s: unable to allocate memory for %s s/w buffers\n", 442 sc->sc_dev.dv_xname, dma->name); 443 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 444 error = ENOMEM; 445 goto destroy_dmamap; 446 } 447 448 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 449 for (i = 0; i < dma->nbuf; i++) { 450 struct npebuf *npe = &dma->buf[i]; 451 struct npehwbuf *hw = &dma->hwbuf[i]; 452 453 /* calculate offset to shared area */ 454 npe->ix_neaddr = dma->buf_phys + 455 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 456 KASSERT((npe->ix_neaddr & 0x1f) == 0); 457 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, 1, 458 MCLBYTES, 0, 0, &npe->ix_map); 459 if (error != 0) { 460 printf("%s: unable to create dmamap for %s buffer %u, " 461 "error %u\n", sc->sc_dev.dv_xname, dma->name, i, 462 error); 463 /* XXXSCW: Free up maps... */ 464 return error; 465 } 466 npe->ix_hw = hw; 467 } 468 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 469 BUS_DMASYNC_PREWRITE); 470 return 0; 471 } 472 473 #if 0 474 static void 475 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 476 { 477 int i; 478 479 /* XXXSCW: Clean this up */ 480 481 if (dma->hwbuf != NULL) { 482 for (i = 0; i < dma->nbuf; i++) { 483 struct npebuf *npe = &dma->buf[i]; 484 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 485 } 486 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 487 bus_dmamem_free(sc->sc_dt, (caddr_t)dma->hwbuf, dma->buf_map); 488 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 489 } 490 if (dma->buf != NULL) 491 free(dma->buf, M_TEMP); 492 memset(dma, 0, sizeof(*dma)); 493 } 494 #endif 495 496 static int 497 npe_activate(struct npe_softc *sc) 498 { 499 bus_dma_segment_t seg; 500 int unit = sc->sc_unit; 501 int error, i, rseg; 502 caddr_t statbuf; 503 504 /* load NPE firmware and start it running */ 505 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 506 if (error != 0) 507 return error; 508 509 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 510 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 511 printf("%s: Cannot map registers 0x%x:0x%x\n", 512 sc->sc_dev.dv_xname, npeconfig[unit].regbase, 513 npeconfig[unit].regsize); 514 return ENOMEM; 515 } 516 517 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 518 /* 519 * The PHY's are only accessible from one MAC (it appears) 520 * so for other MAC's setup an additional mapping for 521 * frobbing the PHY registers. 522 */ 523 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 524 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 525 printf("%s: Cannot map MII registers 0x%x:0x%x\n", 526 sc->sc_dev.dv_xname, npeconfig[unit].miibase, 527 npeconfig[unit].miisize); 528 return ENOMEM; 529 } 530 } else 531 sc->sc_miih = sc->sc_ioh; 532 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 533 if (error != 0) 534 return error; 535 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 536 if (error != 0) 537 return error; 538 539 /* setup statistics block */ 540 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 541 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 542 if (error) { 543 printf("%s: unable to allocate memory for stats block, " 544 "error %u\n", sc->sc_dev.dv_xname, error); 545 return error; 546 } 547 548 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 549 &statbuf, BUS_DMA_NOWAIT); 550 if (error) { 551 printf("%s: unable to map memory for stats block, " 552 "error %u\n", sc->sc_dev.dv_xname, error); 553 return error; 554 } 555 sc->sc_stats = (void *)statbuf; 556 557 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 558 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 559 &sc->sc_stats_map); 560 if (error) { 561 printf("%s: unable to create map for stats block, " 562 "error %u\n", sc->sc_dev.dv_xname, error); 563 return error; 564 } 565 566 if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 567 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) { 568 printf("%s: unable to load memory for stats block, error %u\n", 569 sc->sc_dev.dv_xname, error); 570 return error; 571 } 572 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 573 574 /* XXX disable half-bridge LEARNING+FILTERING feature */ 575 576 /* 577 * Setup h/w rx/tx queues. There are four q's: 578 * rx inbound q of rx'd frames 579 * rx_free pool of ixpbuf's for receiving frames 580 * tx outbound q of frames to send 581 * tx_done q of tx frames that have been processed 582 * 583 * The NPE handles the actual tx/rx process and the q manager 584 * handles the queues. The driver just writes entries to the 585 * q manager mailbox's and gets callbacks when there are rx'd 586 * frames to process or tx'd frames to reap. These callbacks 587 * are controlled by the q configurations; e.g. we get a 588 * callback when tx_done has 2 or more frames to process and 589 * when the rx q has at least one frame. These setings can 590 * changed at the time the q is configured. 591 */ 592 sc->rx_qid = npeconfig[unit].rx_qid; 593 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 594 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 595 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 596 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 597 /* tell the NPE to direct all traffic to rx_qid */ 598 #if 0 599 for (i = 0; i < 8; i++) 600 #else 601 printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname); 602 for (i = 0; i < 4; i++) 603 #endif 604 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 605 606 sc->tx_qid = npeconfig[unit].tx_qid; 607 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 608 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 609 if (tx_doneqid == -1) { 610 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 611 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 612 tx_doneqid = sc->tx_doneqid; 613 } 614 615 KASSERT(npes[npeconfig[unit].npeid] == NULL); 616 npes[npeconfig[unit].npeid] = sc; 617 618 return 0; 619 } 620 621 #if 0 622 static void 623 npe_deactivate(struct npe_softc *sc); 624 { 625 int unit = sc->sc_unit; 626 627 npes[npeconfig[unit].npeid] = NULL; 628 629 /* XXX disable q's */ 630 if (sc->sc_npe != NULL) 631 ixpnpe_stop(sc->sc_npe); 632 if (sc->sc_stats != NULL) { 633 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 634 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 635 sc->sc_stats_map); 636 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 637 } 638 if (sc->sc_stats_tag != NULL) 639 bus_dma_tag_destroy(sc->sc_stats_tag); 640 npe_dma_destroy(sc, &sc->txdma); 641 npe_dma_destroy(sc, &sc->rxdma); 642 bus_generic_detach(sc->sc_dev); 643 if (sc->sc_mii) 644 device_delete_child(sc->sc_dev, sc->sc_mii); 645 #if 0 646 /* XXX sc_ioh and sc_miih */ 647 if (sc->mem_res) 648 bus_release_resource(dev, SYS_RES_IOPORT, 649 rman_get_rid(sc->mem_res), sc->mem_res); 650 sc->mem_res = 0; 651 #endif 652 } 653 #endif 654 655 /* 656 * Change media according to request. 657 */ 658 static int 659 npe_ifmedia_change(struct ifnet *ifp) 660 { 661 struct npe_softc *sc = ifp->if_softc; 662 663 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && ifp->if_flags & IFF_UP) 664 mii_mediachg(&sc->sc_mii); 665 return (0); 666 } 667 668 /* 669 * Notify the world which media we're using. 670 */ 671 static void 672 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 673 { 674 struct npe_softc *sc = ifp->if_softc; 675 676 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 677 mii_pollstat(&sc->sc_mii); 678 679 ifmr->ifm_active = sc->sc_mii.mii_media_active; 680 ifmr->ifm_status = sc->sc_mii.mii_media_status; 681 } 682 683 static void 684 npe_addstats(struct npe_softc *sc) 685 { 686 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 687 struct npestats *ns = sc->sc_stats; 688 689 ifp->if_oerrors += 690 be32toh(ns->dot3StatsInternalMacTransmitErrors) 691 + be32toh(ns->dot3StatsCarrierSenseErrors) 692 + be32toh(ns->TxVLANIdFilterDiscards) 693 ; 694 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 695 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 696 + be32toh(ns->RxOverrunDiscards) 697 + be32toh(ns->RxUnderflowEntryDiscards) 698 ; 699 ifp->if_collisions += 700 be32toh(ns->dot3StatsSingleCollisionFrames) 701 + be32toh(ns->dot3StatsMultipleCollisionFrames) 702 ; 703 } 704 705 static void 706 npe_tick(void *xsc) 707 { 708 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 709 struct npe_softc *sc = xsc; 710 uint32_t msg[2]; 711 712 /* 713 * NB: to avoid sleeping with the softc lock held we 714 * split the NPE msg processing into two parts. The 715 * request for statistics is sent w/o waiting for a 716 * reply and then on the next tick we retrieve the 717 * results. This works because npe_tick is the only 718 * code that talks via the mailbox's (except at setup). 719 * This likely can be handled better. 720 */ 721 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 722 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 723 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 724 npe_addstats(sc); 725 } 726 npe_updatestats(sc); 727 mii_tick(&sc->sc_mii); 728 729 /* schedule next poll */ 730 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 731 #undef ACK 732 } 733 734 static void 735 npe_setmac(struct npe_softc *sc, u_char *eaddr) 736 { 737 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 738 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 739 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 740 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 741 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 742 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 743 744 } 745 746 static void 747 npe_getmac(struct npe_softc *sc, u_char *eaddr) 748 { 749 /* NB: the unicast address appears to be loaded from EEPROM on reset */ 750 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 751 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 752 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 753 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 754 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 755 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 756 } 757 758 struct txdone { 759 struct npebuf *head; 760 struct npebuf **tail; 761 int count; 762 }; 763 764 static __inline void 765 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 766 { 767 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 768 769 *td->tail = sc->tx_free; 770 sc->tx_free = td->head; 771 /* 772 * We're no longer busy, so clear the busy flag and call the 773 * start routine to xmit more packets. 774 */ 775 ifp->if_opackets += td->count; 776 ifp->if_flags &= ~IFF_OACTIVE; 777 ifp->if_timer = 0; 778 npestart(ifp); 779 } 780 781 /* 782 * Q manager callback on tx done queue. Reap mbufs 783 * and return tx buffers to the free list. Finally 784 * restart output. Note the microcode has only one 785 * txdone q wired into it so we must use the NPE ID 786 * returned with each npehwbuf to decide where to 787 * send buffers. 788 */ 789 static void 790 npe_txdone(int qid, void *arg) 791 { 792 #define P2V(a, dma) \ 793 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 794 struct npe_softc *sc; 795 struct npebuf *npe; 796 struct txdone *td, q[NPE_MAX]; 797 uint32_t entry; 798 799 /* XXX no NPE-A support */ 800 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 801 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 802 /* XXX max # at a time? */ 803 while (ixpqmgr_qread(qid, &entry) == 0) { 804 sc = npes[NPE_QM_Q_NPE(entry)]; 805 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 806 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 807 808 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 809 m_freem(npe->ix_m); 810 npe->ix_m = NULL; 811 812 td = &q[NPE_QM_Q_NPE(entry)]; 813 *td->tail = npe; 814 td->tail = &npe->ix_next; 815 td->count++; 816 } 817 818 if (q[NPE_B].count) 819 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 820 if (q[NPE_C].count) 821 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 822 #undef P2V 823 } 824 825 static __inline struct mbuf * 826 npe_getcl(void) 827 { 828 struct mbuf *m; 829 830 MGETHDR(m, M_DONTWAIT, MT_DATA); 831 if (m != NULL) { 832 MCLGET(m, M_DONTWAIT); 833 if ((m->m_flags & M_EXT) == 0) { 834 m_freem(m); 835 m = NULL; 836 } 837 } 838 return (m); 839 } 840 841 static int 842 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 843 { 844 struct npehwbuf *hw; 845 int error; 846 847 if (m == NULL) { 848 m = npe_getcl(); 849 if (m == NULL) 850 return ENOBUFS; 851 } 852 KASSERT(m->m_ext.ext_size >= (1536 + ETHER_ALIGN)); 853 m->m_pkthdr.len = m->m_len = 1536; 854 /* backload payload and align ip hdr */ 855 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 856 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 857 BUS_DMA_READ|BUS_DMA_NOWAIT); 858 if (error != 0) { 859 m_freem(m); 860 return error; 861 } 862 hw = npe->ix_hw; 863 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 864 /* NB: NPE requires length be a multiple of 64 */ 865 /* NB: buffer length is shifted in word */ 866 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 867 hw->ix_ne[0].next = 0; 868 npe->ix_m = m; 869 /* Flush the memory in the mbuf */ 870 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 871 BUS_DMASYNC_PREREAD); 872 return 0; 873 } 874 875 /* 876 * RX q processing for a specific NPE. Claim entries 877 * from the hardware queue and pass the frames up the 878 * stack. Pass the rx buffers to the free list. 879 */ 880 static void 881 npe_rxdone(int qid, void *arg) 882 { 883 #define P2V(a, dma) \ 884 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 885 struct npe_softc *sc = arg; 886 struct npedma *dma = &sc->rxdma; 887 uint32_t entry; 888 889 while (ixpqmgr_qread(qid, &entry) == 0) { 890 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 891 struct mbuf *m; 892 893 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 894 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 895 /* 896 * Allocate a new mbuf to replenish the rx buffer. 897 * If doing so fails we drop the rx'd frame so we 898 * can reuse the previous mbuf. When we're able to 899 * allocate a new mbuf dispatch the mbuf w/ rx'd 900 * data up the stack and replace it with the newly 901 * allocated one. 902 */ 903 m = npe_getcl(); 904 if (m != NULL) { 905 struct mbuf *mrx = npe->ix_m; 906 struct npehwbuf *hw = npe->ix_hw; 907 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 908 909 /* Flush mbuf memory for rx'd data */ 910 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 911 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 912 913 /* XXX flush hw buffer; works now 'cuz coherent */ 914 /* set m_len etc. per rx frame size */ 915 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 916 mrx->m_pkthdr.len = mrx->m_len; 917 mrx->m_pkthdr.rcvif = ifp; 918 mrx->m_flags |= M_HASFCS; 919 920 ifp->if_ipackets++; 921 ifp->if_input(ifp, mrx); 922 } else { 923 /* discard frame and re-use mbuf */ 924 m = npe->ix_m; 925 } 926 if (npe_rxbuf_init(sc, npe, m) == 0) { 927 /* return npe buf to rx free list */ 928 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 929 } else { 930 /* XXX should not happen */ 931 } 932 } 933 #undef P2V 934 } 935 936 static void 937 npe_startxmit(struct npe_softc *sc) 938 { 939 struct npedma *dma = &sc->txdma; 940 int i; 941 942 sc->tx_free = NULL; 943 for (i = 0; i < dma->nbuf; i++) { 944 struct npebuf *npe = &dma->buf[i]; 945 if (npe->ix_m != NULL) { 946 /* NB: should not happen */ 947 printf("%s: %s: free mbuf at entry %u\n", 948 sc->sc_dev.dv_xname, __func__, i); 949 m_freem(npe->ix_m); 950 } 951 npe->ix_m = NULL; 952 npe->ix_next = sc->tx_free; 953 sc->tx_free = npe; 954 } 955 } 956 957 static void 958 npe_startrecv(struct npe_softc *sc) 959 { 960 struct npedma *dma = &sc->rxdma; 961 struct npebuf *npe; 962 int i; 963 964 for (i = 0; i < dma->nbuf; i++) { 965 npe = &dma->buf[i]; 966 npe_rxbuf_init(sc, npe, npe->ix_m); 967 /* set npe buf on rx free list */ 968 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 969 } 970 } 971 972 /* 973 * Reset and initialize the chip 974 */ 975 static void 976 npeinit_locked(void *xsc) 977 { 978 struct npe_softc *sc = xsc; 979 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 980 981 if (ifp->if_flags & IFF_RUNNING) return;/*XXX*/ 982 983 /* 984 * Reset MAC core. 985 */ 986 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 987 DELAY(NPE_MAC_RESET_DELAY); 988 /* configure MAC to generate MDC clock */ 989 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 990 991 /* disable transmitter and reciver in the MAC */ 992 WR4(sc, NPE_MAC_RX_CNTRL1, 993 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 994 WR4(sc, NPE_MAC_TX_CNTRL1, 995 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 996 997 /* 998 * Set the MAC core registers. 999 */ 1000 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1001 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1002 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1003 /* thresholds determined by NPE firmware FS */ 1004 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1005 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1006 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1007 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1008 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1009 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1010 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1011 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1012 1013 WR4(sc, NPE_MAC_TX_CNTRL1, 1014 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1015 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1016 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1017 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1018 /* XXX pad strip? */ 1019 WR4(sc, NPE_MAC_RX_CNTRL1, 1020 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1021 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1022 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1023 1024 npe_setmac(sc, LLADDR(ifp->if_sadl)); 1025 npe_setmcast(sc); 1026 1027 npe_startxmit(sc); 1028 npe_startrecv(sc); 1029 1030 ifp->if_flags |= IFF_RUNNING; 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 ifp->if_timer = 0; /* just in case */ 1033 1034 /* enable transmitter and reciver in the MAC */ 1035 WR4(sc, NPE_MAC_RX_CNTRL1, 1036 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1037 WR4(sc, NPE_MAC_TX_CNTRL1, 1038 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1039 1040 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1041 } 1042 1043 static int 1044 npeinit(struct ifnet *ifp) 1045 { 1046 struct npe_softc *sc = ifp->if_softc; 1047 int s; 1048 1049 s = splnet(); 1050 npeinit_locked(sc); 1051 splx(s); 1052 1053 return (0); 1054 } 1055 1056 /* 1057 * Defragment an mbuf chain, returning at most maxfrags separate 1058 * mbufs+clusters. If this is not possible NULL is returned and 1059 * the original mbuf chain is left in it's present (potentially 1060 * modified) state. We use two techniques: collapsing consecutive 1061 * mbufs and replacing consecutive mbufs by a cluster. 1062 */ 1063 static __inline struct mbuf * 1064 npe_defrag(struct mbuf *m0) 1065 { 1066 struct mbuf *m; 1067 1068 MGETHDR(m, M_DONTWAIT, MT_DATA); 1069 if (m == NULL) 1070 return (NULL); 1071 M_COPY_PKTHDR(m, m0); 1072 1073 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1074 MCLGET(m, M_DONTWAIT); 1075 if ((m->m_flags & M_EXT) == 0) { 1076 m_freem(m); 1077 return (NULL); 1078 } 1079 } 1080 1081 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1082 m_freem(m0); 1083 1084 return (m); 1085 } 1086 1087 /* 1088 * Dequeue packets and place on the h/w transmit queue. 1089 */ 1090 static void 1091 npestart(struct ifnet *ifp) 1092 { 1093 struct npe_softc *sc = ifp->if_softc; 1094 struct npebuf *npe; 1095 struct npehwbuf *hw; 1096 struct mbuf *m, *n; 1097 bus_dma_segment_t *segs; 1098 int nseg, len, error, i; 1099 uint32_t next; 1100 1101 /* XXX can this happen? */ 1102 if (ifp->if_flags & IFF_OACTIVE) 1103 return; 1104 1105 while (sc->tx_free != NULL) { 1106 IFQ_DEQUEUE(&ifp->if_snd, m); 1107 if (m == NULL) { 1108 /* XXX? */ 1109 ifp->if_flags &= ~IFF_OACTIVE; 1110 return; 1111 } 1112 npe = sc->tx_free; 1113 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1114 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1115 if (error == EFBIG) { 1116 n = npe_defrag(m); 1117 if (n == NULL) { 1118 printf("%s: %s: too many fragments\n", 1119 sc->sc_dev.dv_xname, __func__); 1120 m_freem(m); 1121 return; /* XXX? */ 1122 } 1123 m = n; 1124 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1125 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1126 } 1127 if (error != 0) { 1128 printf("%s: %s: error %u\n", 1129 sc->sc_dev.dv_xname, __func__, error); 1130 m_freem(m); 1131 return; /* XXX? */ 1132 } 1133 sc->tx_free = npe->ix_next; 1134 1135 #if NBPFILTER > 0 1136 /* 1137 * Tap off here if there is a bpf listener. 1138 */ 1139 if (__predict_false(ifp->if_bpf)) 1140 bpf_mtap(ifp->if_bpf, m); 1141 #endif 1142 1143 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1144 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1145 1146 npe->ix_m = m; 1147 hw = npe->ix_hw; 1148 len = m->m_pkthdr.len; 1149 nseg = npe->ix_map->dm_nsegs; 1150 segs = npe->ix_map->dm_segs; 1151 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1152 for (i = 0; i < nseg; i++) { 1153 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1154 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1155 hw->ix_ne[i].next = htobe32(next); 1156 1157 len = 0; /* zero for segments > 1 */ 1158 next += sizeof(hw->ix_ne[0]); 1159 } 1160 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1161 /* XXX flush descriptor instead of using uncached memory */ 1162 1163 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1164 __func__, sc->tx_qid, npe->ix_neaddr, 1165 hw->ix_ne[0].data, hw->ix_ne[0].len); 1166 /* stick it on the tx q */ 1167 /* XXX add vlan priority */ 1168 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1169 1170 ifp->if_timer = 5; 1171 } 1172 if (sc->tx_free == NULL) 1173 ifp->if_flags |= IFF_OACTIVE; 1174 } 1175 1176 static void 1177 npe_stopxmit(struct npe_softc *sc) 1178 { 1179 struct npedma *dma = &sc->txdma; 1180 int i; 1181 1182 /* XXX qmgr */ 1183 for (i = 0; i < dma->nbuf; i++) { 1184 struct npebuf *npe = &dma->buf[i]; 1185 1186 if (npe->ix_m != NULL) { 1187 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1188 m_freem(npe->ix_m); 1189 npe->ix_m = NULL; 1190 } 1191 } 1192 } 1193 1194 static void 1195 npe_stoprecv(struct npe_softc *sc) 1196 { 1197 struct npedma *dma = &sc->rxdma; 1198 int i; 1199 1200 /* XXX qmgr */ 1201 for (i = 0; i < dma->nbuf; i++) { 1202 struct npebuf *npe = &dma->buf[i]; 1203 1204 if (npe->ix_m != NULL) { 1205 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1206 m_freem(npe->ix_m); 1207 npe->ix_m = NULL; 1208 } 1209 } 1210 } 1211 1212 /* 1213 * Turn off interrupts, and stop the nic. 1214 */ 1215 void 1216 npestop(struct ifnet *ifp, int disable) 1217 { 1218 struct npe_softc *sc = ifp->if_softc; 1219 1220 /* disable transmitter and reciver in the MAC */ 1221 WR4(sc, NPE_MAC_RX_CNTRL1, 1222 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1223 WR4(sc, NPE_MAC_TX_CNTRL1, 1224 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1225 1226 ifp->if_timer = 0; 1227 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1228 1229 callout_stop(&sc->sc_tick_ch); 1230 1231 npe_stopxmit(sc); 1232 npe_stoprecv(sc); 1233 /* XXX go into loopback & drain q's? */ 1234 /* XXX but beware of disabling tx above */ 1235 1236 /* 1237 * The MAC core rx/tx disable may leave the MAC hardware in an 1238 * unpredictable state. A hw reset is executed before resetting 1239 * all the MAC parameters to a known value. 1240 */ 1241 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1242 DELAY(NPE_MAC_RESET_DELAY); 1243 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1244 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1245 } 1246 1247 void 1248 npewatchdog(struct ifnet *ifp) 1249 { 1250 struct npe_softc *sc = ifp->if_softc; 1251 int s; 1252 1253 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1254 s = splnet(); 1255 ifp->if_oerrors++; 1256 npeinit_locked(sc); 1257 splx(s); 1258 } 1259 1260 static int 1261 npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1262 { 1263 struct npe_softc *sc = ifp->if_softc; 1264 struct ifreq *ifr = (struct ifreq *)data; 1265 int s, error = 0; 1266 1267 s = splnet(); 1268 1269 switch (cmd) { 1270 case SIOCSIFMEDIA: 1271 case SIOCGIFMEDIA: 1272 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1273 break; 1274 1275 default: 1276 error = ether_ioctl(ifp, cmd, data); 1277 if (error == ENETRESET) { 1278 if ((ifp->if_flags & IFF_UP) == 0 && 1279 ifp->if_flags & IFF_RUNNING) { 1280 ifp->if_flags &= ~IFF_RUNNING; 1281 npestop(&sc->sc_ethercom.ec_if, 0); 1282 } else { 1283 /* reinitialize card on any parameter change */ 1284 npeinit_locked(sc); 1285 } 1286 error = 0; 1287 } 1288 break; 1289 } 1290 1291 npestart(ifp); 1292 1293 splx(s); 1294 return error; 1295 } 1296 1297 /* 1298 * Setup a traffic class -> rx queue mapping. 1299 */ 1300 static int 1301 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1302 { 1303 int npeid = npeconfig[sc->sc_unit].npeid; 1304 uint32_t msg[2]; 1305 1306 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix; 1307 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1308 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1309 } 1310 1311 /* 1312 * Update and reset the statistics in the NPE. 1313 */ 1314 static int 1315 npe_updatestats(struct npe_softc *sc) 1316 { 1317 uint32_t msg[2]; 1318 1319 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1320 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1321 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1322 } 1323 1324 #if 0 1325 /* 1326 * Get the current statistics block. 1327 */ 1328 static int 1329 npe_getstats(struct npe_softc *sc) 1330 { 1331 uint32_t msg[2]; 1332 1333 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1334 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1335 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1336 } 1337 1338 /* 1339 * Query the image id of the loaded firmware. 1340 */ 1341 static uint32_t 1342 npe_getimageid(struct npe_softc *sc) 1343 { 1344 uint32_t msg[2]; 1345 1346 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1347 msg[1] = 0; 1348 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1349 } 1350 1351 /* 1352 * Enable/disable loopback. 1353 */ 1354 static int 1355 npe_setloopback(struct npe_softc *sc, int ena) 1356 { 1357 uint32_t msg[2]; 1358 1359 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1360 msg[1] = 0; 1361 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1362 } 1363 #endif 1364 1365 /* 1366 * MII bus support routines. 1367 * 1368 * NB: ixp425 has one PHY per NPE 1369 */ 1370 static uint32_t 1371 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1372 { 1373 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1374 uint32_t v; 1375 1376 /* NB: registers are known to be sequential */ 1377 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1378 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1379 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1380 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1381 return v; 1382 #undef MII_RD4 1383 } 1384 1385 static void 1386 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1387 { 1388 #define MII_WR4(sc, reg, v) \ 1389 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1390 1391 /* NB: registers are known to be sequential */ 1392 MII_WR4(sc, reg+0, cmd & 0xff); 1393 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1394 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1395 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1396 #undef MII_WR4 1397 } 1398 1399 static int 1400 npe_mii_mdio_wait(struct npe_softc *sc) 1401 { 1402 #define MAXTRIES 100 /* XXX */ 1403 uint32_t v; 1404 int i; 1405 1406 for (i = 0; i < MAXTRIES; i++) { 1407 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1408 if ((v & NPE_MII_GO) == 0) 1409 return 1; 1410 } 1411 return 0; /* NB: timeout */ 1412 #undef MAXTRIES 1413 } 1414 1415 static int 1416 npe_miibus_readreg(struct device *self, int phy, int reg) 1417 { 1418 struct npe_softc *sc = (void *)self; 1419 uint32_t v; 1420 1421 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1422 return 0xffff; 1423 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1424 | NPE_MII_GO; 1425 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1426 if (npe_mii_mdio_wait(sc)) { 1427 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1428 else 1429 v = 0xffff | NPE_MII_READ_FAIL; 1430 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1431 #undef MAXTRIES 1432 } 1433 1434 static void 1435 npe_miibus_writereg(struct device *self, int phy, int reg, int data) 1436 { 1437 struct npe_softc *sc = (void *)self; 1438 uint32_t v; 1439 1440 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1441 return; 1442 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1443 | data | NPE_MII_WRITE 1444 | NPE_MII_GO; 1445 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1446 /* XXX complain about timeout */ 1447 (void) npe_mii_mdio_wait(sc); 1448 } 1449 1450 static void 1451 npe_miibus_statchg(struct device *self) 1452 { 1453 struct npe_softc *sc = (void *)self; 1454 uint32_t tx1, rx1; 1455 1456 /* sync MAC duplex state */ 1457 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1458 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1459 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1460 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1461 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1462 } else { 1463 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1464 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1465 } 1466 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1467 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1468 } 1469
Indexes created Thu Oct 02 10:09:58 GMT 2025