ixp425_if_npe.c revision 1.13
1 /* $NetBSD: ixp425_if_npe.c,v 1.13 2009/03/11 12:16:12 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.13 2009/03/11 12:16:12 msaitoh Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include "bpfilter.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/device.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/socket.h> 60 #include <sys/endian.h> 61 #include <sys/ioctl.h> 62 #include <sys/syslog.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <arm/xscale/ixp425reg.h> 76 #include <arm/xscale/ixp425var.h> 77 #include <arm/xscale/ixp425_qmgr.h> 78 #include <arm/xscale/ixp425_npevar.h> 79 #include <arm/xscale/ixp425_if_npereg.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include "locators.h" 84 85 struct npebuf { 86 struct npebuf *ix_next; /* chain to next buffer */ 87 void *ix_m; /* backpointer to mbuf */ 88 bus_dmamap_t ix_map; /* bus dma map for associated data */ 89 struct npehwbuf *ix_hw; /* associated h/w block */ 90 uint32_t ix_neaddr; /* phys address of ix_hw */ 91 }; 92 93 struct npedma { 94 const char* name; 95 int nbuf; /* # npebuf's allocated */ 96 bus_dmamap_t m_map; 97 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 98 bus_dmamap_t buf_map; 99 bus_addr_t buf_phys; /* phys addr of buffers */ 100 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 101 }; 102 103 struct npe_softc { 104 struct device sc_dev; 105 struct ethercom sc_ethercom; 106 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 107 struct mii_data sc_mii; 108 bus_space_tag_t sc_iot; 109 bus_dma_tag_t sc_dt; 110 bus_space_handle_t sc_ioh; /* MAC register window */ 111 bus_space_handle_t sc_miih; /* MII register window */ 112 struct ixpnpe_softc *sc_npe; /* NPE support */ 113 int sc_unit; 114 int sc_phy; 115 struct callout sc_tick_ch; /* Tick callout */ 116 struct npedma txdma; 117 struct npebuf *tx_free; /* list of free tx buffers */ 118 struct npedma rxdma; 119 int rx_qid; /* rx qid */ 120 int rx_freeqid; /* rx free buffers qid */ 121 int tx_qid; /* tx qid */ 122 int tx_doneqid; /* tx completed qid */ 123 struct npestats *sc_stats; 124 bus_dmamap_t sc_stats_map; 125 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 126 int sc_if_flags; /* keep last if_flags */ 127 }; 128 129 /* 130 * Per-unit static configuration for IXP425. The tx and 131 * rx free Q id's are fixed by the NPE microcode. The 132 * rx Q id's are programmed to be separate to simplify 133 * multi-port processing. It may be better to handle 134 * all traffic through one Q (as done by the Intel drivers). 135 * 136 * Note that the PHY's are accessible only from MAC A 137 * on the IXP425. This and other platform-specific 138 * assumptions probably need to be handled through hints. 139 */ 140 static const struct { 141 const char *desc; /* device description */ 142 int npeid; /* NPE assignment */ 143 uint32_t imageid; /* NPE firmware image id */ 144 uint32_t regbase; 145 int regsize; 146 uint32_t miibase; 147 int miisize; 148 uint8_t rx_qid; 149 uint8_t rx_freeqid; 150 uint8_t tx_qid; 151 uint8_t tx_doneqid; 152 } npeconfig[NPE_PORTS_MAX] = { 153 { .desc = "IXP NPE-B", 154 .npeid = NPE_B, 155 .imageid = IXP425_NPE_B_IMAGEID, 156 .regbase = IXP425_MAC_A_HWBASE, 157 .regsize = IXP425_MAC_A_SIZE, 158 .miibase = IXP425_MAC_A_HWBASE, 159 .miisize = IXP425_MAC_A_SIZE, 160 .rx_qid = 4, 161 .rx_freeqid = 27, 162 .tx_qid = 24, 163 .tx_doneqid = 31 164 }, 165 { .desc = "IXP NPE-C", 166 .npeid = NPE_C, 167 .imageid = IXP425_NPE_C_IMAGEID, 168 .regbase = IXP425_MAC_B_HWBASE, 169 .regsize = IXP425_MAC_B_SIZE, 170 .miibase = IXP425_MAC_A_HWBASE, 171 .miisize = IXP425_MAC_A_SIZE, 172 .rx_qid = 12, 173 .rx_freeqid = 28, 174 .tx_qid = 25, 175 .tx_doneqid = 31 176 }, 177 }; 178 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 179 180 static __inline uint32_t 181 RD4(struct npe_softc *sc, bus_size_t off) 182 { 183 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 184 } 185 186 static __inline void 187 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 188 { 189 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 190 } 191 192 static int npe_activate(struct npe_softc *); 193 #if 0 194 static void npe_deactivate(struct npe_softc *); 195 #endif 196 static int npe_ifmedia_change(struct ifnet *ifp); 197 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 198 static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 199 static void npe_getmac(struct npe_softc *sc); 200 static void npe_txdone(int qid, void *arg); 201 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 202 struct mbuf *); 203 static void npe_rxdone(int qid, void *arg); 204 static void npeinit_macreg(struct npe_softc *); 205 static int npeinit(struct ifnet *); 206 static void npeinit_locked(void *); 207 static void npestart(struct ifnet *); 208 static void npestop(struct ifnet *, int); 209 static void npewatchdog(struct ifnet *); 210 static int npeioctl(struct ifnet * ifp, u_long, void *); 211 212 static int npe_setrxqosentry(struct npe_softc *, int classix, 213 int trafclass, int qid); 214 static int npe_updatestats(struct npe_softc *); 215 #if 0 216 static int npe_getstats(struct npe_softc *); 217 static uint32_t npe_getimageid(struct npe_softc *); 218 static int npe_setloopback(struct npe_softc *, int ena); 219 #endif 220 221 static int npe_miibus_readreg(struct device *, int, int); 222 static void npe_miibus_writereg(struct device *, int, int, int); 223 static void npe_miibus_statchg(struct device *); 224 225 static int npe_debug; 226 #define DPRINTF(sc, fmt, ...) do { \ 227 if (npe_debug) printf(fmt, __VA_ARGS__); \ 228 } while (0) 229 #define DPRINTFn(n, sc, fmt, ...) do { \ 230 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 231 } while (0) 232 233 #define NPE_TXBUF 128 234 #define NPE_RXBUF 64 235 236 #ifndef ETHER_ALIGN 237 #define ETHER_ALIGN 2 /* XXX: Ditch this */ 238 #endif 239 240 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 241 + ((uint64_t)addr[1] << 32) \ 242 + ((uint64_t)addr[2] << 24) \ 243 + ((uint64_t)addr[3] << 16) \ 244 + ((uint64_t)addr[4] << 8) \ 245 + (uint64_t)addr[5]) 246 247 /* NB: all tx done processing goes through one queue */ 248 static int tx_doneqid = -1; 249 250 void (*npe_getmac_md)(int, uint8_t *); 251 252 static int npe_match(struct device *, struct cfdata *, void *); 253 static void npe_attach(struct device *, struct device *, void *); 254 255 CFATTACH_DECL(npe, sizeof(struct npe_softc), 256 npe_match, npe_attach, NULL, NULL); 257 258 static int 259 npe_match(struct device *parent, struct cfdata *cf, void *arg) 260 { 261 struct ixpnpe_attach_args *na = arg; 262 263 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 264 } 265 266 static void 267 npe_attach(struct device *parent, struct device *self, void *arg) 268 { 269 struct npe_softc *sc = (void *)self; 270 struct ixpnpe_attach_args *na = arg; 271 struct ifnet *ifp; 272 273 aprint_naive("\n"); 274 aprint_normal(": Ethernet co-processor\n"); 275 276 sc->sc_iot = na->na_iot; 277 sc->sc_dt = na->na_dt; 278 sc->sc_npe = na->na_npe; 279 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 280 sc->sc_phy = na->na_phy; 281 282 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 283 memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 284 285 callout_init(&sc->sc_tick_ch, 0); 286 287 if (npe_activate(sc)) { 288 aprint_error("%s: Failed to activate NPE (missing " 289 "microcode?)\n", sc->sc_dev.dv_xname); 290 return; 291 } 292 293 npeinit_macreg(sc); 294 /* 295 * XXXSCW: This is bogus - the NPE may not have been configured for 296 * XXXSCW: Ethernet yet. We must check for a property set by 297 * XXXSCW: board-specific code. 298 */ 299 npe_getmac(sc); 300 301 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 302 ether_sprintf(sc->sc_enaddr)); 303 304 ifp = &sc->sc_ethercom.ec_if; 305 ifmedia_init(&sc->sc_mii.mii_media, 0, npe_ifmedia_change, 306 npe_ifmedia_status); 307 308 if (sc->sc_phy != IXPNPECF_PHY_DEFAULT) { 309 sc->sc_mii.mii_ifp = ifp; 310 sc->sc_mii.mii_readreg = npe_miibus_readreg; 311 sc->sc_mii.mii_writereg = npe_miibus_writereg; 312 sc->sc_mii.mii_statchg = npe_miibus_statchg; 313 sc->sc_ethercom.ec_mii = &sc->sc_mii; 314 315 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 316 (sc->sc_phy > IXPNPECF_PHY_DEFAULT) ? 317 sc->sc_phy : MII_PHY_ANY, 318 MII_OFFSET_ANY, MIIF_NOISOLATE); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 320 } else { 321 /* Assume direct connection to a 100mbit switch */ 322 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX, 0,0); 323 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX); 324 } 325 326 ifp->if_softc = sc; 327 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329 ifp->if_start = npestart; 330 ifp->if_ioctl = npeioctl; 331 ifp->if_watchdog = npewatchdog; 332 ifp->if_init = npeinit; 333 ifp->if_stop = npestop; 334 IFQ_SET_READY(&ifp->if_snd); 335 336 /* VLAN capable */ 337 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 338 339 if_attach(ifp); 340 ether_ifattach(ifp, sc->sc_enaddr); 341 } 342 343 /* 344 * Compute and install the multicast filter. 345 */ 346 static void 347 npe_setmcast(struct npe_softc *sc) 348 { 349 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 350 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 351 uint32_t reg; 352 int i; 353 354 /* Always use filter. Is here a correct position? */ 355 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 356 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 357 358 if (ifp->if_flags & IFF_PROMISC) { 359 memset(mask, 0, ETHER_ADDR_LEN); 360 memset(addr, 0, ETHER_ADDR_LEN); 361 } else if (ifp->if_flags & IFF_ALLMULTI) { 362 static const uint8_t allmulti[ETHER_ADDR_LEN] = 363 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 364 all_multi: 365 memcpy(mask, allmulti, ETHER_ADDR_LEN); 366 memcpy(addr, allmulti, ETHER_ADDR_LEN); 367 } else { 368 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 369 struct ether_multistep step; 370 struct ether_multi *enm; 371 372 memset(clr, 0, ETHER_ADDR_LEN); 373 memset(set, 0xff, ETHER_ADDR_LEN); 374 375 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 376 while (enm != NULL) { 377 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 goto all_multi; 380 } 381 382 for (i = 0; i < ETHER_ADDR_LEN; i++) { 383 clr[i] |= enm->enm_addrlo[i]; 384 set[i] &= enm->enm_addrlo[i]; 385 } 386 387 ETHER_NEXT_MULTI(step, enm); 388 } 389 390 for (i = 0; i < ETHER_ADDR_LEN; i++) { 391 mask[i] = set[i] | ~clr[i]; 392 addr[i] = set[i]; 393 } 394 } 395 396 /* 397 * Write the mask and address registers. 398 */ 399 for (i = 0; i < ETHER_ADDR_LEN; i++) { 400 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 401 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 402 } 403 } 404 405 static int 406 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 407 const char *name, int nbuf, int maxseg) 408 { 409 bus_dma_segment_t seg; 410 int rseg, error, i; 411 void *hwbuf; 412 size_t size; 413 414 memset(dma, 0, sizeof(*dma)); 415 416 dma->name = name; 417 dma->nbuf = nbuf; 418 419 size = nbuf * sizeof(struct npehwbuf); 420 421 /* XXX COHERENT for now */ 422 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 423 1, &rseg, BUS_DMA_NOWAIT); 424 if (error) { 425 printf("%s: unable to allocate memory for %s h/w buffers, " 426 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 427 } 428 429 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 430 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 431 if (error) { 432 printf("%s: unable to map memory for %s h/w buffers, " 433 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 434 free_dmamem: 435 bus_dmamem_free(sc->sc_dt, &seg, rseg); 436 return error; 437 } 438 dma->hwbuf = (void *)hwbuf; 439 440 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 441 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 442 if (error) { 443 printf("%s: unable to create map for %s h/w buffers, " 444 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 445 unmap_dmamem: 446 dma->hwbuf = NULL; 447 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 448 goto free_dmamem; 449 } 450 451 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 452 BUS_DMA_NOWAIT); 453 if (error) { 454 printf("%s: unable to load map for %s h/w buffers, " 455 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 456 destroy_dmamap: 457 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 458 goto unmap_dmamem; 459 } 460 461 /* XXX M_TEMP */ 462 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 463 if (dma->buf == NULL) { 464 printf("%s: unable to allocate memory for %s s/w buffers\n", 465 sc->sc_dev.dv_xname, dma->name); 466 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 467 error = ENOMEM; 468 goto destroy_dmamap; 469 } 470 471 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 472 for (i = 0; i < dma->nbuf; i++) { 473 struct npebuf *npe = &dma->buf[i]; 474 struct npehwbuf *hw = &dma->hwbuf[i]; 475 476 /* calculate offset to shared area */ 477 npe->ix_neaddr = dma->buf_phys + 478 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 479 KASSERT((npe->ix_neaddr & 0x1f) == 0); 480 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 481 MCLBYTES, 0, 0, &npe->ix_map); 482 if (error != 0) { 483 printf("%s: unable to create dmamap for %s buffer %u, " 484 "error %u\n", sc->sc_dev.dv_xname, dma->name, i, 485 error); 486 /* XXXSCW: Free up maps... */ 487 return error; 488 } 489 npe->ix_hw = hw; 490 } 491 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 492 BUS_DMASYNC_PREWRITE); 493 return 0; 494 } 495 496 #if 0 497 static void 498 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 499 { 500 int i; 501 502 /* XXXSCW: Clean this up */ 503 504 if (dma->hwbuf != NULL) { 505 for (i = 0; i < dma->nbuf; i++) { 506 struct npebuf *npe = &dma->buf[i]; 507 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 508 } 509 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 510 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 511 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 512 } 513 if (dma->buf != NULL) 514 free(dma->buf, M_TEMP); 515 memset(dma, 0, sizeof(*dma)); 516 } 517 #endif 518 519 static int 520 npe_activate(struct npe_softc *sc) 521 { 522 bus_dma_segment_t seg; 523 int unit = sc->sc_unit; 524 int error, i, rseg; 525 void *statbuf; 526 527 /* load NPE firmware and start it running */ 528 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 529 if (error != 0) 530 return error; 531 532 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 533 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 534 printf("%s: Cannot map registers 0x%x:0x%x\n", 535 sc->sc_dev.dv_xname, npeconfig[unit].regbase, 536 npeconfig[unit].regsize); 537 return ENOMEM; 538 } 539 540 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 541 /* 542 * The PHY's are only accessible from one MAC (it appears) 543 * so for other MAC's setup an additional mapping for 544 * frobbing the PHY registers. 545 */ 546 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 547 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 548 printf("%s: Cannot map MII registers 0x%x:0x%x\n", 549 sc->sc_dev.dv_xname, npeconfig[unit].miibase, 550 npeconfig[unit].miisize); 551 return ENOMEM; 552 } 553 } else 554 sc->sc_miih = sc->sc_ioh; 555 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 556 if (error != 0) 557 return error; 558 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 559 if (error != 0) 560 return error; 561 562 /* setup statistics block */ 563 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 564 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 565 if (error) { 566 printf("%s: unable to allocate memory for stats block, " 567 "error %u\n", sc->sc_dev.dv_xname, error); 568 return error; 569 } 570 571 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 572 &statbuf, BUS_DMA_NOWAIT); 573 if (error) { 574 printf("%s: unable to map memory for stats block, " 575 "error %u\n", sc->sc_dev.dv_xname, error); 576 return error; 577 } 578 sc->sc_stats = (void *)statbuf; 579 580 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 581 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 582 &sc->sc_stats_map); 583 if (error) { 584 printf("%s: unable to create map for stats block, " 585 "error %u\n", sc->sc_dev.dv_xname, error); 586 return error; 587 } 588 589 if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 590 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) { 591 printf("%s: unable to load memory for stats block, error %u\n", 592 sc->sc_dev.dv_xname, error); 593 return error; 594 } 595 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 596 597 /* XXX disable half-bridge LEARNING+FILTERING feature */ 598 599 /* 600 * Setup h/w rx/tx queues. There are four q's: 601 * rx inbound q of rx'd frames 602 * rx_free pool of ixpbuf's for receiving frames 603 * tx outbound q of frames to send 604 * tx_done q of tx frames that have been processed 605 * 606 * The NPE handles the actual tx/rx process and the q manager 607 * handles the queues. The driver just writes entries to the 608 * q manager mailbox's and gets callbacks when there are rx'd 609 * frames to process or tx'd frames to reap. These callbacks 610 * are controlled by the q configurations; e.g. we get a 611 * callback when tx_done has 2 or more frames to process and 612 * when the rx q has at least one frame. These setings can 613 * changed at the time the q is configured. 614 */ 615 sc->rx_qid = npeconfig[unit].rx_qid; 616 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 617 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 618 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 619 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 620 /* tell the NPE to direct all traffic to rx_qid */ 621 #if 0 622 for (i = 0; i < 8; i++) 623 #else 624 printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname); 625 for (i = 0; i < 4; i++) 626 #endif 627 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 628 629 sc->tx_qid = npeconfig[unit].tx_qid; 630 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 631 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 632 if (tx_doneqid == -1) { 633 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 634 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 635 tx_doneqid = sc->tx_doneqid; 636 } 637 638 KASSERT(npes[npeconfig[unit].npeid] == NULL); 639 npes[npeconfig[unit].npeid] = sc; 640 641 return 0; 642 } 643 644 #if 0 645 static void 646 npe_deactivate(struct npe_softc *sc); 647 { 648 int unit = sc->sc_unit; 649 650 npes[npeconfig[unit].npeid] = NULL; 651 652 /* XXX disable q's */ 653 if (sc->sc_npe != NULL) 654 ixpnpe_stop(sc->sc_npe); 655 if (sc->sc_stats != NULL) { 656 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 657 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 658 sc->sc_stats_map); 659 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 660 } 661 if (sc->sc_stats_tag != NULL) 662 bus_dma_tag_destroy(sc->sc_stats_tag); 663 npe_dma_destroy(sc, &sc->txdma); 664 npe_dma_destroy(sc, &sc->rxdma); 665 bus_generic_detach(sc->sc_dev); 666 if (sc->sc_mii) 667 device_delete_child(sc->sc_dev, sc->sc_mii); 668 #if 0 669 /* XXX sc_ioh and sc_miih */ 670 if (sc->mem_res) 671 bus_release_resource(dev, SYS_RES_IOPORT, 672 rman_get_rid(sc->mem_res), sc->mem_res); 673 sc->mem_res = 0; 674 #endif 675 } 676 #endif 677 678 /* 679 * Change media according to request. 680 */ 681 static int 682 npe_ifmedia_change(struct ifnet *ifp) 683 { 684 struct npe_softc *sc = ifp->if_softc; 685 686 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 687 return ether_mediachange(ifp); 688 return 0; 689 } 690 691 /* 692 * Notify the world which media we're using. 693 */ 694 static void 695 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 696 { 697 struct npe_softc *sc = ifp->if_softc; 698 699 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 700 mii_pollstat(&sc->sc_mii); 701 702 ifmr->ifm_active = sc->sc_mii.mii_media_active; 703 ifmr->ifm_status = sc->sc_mii.mii_media_status; 704 } 705 706 static void 707 npe_addstats(struct npe_softc *sc) 708 { 709 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 710 struct npestats *ns = sc->sc_stats; 711 712 ifp->if_oerrors += 713 be32toh(ns->dot3StatsInternalMacTransmitErrors) 714 + be32toh(ns->dot3StatsCarrierSenseErrors) 715 + be32toh(ns->TxVLANIdFilterDiscards) 716 ; 717 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 718 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 719 + be32toh(ns->RxOverrunDiscards) 720 + be32toh(ns->RxUnderflowEntryDiscards) 721 ; 722 ifp->if_collisions += 723 be32toh(ns->dot3StatsSingleCollisionFrames) 724 + be32toh(ns->dot3StatsMultipleCollisionFrames) 725 ; 726 } 727 728 static void 729 npe_tick(void *xsc) 730 { 731 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 732 struct npe_softc *sc = xsc; 733 uint32_t msg[2]; 734 735 /* 736 * NB: to avoid sleeping with the softc lock held we 737 * split the NPE msg processing into two parts. The 738 * request for statistics is sent w/o waiting for a 739 * reply and then on the next tick we retrieve the 740 * results. This works because npe_tick is the only 741 * code that talks via the mailbox's (except at setup). 742 * This likely can be handled better. 743 */ 744 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 745 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 746 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 747 npe_addstats(sc); 748 } 749 npe_updatestats(sc); 750 mii_tick(&sc->sc_mii); 751 752 /* schedule next poll */ 753 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 754 #undef ACK 755 } 756 757 static void 758 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 759 { 760 761 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 762 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 763 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 764 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 765 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 766 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 767 } 768 769 static void 770 npe_getmac(struct npe_softc *sc) 771 { 772 uint8_t *eaddr = sc->sc_enaddr; 773 774 if (npe_getmac_md != NULL) { 775 (*npe_getmac_md)(sc->sc_dev.dv_unit, eaddr); 776 } else { 777 /* 778 * Some system's unicast address appears to be loaded from 779 * EEPROM on reset 780 */ 781 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 782 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 783 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 784 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 785 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 786 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 787 } 788 } 789 790 struct txdone { 791 struct npebuf *head; 792 struct npebuf **tail; 793 int count; 794 }; 795 796 static __inline void 797 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 798 { 799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 801 *td->tail = sc->tx_free; 802 sc->tx_free = td->head; 803 /* 804 * We're no longer busy, so clear the busy flag and call the 805 * start routine to xmit more packets. 806 */ 807 ifp->if_opackets += td->count; 808 ifp->if_flags &= ~IFF_OACTIVE; 809 ifp->if_timer = 0; 810 npestart(ifp); 811 } 812 813 /* 814 * Q manager callback on tx done queue. Reap mbufs 815 * and return tx buffers to the free list. Finally 816 * restart output. Note the microcode has only one 817 * txdone q wired into it so we must use the NPE ID 818 * returned with each npehwbuf to decide where to 819 * send buffers. 820 */ 821 static void 822 npe_txdone(int qid, void *arg) 823 { 824 #define P2V(a, dma) \ 825 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 826 struct npe_softc *sc; 827 struct npebuf *npe; 828 struct txdone *td, q[NPE_MAX]; 829 uint32_t entry; 830 831 /* XXX no NPE-A support */ 832 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 833 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 834 /* XXX max # at a time? */ 835 while (ixpqmgr_qread(qid, &entry) == 0) { 836 sc = npes[NPE_QM_Q_NPE(entry)]; 837 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 838 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 839 840 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 841 m_freem(npe->ix_m); 842 npe->ix_m = NULL; 843 844 td = &q[NPE_QM_Q_NPE(entry)]; 845 *td->tail = npe; 846 td->tail = &npe->ix_next; 847 td->count++; 848 } 849 850 if (q[NPE_B].count) 851 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 852 if (q[NPE_C].count) 853 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 854 #undef P2V 855 } 856 857 static __inline struct mbuf * 858 npe_getcl(void) 859 { 860 struct mbuf *m; 861 862 MGETHDR(m, M_DONTWAIT, MT_DATA); 863 if (m != NULL) { 864 MCLGET(m, M_DONTWAIT); 865 if ((m->m_flags & M_EXT) == 0) { 866 m_freem(m); 867 m = NULL; 868 } 869 } 870 return (m); 871 } 872 873 static int 874 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 875 { 876 struct npehwbuf *hw; 877 int error; 878 879 if (m == NULL) { 880 m = npe_getcl(); 881 if (m == NULL) 882 return ENOBUFS; 883 } 884 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 885 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 886 /* backload payload and align ip hdr */ 887 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 888 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 889 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 890 BUS_DMA_READ|BUS_DMA_NOWAIT); 891 if (error != 0) { 892 m_freem(m); 893 return error; 894 } 895 hw = npe->ix_hw; 896 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 897 /* NB: NPE requires length be a multiple of 64 */ 898 /* NB: buffer length is shifted in word */ 899 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 900 hw->ix_ne[0].next = 0; 901 npe->ix_m = m; 902 /* Flush the memory in the mbuf */ 903 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 904 BUS_DMASYNC_PREREAD); 905 return 0; 906 } 907 908 /* 909 * RX q processing for a specific NPE. Claim entries 910 * from the hardware queue and pass the frames up the 911 * stack. Pass the rx buffers to the free list. 912 */ 913 static void 914 npe_rxdone(int qid, void *arg) 915 { 916 #define P2V(a, dma) \ 917 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 918 struct npe_softc *sc = arg; 919 struct npedma *dma = &sc->rxdma; 920 uint32_t entry; 921 922 while (ixpqmgr_qread(qid, &entry) == 0) { 923 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 924 struct mbuf *m; 925 926 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 927 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 928 /* 929 * Allocate a new mbuf to replenish the rx buffer. 930 * If doing so fails we drop the rx'd frame so we 931 * can reuse the previous mbuf. When we're able to 932 * allocate a new mbuf dispatch the mbuf w/ rx'd 933 * data up the stack and replace it with the newly 934 * allocated one. 935 */ 936 m = npe_getcl(); 937 if (m != NULL) { 938 struct mbuf *mrx = npe->ix_m; 939 struct npehwbuf *hw = npe->ix_hw; 940 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 941 942 /* Flush mbuf memory for rx'd data */ 943 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 944 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 945 946 /* XXX flush hw buffer; works now 'cuz coherent */ 947 /* set m_len etc. per rx frame size */ 948 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 949 mrx->m_pkthdr.len = mrx->m_len; 950 mrx->m_pkthdr.rcvif = ifp; 951 /* Don't add M_HASFCS. See below */ 952 953 #if 1 954 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 955 log(LOG_INFO, "%s: too short frame (len=%d)\n", 956 sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 957 /* Back out "newly allocated" mbuf. */ 958 m_freem(m); 959 ifp->if_ierrors++; 960 goto fail; 961 } 962 if ((ifp->if_flags & IFF_PROMISC) == 0) { 963 struct ether_header *eh; 964 965 /* 966 * Workaround for "Non-Intel XScale Technology 967 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 968 * matches the filter (both unicast and 969 * multicast). 970 */ 971 eh = mtod(mrx, struct ether_header *); 972 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 973 /* unicast */ 974 975 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 976 /* discard it */ 977 #if 0 978 printf("discard it\n"); 979 #endif 980 /* 981 * Back out "newly allocated" 982 * mbuf. 983 */ 984 m_freem(m); 985 goto fail; 986 } 987 } else if (memcmp(eh->ether_dhost, 988 etherbroadcastaddr, 6) == 0) { 989 /* Always accept broadcast packet*/ 990 } else { 991 struct ethercom *ec = &sc->sc_ethercom; 992 struct ether_multi *enm; 993 struct ether_multistep step; 994 int match = 0; 995 996 /* multicast */ 997 998 ETHER_FIRST_MULTI(step, ec, enm); 999 while (enm != NULL) { 1000 uint64_t lowint, highint, dest; 1001 1002 lowint = MAC2UINT64(enm->enm_addrlo); 1003 highint = MAC2UINT64(enm->enm_addrhi); 1004 dest = MAC2UINT64(eh->ether_dhost); 1005 #if 0 1006 printf("%llx\n", lowint); 1007 printf("%llx\n", dest); 1008 printf("%llx\n", highint); 1009 #endif 1010 if ((lowint <= dest) && (dest <= highint)) { 1011 match = 1; 1012 break; 1013 } 1014 ETHER_NEXT_MULTI(step, enm); 1015 } 1016 if (match == 0) { 1017 /* discard it */ 1018 #if 0 1019 printf("discard it(M)\n"); 1020 #endif 1021 /* 1022 * Back out "newly allocated" 1023 * mbuf. 1024 */ 1025 m_freem(m); 1026 goto fail; 1027 } 1028 } 1029 } 1030 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1031 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1032 sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 1033 /* Back out "newly allocated" mbuf. */ 1034 m_freem(m); 1035 ifp->if_ierrors++; 1036 goto fail; 1037 } 1038 #endif 1039 1040 /* 1041 * Trim FCS! 1042 * NPE always adds the FCS by this driver's setting, 1043 * so we always trim it here and not add M_HASFCS. 1044 */ 1045 m_adj(mrx, -ETHER_CRC_LEN); 1046 1047 ifp->if_ipackets++; 1048 #if NBPFILTER > 0 1049 /* 1050 * Tap off here if there is a bpf listener. 1051 */ 1052 if (__predict_false(ifp->if_bpf)) 1053 bpf_mtap(ifp->if_bpf, mrx); 1054 #endif 1055 ifp->if_input(ifp, mrx); 1056 } else { 1057 fail: 1058 /* discard frame and re-use mbuf */ 1059 m = npe->ix_m; 1060 } 1061 if (npe_rxbuf_init(sc, npe, m) == 0) { 1062 /* return npe buf to rx free list */ 1063 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1064 } else { 1065 /* XXX should not happen */ 1066 } 1067 } 1068 #undef P2V 1069 } 1070 1071 static void 1072 npe_startxmit(struct npe_softc *sc) 1073 { 1074 struct npedma *dma = &sc->txdma; 1075 int i; 1076 1077 sc->tx_free = NULL; 1078 for (i = 0; i < dma->nbuf; i++) { 1079 struct npebuf *npe = &dma->buf[i]; 1080 if (npe->ix_m != NULL) { 1081 /* NB: should not happen */ 1082 printf("%s: %s: free mbuf at entry %u\n", 1083 sc->sc_dev.dv_xname, __func__, i); 1084 m_freem(npe->ix_m); 1085 } 1086 npe->ix_m = NULL; 1087 npe->ix_next = sc->tx_free; 1088 sc->tx_free = npe; 1089 } 1090 } 1091 1092 static void 1093 npe_startrecv(struct npe_softc *sc) 1094 { 1095 struct npedma *dma = &sc->rxdma; 1096 struct npebuf *npe; 1097 int i; 1098 1099 for (i = 0; i < dma->nbuf; i++) { 1100 npe = &dma->buf[i]; 1101 npe_rxbuf_init(sc, npe, npe->ix_m); 1102 /* set npe buf on rx free list */ 1103 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1104 } 1105 } 1106 1107 static void 1108 npeinit_macreg(struct npe_softc *sc) 1109 { 1110 1111 /* 1112 * Reset MAC core. 1113 */ 1114 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1115 DELAY(NPE_MAC_RESET_DELAY); 1116 /* configure MAC to generate MDC clock */ 1117 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1118 1119 /* disable transmitter and reciver in the MAC */ 1120 WR4(sc, NPE_MAC_RX_CNTRL1, 1121 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1122 WR4(sc, NPE_MAC_TX_CNTRL1, 1123 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1124 1125 /* 1126 * Set the MAC core registers. 1127 */ 1128 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1129 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1130 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1131 /* thresholds determined by NPE firmware FS */ 1132 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1133 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1134 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1135 /* tx fifo threshold (bytes) */ 1136 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1137 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1138 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1139 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1140 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1141 /* assumes MII mode */ 1142 WR4(sc, NPE_MAC_TX_CNTRL1, 1143 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1144 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1145 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1146 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1147 /* XXX pad strip? */ 1148 WR4(sc, NPE_MAC_RX_CNTRL1, 1149 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1150 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1151 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1152 } 1153 1154 /* 1155 * Reset and initialize the chip 1156 */ 1157 static void 1158 npeinit_locked(void *xsc) 1159 { 1160 struct npe_softc *sc = xsc; 1161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162 1163 /* Cancel any pending I/O. */ 1164 npestop(ifp, 0); 1165 1166 /* Reset the chip to a known state. */ 1167 npeinit_macreg(sc); 1168 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1169 npe_ifmedia_change(ifp); 1170 npe_setmcast(sc); 1171 1172 npe_startxmit(sc); 1173 npe_startrecv(sc); 1174 1175 ifp->if_flags |= IFF_RUNNING; 1176 ifp->if_flags &= ~IFF_OACTIVE; 1177 ifp->if_timer = 0; /* just in case */ 1178 1179 /* enable transmitter and reciver in the MAC */ 1180 WR4(sc, NPE_MAC_RX_CNTRL1, 1181 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1182 WR4(sc, NPE_MAC_TX_CNTRL1, 1183 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1184 1185 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1186 } 1187 1188 static int 1189 npeinit(struct ifnet *ifp) 1190 { 1191 struct npe_softc *sc = ifp->if_softc; 1192 int s; 1193 1194 s = splnet(); 1195 npeinit_locked(sc); 1196 splx(s); 1197 1198 return (0); 1199 } 1200 1201 /* 1202 * Defragment an mbuf chain, returning at most maxfrags separate 1203 * mbufs+clusters. If this is not possible NULL is returned and 1204 * the original mbuf chain is left in it's present (potentially 1205 * modified) state. We use two techniques: collapsing consecutive 1206 * mbufs and replacing consecutive mbufs by a cluster. 1207 */ 1208 static __inline struct mbuf * 1209 npe_defrag(struct mbuf *m0) 1210 { 1211 struct mbuf *m; 1212 1213 MGETHDR(m, M_DONTWAIT, MT_DATA); 1214 if (m == NULL) 1215 return (NULL); 1216 M_COPY_PKTHDR(m, m0); 1217 1218 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1219 MCLGET(m, M_DONTWAIT); 1220 if ((m->m_flags & M_EXT) == 0) { 1221 m_freem(m); 1222 return (NULL); 1223 } 1224 } 1225 1226 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1227 m_freem(m0); 1228 1229 return (m); 1230 } 1231 1232 /* 1233 * Dequeue packets and place on the h/w transmit queue. 1234 */ 1235 static void 1236 npestart(struct ifnet *ifp) 1237 { 1238 struct npe_softc *sc = ifp->if_softc; 1239 struct npebuf *npe; 1240 struct npehwbuf *hw; 1241 struct mbuf *m, *n; 1242 bus_dma_segment_t *segs; 1243 int nseg, len, error, i; 1244 uint32_t next; 1245 1246 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1247 return; 1248 1249 while (sc->tx_free != NULL) { 1250 IFQ_DEQUEUE(&ifp->if_snd, m); 1251 if (m == NULL) 1252 break; 1253 npe = sc->tx_free; 1254 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1255 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1256 if (error == EFBIG) { 1257 n = npe_defrag(m); 1258 if (n == NULL) { 1259 printf("%s: %s: too many fragments\n", 1260 sc->sc_dev.dv_xname, __func__); 1261 m_freem(m); 1262 return; /* XXX? */ 1263 } 1264 m = n; 1265 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1266 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1267 } 1268 if (error != 0) { 1269 printf("%s: %s: error %u\n", 1270 sc->sc_dev.dv_xname, __func__, error); 1271 m_freem(m); 1272 return; /* XXX? */ 1273 } 1274 sc->tx_free = npe->ix_next; 1275 1276 #if NBPFILTER > 0 1277 /* 1278 * Tap off here if there is a bpf listener. 1279 */ 1280 if (__predict_false(ifp->if_bpf)) 1281 bpf_mtap(ifp->if_bpf, m); 1282 #endif 1283 1284 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1285 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1286 1287 npe->ix_m = m; 1288 hw = npe->ix_hw; 1289 len = m->m_pkthdr.len; 1290 nseg = npe->ix_map->dm_nsegs; 1291 segs = npe->ix_map->dm_segs; 1292 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1293 for (i = 0; i < nseg; i++) { 1294 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1295 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1296 hw->ix_ne[i].next = htobe32(next); 1297 1298 len = 0; /* zero for segments > 1 */ 1299 next += sizeof(hw->ix_ne[0]); 1300 } 1301 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1302 /* XXX flush descriptor instead of using uncached memory */ 1303 1304 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1305 __func__, sc->tx_qid, npe->ix_neaddr, 1306 hw->ix_ne[0].data, hw->ix_ne[0].len); 1307 /* stick it on the tx q */ 1308 /* XXX add vlan priority */ 1309 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1310 1311 ifp->if_timer = 5; 1312 } 1313 if (sc->tx_free == NULL) 1314 ifp->if_flags |= IFF_OACTIVE; 1315 } 1316 1317 static void 1318 npe_stopxmit(struct npe_softc *sc) 1319 { 1320 struct npedma *dma = &sc->txdma; 1321 int i; 1322 1323 /* XXX qmgr */ 1324 for (i = 0; i < dma->nbuf; i++) { 1325 struct npebuf *npe = &dma->buf[i]; 1326 1327 if (npe->ix_m != NULL) { 1328 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1329 m_freem(npe->ix_m); 1330 npe->ix_m = NULL; 1331 } 1332 } 1333 } 1334 1335 static void 1336 npe_stoprecv(struct npe_softc *sc) 1337 { 1338 struct npedma *dma = &sc->rxdma; 1339 int i; 1340 1341 /* XXX qmgr */ 1342 for (i = 0; i < dma->nbuf; i++) { 1343 struct npebuf *npe = &dma->buf[i]; 1344 1345 if (npe->ix_m != NULL) { 1346 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1347 m_freem(npe->ix_m); 1348 npe->ix_m = NULL; 1349 } 1350 } 1351 } 1352 1353 /* 1354 * Turn off interrupts, and stop the nic. 1355 */ 1356 void 1357 npestop(struct ifnet *ifp, int disable) 1358 { 1359 struct npe_softc *sc = ifp->if_softc; 1360 1361 /* disable transmitter and reciver in the MAC */ 1362 WR4(sc, NPE_MAC_RX_CNTRL1, 1363 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1364 WR4(sc, NPE_MAC_TX_CNTRL1, 1365 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1366 1367 callout_stop(&sc->sc_tick_ch); 1368 1369 npe_stopxmit(sc); 1370 npe_stoprecv(sc); 1371 /* XXX go into loopback & drain q's? */ 1372 /* XXX but beware of disabling tx above */ 1373 1374 /* 1375 * The MAC core rx/tx disable may leave the MAC hardware in an 1376 * unpredictable state. A hw reset is executed before resetting 1377 * all the MAC parameters to a known value. 1378 */ 1379 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1380 DELAY(NPE_MAC_RESET_DELAY); 1381 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1382 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1383 1384 ifp->if_timer = 0; 1385 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1386 } 1387 1388 void 1389 npewatchdog(struct ifnet *ifp) 1390 { 1391 struct npe_softc *sc = ifp->if_softc; 1392 int s; 1393 1394 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1395 s = splnet(); 1396 ifp->if_oerrors++; 1397 npeinit_locked(sc); 1398 splx(s); 1399 } 1400 1401 static int 1402 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1403 { 1404 struct npe_softc *sc = ifp->if_softc; 1405 struct ifreq *ifr = (struct ifreq *) data; 1406 int s, error = 0; 1407 1408 s = splnet(); 1409 1410 switch (cmd) { 1411 case SIOCSIFMEDIA: 1412 case SIOCGIFMEDIA: 1413 #if 0 /* not yet */ 1414 /* Flow control requires full-duplex mode. */ 1415 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1416 (ifr->ifr_media & IFM_FDX) == 0) 1417 ifr->ifr_media &= ~IFM_ETH_FMASK; 1418 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1419 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1420 /* We can do both TXPAUSE and RXPAUSE. */ 1421 ifr->ifr_media |= 1422 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1423 } 1424 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1425 } 1426 #endif 1427 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1428 break; 1429 case SIOCSIFFLAGS: 1430 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) { 1431 /* 1432 * If interface is marked down and it is running, 1433 * then stop and disable it. 1434 */ 1435 (*ifp->if_stop)(ifp, 1); 1436 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) { 1437 /* 1438 * If interface is marked up and it is stopped, then 1439 * start it. 1440 */ 1441 error = (*ifp->if_init)(ifp); 1442 } else if ((ifp->if_flags & IFF_UP) != 0) { 1443 int diff; 1444 1445 /* Up (AND RUNNING). */ 1446 1447 diff = (ifp->if_flags ^ sc->sc_if_flags) 1448 & (IFF_PROMISC|IFF_ALLMULTI); 1449 if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 1450 /* 1451 * If the difference bettween last flag and 1452 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1453 * set multicast filter only (don't reset to 1454 * prevent link down). 1455 */ 1456 npe_setmcast(sc); 1457 } else { 1458 /* 1459 * Reset the interface to pick up changes in 1460 * any other flags that affect the hardware 1461 * state. 1462 */ 1463 error = (*ifp->if_init)(ifp); 1464 } 1465 } 1466 sc->sc_if_flags = ifp->if_flags; 1467 break; 1468 default: 1469 error = ether_ioctl(ifp, cmd, data); 1470 if (error == ENETRESET) { 1471 /* 1472 * Multicast list has changed; set the hardware filter 1473 * accordingly. 1474 */ 1475 npe_setmcast(sc); 1476 error = 0; 1477 } 1478 } 1479 1480 npestart(ifp); 1481 1482 splx(s); 1483 return error; 1484 } 1485 1486 /* 1487 * Setup a traffic class -> rx queue mapping. 1488 */ 1489 static int 1490 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1491 { 1492 int npeid = npeconfig[sc->sc_unit].npeid; 1493 uint32_t msg[2]; 1494 1495 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix; 1496 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1497 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1498 } 1499 1500 /* 1501 * Update and reset the statistics in the NPE. 1502 */ 1503 static int 1504 npe_updatestats(struct npe_softc *sc) 1505 { 1506 uint32_t msg[2]; 1507 1508 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1509 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1510 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1511 } 1512 1513 #if 0 1514 /* 1515 * Get the current statistics block. 1516 */ 1517 static int 1518 npe_getstats(struct npe_softc *sc) 1519 { 1520 uint32_t msg[2]; 1521 1522 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1523 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1524 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1525 } 1526 1527 /* 1528 * Query the image id of the loaded firmware. 1529 */ 1530 static uint32_t 1531 npe_getimageid(struct npe_softc *sc) 1532 { 1533 uint32_t msg[2]; 1534 1535 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1536 msg[1] = 0; 1537 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1538 } 1539 1540 /* 1541 * Enable/disable loopback. 1542 */ 1543 static int 1544 npe_setloopback(struct npe_softc *sc, int ena) 1545 { 1546 uint32_t msg[2]; 1547 1548 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1549 msg[1] = 0; 1550 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1551 } 1552 #endif 1553 1554 /* 1555 * MII bus support routines. 1556 * 1557 * NB: ixp425 has one PHY per NPE 1558 */ 1559 static uint32_t 1560 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1561 { 1562 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1563 uint32_t v; 1564 1565 /* NB: registers are known to be sequential */ 1566 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1567 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1568 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1569 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1570 return v; 1571 #undef MII_RD4 1572 } 1573 1574 static void 1575 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1576 { 1577 #define MII_WR4(sc, reg, v) \ 1578 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1579 1580 /* NB: registers are known to be sequential */ 1581 MII_WR4(sc, reg+0, cmd & 0xff); 1582 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1583 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1584 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1585 #undef MII_WR4 1586 } 1587 1588 static int 1589 npe_mii_mdio_wait(struct npe_softc *sc) 1590 { 1591 #define MAXTRIES 100 /* XXX */ 1592 uint32_t v; 1593 int i; 1594 1595 for (i = 0; i < MAXTRIES; i++) { 1596 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1597 if ((v & NPE_MII_GO) == 0) 1598 return 1; 1599 } 1600 return 0; /* NB: timeout */ 1601 #undef MAXTRIES 1602 } 1603 1604 static int 1605 npe_miibus_readreg(struct device *self, int phy, int reg) 1606 { 1607 struct npe_softc *sc = (void *)self; 1608 uint32_t v; 1609 1610 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1611 return 0xffff; 1612 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1613 | NPE_MII_GO; 1614 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1615 if (npe_mii_mdio_wait(sc)) 1616 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1617 else 1618 v = 0xffff | NPE_MII_READ_FAIL; 1619 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1620 #undef MAXTRIES 1621 } 1622 1623 static void 1624 npe_miibus_writereg(struct device *self, int phy, int reg, int data) 1625 { 1626 struct npe_softc *sc = (void *)self; 1627 uint32_t v; 1628 1629 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1630 return; 1631 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1632 | data | NPE_MII_WRITE 1633 | NPE_MII_GO; 1634 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1635 /* XXX complain about timeout */ 1636 (void) npe_mii_mdio_wait(sc); 1637 } 1638 1639 static void 1640 npe_miibus_statchg(struct device *self) 1641 { 1642 struct npe_softc *sc = (void *)self; 1643 uint32_t tx1, rx1; 1644 1645 /* sync MAC duplex state */ 1646 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1647 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1648 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1649 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1650 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1651 } else { 1652 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1653 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1654 } 1655 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1656 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1657 } 1658
Indexes created Thu Oct 02 10:09:58 GMT 2025