ixp425_if_npe.c revision 1.14
1 /* $NetBSD: ixp425_if_npe.c,v 1.14 2009/03/11 13:20:30 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.14 2009/03/11 13:20:30 msaitoh Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include "bpfilter.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/device.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/socket.h> 60 #include <sys/endian.h> 61 #include <sys/ioctl.h> 62 #include <sys/syslog.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <arm/xscale/ixp425reg.h> 76 #include <arm/xscale/ixp425var.h> 77 #include <arm/xscale/ixp425_qmgr.h> 78 #include <arm/xscale/ixp425_npevar.h> 79 #include <arm/xscale/ixp425_if_npereg.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include "locators.h" 84 85 struct npebuf { 86 struct npebuf *ix_next; /* chain to next buffer */ 87 void *ix_m; /* backpointer to mbuf */ 88 bus_dmamap_t ix_map; /* bus dma map for associated data */ 89 struct npehwbuf *ix_hw; /* associated h/w block */ 90 uint32_t ix_neaddr; /* phys address of ix_hw */ 91 }; 92 93 struct npedma { 94 const char* name; 95 int nbuf; /* # npebuf's allocated */ 96 bus_dmamap_t m_map; 97 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 98 bus_dmamap_t buf_map; 99 bus_addr_t buf_phys; /* phys addr of buffers */ 100 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 101 }; 102 103 struct npe_softc { 104 struct device sc_dev; 105 struct ethercom sc_ethercom; 106 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 107 struct mii_data sc_mii; 108 bus_space_tag_t sc_iot; 109 bus_dma_tag_t sc_dt; 110 bus_space_handle_t sc_ioh; /* MAC register window */ 111 bus_space_handle_t sc_miih; /* MII register window */ 112 struct ixpnpe_softc *sc_npe; /* NPE support */ 113 int sc_unit; 114 int sc_phy; 115 struct callout sc_tick_ch; /* Tick callout */ 116 struct npedma txdma; 117 struct npebuf *tx_free; /* list of free tx buffers */ 118 struct npedma rxdma; 119 int rx_qid; /* rx qid */ 120 int rx_freeqid; /* rx free buffers qid */ 121 int tx_qid; /* tx qid */ 122 int tx_doneqid; /* tx completed qid */ 123 struct npestats *sc_stats; 124 bus_dmamap_t sc_stats_map; 125 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 126 int sc_if_flags; /* keep last if_flags */ 127 }; 128 129 /* 130 * Per-unit static configuration for IXP425. The tx and 131 * rx free Q id's are fixed by the NPE microcode. The 132 * rx Q id's are programmed to be separate to simplify 133 * multi-port processing. It may be better to handle 134 * all traffic through one Q (as done by the Intel drivers). 135 * 136 * Note that the PHY's are accessible only from MAC A 137 * on the IXP425. This and other platform-specific 138 * assumptions probably need to be handled through hints. 139 */ 140 static const struct { 141 const char *desc; /* device description */ 142 int npeid; /* NPE assignment */ 143 uint32_t imageid; /* NPE firmware image id */ 144 uint32_t regbase; 145 int regsize; 146 uint32_t miibase; 147 int miisize; 148 uint8_t rx_qid; 149 uint8_t rx_freeqid; 150 uint8_t tx_qid; 151 uint8_t tx_doneqid; 152 } npeconfig[NPE_PORTS_MAX] = { 153 { .desc = "IXP NPE-B", 154 .npeid = NPE_B, 155 .imageid = IXP425_NPE_B_IMAGEID, 156 .regbase = IXP425_MAC_A_HWBASE, 157 .regsize = IXP425_MAC_A_SIZE, 158 .miibase = IXP425_MAC_A_HWBASE, 159 .miisize = IXP425_MAC_A_SIZE, 160 .rx_qid = 4, 161 .rx_freeqid = 27, 162 .tx_qid = 24, 163 .tx_doneqid = 31 164 }, 165 { .desc = "IXP NPE-C", 166 .npeid = NPE_C, 167 .imageid = IXP425_NPE_C_IMAGEID, 168 .regbase = IXP425_MAC_B_HWBASE, 169 .regsize = IXP425_MAC_B_SIZE, 170 .miibase = IXP425_MAC_A_HWBASE, 171 .miisize = IXP425_MAC_A_SIZE, 172 .rx_qid = 12, 173 .rx_freeqid = 28, 174 .tx_qid = 25, 175 .tx_doneqid = 31 176 }, 177 }; 178 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 179 180 static __inline uint32_t 181 RD4(struct npe_softc *sc, bus_size_t off) 182 { 183 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 184 } 185 186 static __inline void 187 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 188 { 189 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 190 } 191 192 static int npe_activate(struct npe_softc *); 193 #if 0 194 static void npe_deactivate(struct npe_softc *); 195 #endif 196 static int npe_ifmedia_change(struct ifnet *ifp); 197 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 198 static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 199 static void npe_getmac(struct npe_softc *sc); 200 static void npe_txdone(int qid, void *arg); 201 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 202 struct mbuf *); 203 static void npe_rxdone(int qid, void *arg); 204 static void npeinit_macreg(struct npe_softc *); 205 static int npeinit(struct ifnet *); 206 static void npeinit_locked(void *); 207 static void npestart(struct ifnet *); 208 static void npestop(struct ifnet *, int); 209 static void npewatchdog(struct ifnet *); 210 static int npeioctl(struct ifnet * ifp, u_long, void *); 211 212 static int npe_setrxqosentry(struct npe_softc *, int classix, 213 int trafclass, int qid); 214 static int npe_updatestats(struct npe_softc *); 215 #if 0 216 static int npe_getstats(struct npe_softc *); 217 static uint32_t npe_getimageid(struct npe_softc *); 218 static int npe_setloopback(struct npe_softc *, int ena); 219 #endif 220 221 static int npe_miibus_readreg(struct device *, int, int); 222 static void npe_miibus_writereg(struct device *, int, int, int); 223 static void npe_miibus_statchg(struct device *); 224 225 static int npe_debug; 226 #define DPRINTF(sc, fmt, ...) do { \ 227 if (npe_debug) printf(fmt, __VA_ARGS__); \ 228 } while (0) 229 #define DPRINTFn(n, sc, fmt, ...) do { \ 230 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 231 } while (0) 232 233 #define NPE_TXBUF 128 234 #define NPE_RXBUF 64 235 236 #ifndef ETHER_ALIGN 237 #define ETHER_ALIGN 2 /* XXX: Ditch this */ 238 #endif 239 240 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 241 + ((uint64_t)addr[1] << 32) \ 242 + ((uint64_t)addr[2] << 24) \ 243 + ((uint64_t)addr[3] << 16) \ 244 + ((uint64_t)addr[4] << 8) \ 245 + (uint64_t)addr[5]) 246 247 /* NB: all tx done processing goes through one queue */ 248 static int tx_doneqid = -1; 249 250 void (*npe_getmac_md)(int, uint8_t *); 251 252 static int npe_match(struct device *, struct cfdata *, void *); 253 static void npe_attach(struct device *, struct device *, void *); 254 255 CFATTACH_DECL(npe, sizeof(struct npe_softc), 256 npe_match, npe_attach, NULL, NULL); 257 258 static int 259 npe_match(struct device *parent, struct cfdata *cf, void *arg) 260 { 261 struct ixpnpe_attach_args *na = arg; 262 263 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 264 } 265 266 static void 267 npe_attach(struct device *parent, struct device *self, void *arg) 268 { 269 struct npe_softc *sc = (void *)self; 270 struct ixpnpe_attach_args *na = arg; 271 struct ifnet *ifp; 272 273 aprint_naive("\n"); 274 aprint_normal(": Ethernet co-processor\n"); 275 276 sc->sc_iot = na->na_iot; 277 sc->sc_dt = na->na_dt; 278 sc->sc_npe = na->na_npe; 279 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 280 sc->sc_phy = na->na_phy; 281 282 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 283 memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 284 285 callout_init(&sc->sc_tick_ch, 0); 286 287 if (npe_activate(sc)) { 288 aprint_error("%s: Failed to activate NPE (missing " 289 "microcode?)\n", sc->sc_dev.dv_xname); 290 return; 291 } 292 293 npe_getmac(sc); 294 npeinit_macreg(sc); 295 296 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 297 ether_sprintf(sc->sc_enaddr)); 298 299 ifp = &sc->sc_ethercom.ec_if; 300 ifmedia_init(&sc->sc_mii.mii_media, 0, npe_ifmedia_change, 301 npe_ifmedia_status); 302 303 if (sc->sc_phy != IXPNPECF_PHY_DEFAULT) { 304 sc->sc_mii.mii_ifp = ifp; 305 sc->sc_mii.mii_readreg = npe_miibus_readreg; 306 sc->sc_mii.mii_writereg = npe_miibus_writereg; 307 sc->sc_mii.mii_statchg = npe_miibus_statchg; 308 sc->sc_ethercom.ec_mii = &sc->sc_mii; 309 310 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, 311 (sc->sc_phy > IXPNPECF_PHY_DEFAULT) ? 312 sc->sc_phy : MII_PHY_ANY, 313 MII_OFFSET_ANY, MIIF_NOISOLATE); 314 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 315 } else { 316 /* Assume direct connection to a 100mbit switch */ 317 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX, 0,0); 318 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_100_TX); 319 } 320 321 ifp->if_softc = sc; 322 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_start = npestart; 325 ifp->if_ioctl = npeioctl; 326 ifp->if_watchdog = npewatchdog; 327 ifp->if_init = npeinit; 328 ifp->if_stop = npestop; 329 IFQ_SET_READY(&ifp->if_snd); 330 331 /* VLAN capable */ 332 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 333 334 if_attach(ifp); 335 ether_ifattach(ifp, sc->sc_enaddr); 336 } 337 338 /* 339 * Compute and install the multicast filter. 340 */ 341 static void 342 npe_setmcast(struct npe_softc *sc) 343 { 344 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 345 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 346 uint32_t reg; 347 int i; 348 349 /* Always use filter. Is here a correct position? */ 350 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 351 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 352 353 if (ifp->if_flags & IFF_PROMISC) { 354 memset(mask, 0, ETHER_ADDR_LEN); 355 memset(addr, 0, ETHER_ADDR_LEN); 356 } else if (ifp->if_flags & IFF_ALLMULTI) { 357 static const uint8_t allmulti[ETHER_ADDR_LEN] = 358 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 359 all_multi: 360 memcpy(mask, allmulti, ETHER_ADDR_LEN); 361 memcpy(addr, allmulti, ETHER_ADDR_LEN); 362 } else { 363 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 364 struct ether_multistep step; 365 struct ether_multi *enm; 366 367 memset(clr, 0, ETHER_ADDR_LEN); 368 memset(set, 0xff, ETHER_ADDR_LEN); 369 370 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 371 while (enm != NULL) { 372 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 373 ifp->if_flags |= IFF_ALLMULTI; 374 goto all_multi; 375 } 376 377 for (i = 0; i < ETHER_ADDR_LEN; i++) { 378 clr[i] |= enm->enm_addrlo[i]; 379 set[i] &= enm->enm_addrlo[i]; 380 } 381 382 ETHER_NEXT_MULTI(step, enm); 383 } 384 385 for (i = 0; i < ETHER_ADDR_LEN; i++) { 386 mask[i] = set[i] | ~clr[i]; 387 addr[i] = set[i]; 388 } 389 } 390 391 /* 392 * Write the mask and address registers. 393 */ 394 for (i = 0; i < ETHER_ADDR_LEN; i++) { 395 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 396 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 397 } 398 } 399 400 static int 401 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 402 const char *name, int nbuf, int maxseg) 403 { 404 bus_dma_segment_t seg; 405 int rseg, error, i; 406 void *hwbuf; 407 size_t size; 408 409 memset(dma, 0, sizeof(*dma)); 410 411 dma->name = name; 412 dma->nbuf = nbuf; 413 414 size = nbuf * sizeof(struct npehwbuf); 415 416 /* XXX COHERENT for now */ 417 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 418 1, &rseg, BUS_DMA_NOWAIT); 419 if (error) { 420 printf("%s: unable to allocate memory for %s h/w buffers, " 421 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 422 } 423 424 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 425 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 426 if (error) { 427 printf("%s: unable to map memory for %s h/w buffers, " 428 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 429 free_dmamem: 430 bus_dmamem_free(sc->sc_dt, &seg, rseg); 431 return error; 432 } 433 dma->hwbuf = (void *)hwbuf; 434 435 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 436 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 437 if (error) { 438 printf("%s: unable to create map for %s h/w buffers, " 439 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 440 unmap_dmamem: 441 dma->hwbuf = NULL; 442 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 443 goto free_dmamem; 444 } 445 446 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 447 BUS_DMA_NOWAIT); 448 if (error) { 449 printf("%s: unable to load map for %s h/w buffers, " 450 "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 451 destroy_dmamap: 452 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 453 goto unmap_dmamem; 454 } 455 456 /* XXX M_TEMP */ 457 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 458 if (dma->buf == NULL) { 459 printf("%s: unable to allocate memory for %s s/w buffers\n", 460 sc->sc_dev.dv_xname, dma->name); 461 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 462 error = ENOMEM; 463 goto destroy_dmamap; 464 } 465 466 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 467 for (i = 0; i < dma->nbuf; i++) { 468 struct npebuf *npe = &dma->buf[i]; 469 struct npehwbuf *hw = &dma->hwbuf[i]; 470 471 /* calculate offset to shared area */ 472 npe->ix_neaddr = dma->buf_phys + 473 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 474 KASSERT((npe->ix_neaddr & 0x1f) == 0); 475 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 476 MCLBYTES, 0, 0, &npe->ix_map); 477 if (error != 0) { 478 printf("%s: unable to create dmamap for %s buffer %u, " 479 "error %u\n", sc->sc_dev.dv_xname, dma->name, i, 480 error); 481 /* XXXSCW: Free up maps... */ 482 return error; 483 } 484 npe->ix_hw = hw; 485 } 486 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 487 BUS_DMASYNC_PREWRITE); 488 return 0; 489 } 490 491 #if 0 492 static void 493 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 494 { 495 int i; 496 497 /* XXXSCW: Clean this up */ 498 499 if (dma->hwbuf != NULL) { 500 for (i = 0; i < dma->nbuf; i++) { 501 struct npebuf *npe = &dma->buf[i]; 502 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 503 } 504 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 505 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 506 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 507 } 508 if (dma->buf != NULL) 509 free(dma->buf, M_TEMP); 510 memset(dma, 0, sizeof(*dma)); 511 } 512 #endif 513 514 static int 515 npe_activate(struct npe_softc *sc) 516 { 517 bus_dma_segment_t seg; 518 int unit = sc->sc_unit; 519 int error, i, rseg; 520 void *statbuf; 521 522 /* load NPE firmware and start it running */ 523 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 524 if (error != 0) 525 return error; 526 527 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 528 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 529 printf("%s: Cannot map registers 0x%x:0x%x\n", 530 sc->sc_dev.dv_xname, npeconfig[unit].regbase, 531 npeconfig[unit].regsize); 532 return ENOMEM; 533 } 534 535 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 536 /* 537 * The PHY's are only accessible from one MAC (it appears) 538 * so for other MAC's setup an additional mapping for 539 * frobbing the PHY registers. 540 */ 541 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 542 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 543 printf("%s: Cannot map MII registers 0x%x:0x%x\n", 544 sc->sc_dev.dv_xname, npeconfig[unit].miibase, 545 npeconfig[unit].miisize); 546 return ENOMEM; 547 } 548 } else 549 sc->sc_miih = sc->sc_ioh; 550 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 551 if (error != 0) 552 return error; 553 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 554 if (error != 0) 555 return error; 556 557 /* setup statistics block */ 558 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 559 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 560 if (error) { 561 printf("%s: unable to allocate memory for stats block, " 562 "error %u\n", sc->sc_dev.dv_xname, error); 563 return error; 564 } 565 566 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 567 &statbuf, BUS_DMA_NOWAIT); 568 if (error) { 569 printf("%s: unable to map memory for stats block, " 570 "error %u\n", sc->sc_dev.dv_xname, error); 571 return error; 572 } 573 sc->sc_stats = (void *)statbuf; 574 575 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 576 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 577 &sc->sc_stats_map); 578 if (error) { 579 printf("%s: unable to create map for stats block, " 580 "error %u\n", sc->sc_dev.dv_xname, error); 581 return error; 582 } 583 584 if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 585 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) { 586 printf("%s: unable to load memory for stats block, error %u\n", 587 sc->sc_dev.dv_xname, error); 588 return error; 589 } 590 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 591 592 /* XXX disable half-bridge LEARNING+FILTERING feature */ 593 594 /* 595 * Setup h/w rx/tx queues. There are four q's: 596 * rx inbound q of rx'd frames 597 * rx_free pool of ixpbuf's for receiving frames 598 * tx outbound q of frames to send 599 * tx_done q of tx frames that have been processed 600 * 601 * The NPE handles the actual tx/rx process and the q manager 602 * handles the queues. The driver just writes entries to the 603 * q manager mailbox's and gets callbacks when there are rx'd 604 * frames to process or tx'd frames to reap. These callbacks 605 * are controlled by the q configurations; e.g. we get a 606 * callback when tx_done has 2 or more frames to process and 607 * when the rx q has at least one frame. These setings can 608 * changed at the time the q is configured. 609 */ 610 sc->rx_qid = npeconfig[unit].rx_qid; 611 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 612 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 613 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 614 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 615 /* tell the NPE to direct all traffic to rx_qid */ 616 #if 0 617 for (i = 0; i < 8; i++) 618 #else 619 printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname); 620 for (i = 0; i < 4; i++) 621 #endif 622 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 623 624 sc->tx_qid = npeconfig[unit].tx_qid; 625 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 626 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 627 if (tx_doneqid == -1) { 628 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 629 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 630 tx_doneqid = sc->tx_doneqid; 631 } 632 633 KASSERT(npes[npeconfig[unit].npeid] == NULL); 634 npes[npeconfig[unit].npeid] = sc; 635 636 return 0; 637 } 638 639 #if 0 640 static void 641 npe_deactivate(struct npe_softc *sc); 642 { 643 int unit = sc->sc_unit; 644 645 npes[npeconfig[unit].npeid] = NULL; 646 647 /* XXX disable q's */ 648 if (sc->sc_npe != NULL) 649 ixpnpe_stop(sc->sc_npe); 650 if (sc->sc_stats != NULL) { 651 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 652 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 653 sc->sc_stats_map); 654 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 655 } 656 if (sc->sc_stats_tag != NULL) 657 bus_dma_tag_destroy(sc->sc_stats_tag); 658 npe_dma_destroy(sc, &sc->txdma); 659 npe_dma_destroy(sc, &sc->rxdma); 660 bus_generic_detach(sc->sc_dev); 661 if (sc->sc_mii) 662 device_delete_child(sc->sc_dev, sc->sc_mii); 663 #if 0 664 /* XXX sc_ioh and sc_miih */ 665 if (sc->mem_res) 666 bus_release_resource(dev, SYS_RES_IOPORT, 667 rman_get_rid(sc->mem_res), sc->mem_res); 668 sc->mem_res = 0; 669 #endif 670 } 671 #endif 672 673 /* 674 * Change media according to request. 675 */ 676 static int 677 npe_ifmedia_change(struct ifnet *ifp) 678 { 679 struct npe_softc *sc = ifp->if_softc; 680 681 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 682 return ether_mediachange(ifp); 683 return 0; 684 } 685 686 /* 687 * Notify the world which media we're using. 688 */ 689 static void 690 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 691 { 692 struct npe_softc *sc = ifp->if_softc; 693 694 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT) 695 mii_pollstat(&sc->sc_mii); 696 697 ifmr->ifm_active = sc->sc_mii.mii_media_active; 698 ifmr->ifm_status = sc->sc_mii.mii_media_status; 699 } 700 701 static void 702 npe_addstats(struct npe_softc *sc) 703 { 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 struct npestats *ns = sc->sc_stats; 706 707 ifp->if_oerrors += 708 be32toh(ns->dot3StatsInternalMacTransmitErrors) 709 + be32toh(ns->dot3StatsCarrierSenseErrors) 710 + be32toh(ns->TxVLANIdFilterDiscards) 711 ; 712 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 713 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 714 + be32toh(ns->RxOverrunDiscards) 715 + be32toh(ns->RxUnderflowEntryDiscards) 716 ; 717 ifp->if_collisions += 718 be32toh(ns->dot3StatsSingleCollisionFrames) 719 + be32toh(ns->dot3StatsMultipleCollisionFrames) 720 ; 721 } 722 723 static void 724 npe_tick(void *xsc) 725 { 726 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 727 struct npe_softc *sc = xsc; 728 uint32_t msg[2]; 729 730 /* 731 * NB: to avoid sleeping with the softc lock held we 732 * split the NPE msg processing into two parts. The 733 * request for statistics is sent w/o waiting for a 734 * reply and then on the next tick we retrieve the 735 * results. This works because npe_tick is the only 736 * code that talks via the mailbox's (except at setup). 737 * This likely can be handled better. 738 */ 739 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 740 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 741 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 742 npe_addstats(sc); 743 } 744 npe_updatestats(sc); 745 mii_tick(&sc->sc_mii); 746 747 /* schedule next poll */ 748 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 749 #undef ACK 750 } 751 752 static void 753 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 754 { 755 756 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 757 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 758 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 759 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 760 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 761 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 762 } 763 764 static void 765 npe_getmac(struct npe_softc *sc) 766 { 767 uint8_t *eaddr = sc->sc_enaddr; 768 769 if (npe_getmac_md != NULL) { 770 (*npe_getmac_md)(sc->sc_dev.dv_unit, eaddr); 771 } else { 772 /* 773 * Some system's unicast address appears to be loaded from 774 * EEPROM on reset 775 */ 776 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 777 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 778 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 779 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 780 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 781 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 782 } 783 } 784 785 struct txdone { 786 struct npebuf *head; 787 struct npebuf **tail; 788 int count; 789 }; 790 791 static __inline void 792 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 793 { 794 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 795 796 *td->tail = sc->tx_free; 797 sc->tx_free = td->head; 798 /* 799 * We're no longer busy, so clear the busy flag and call the 800 * start routine to xmit more packets. 801 */ 802 ifp->if_opackets += td->count; 803 ifp->if_flags &= ~IFF_OACTIVE; 804 ifp->if_timer = 0; 805 npestart(ifp); 806 } 807 808 /* 809 * Q manager callback on tx done queue. Reap mbufs 810 * and return tx buffers to the free list. Finally 811 * restart output. Note the microcode has only one 812 * txdone q wired into it so we must use the NPE ID 813 * returned with each npehwbuf to decide where to 814 * send buffers. 815 */ 816 static void 817 npe_txdone(int qid, void *arg) 818 { 819 #define P2V(a, dma) \ 820 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 821 struct npe_softc *sc; 822 struct npebuf *npe; 823 struct txdone *td, q[NPE_MAX]; 824 uint32_t entry; 825 826 /* XXX no NPE-A support */ 827 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 828 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 829 /* XXX max # at a time? */ 830 while (ixpqmgr_qread(qid, &entry) == 0) { 831 sc = npes[NPE_QM_Q_NPE(entry)]; 832 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 833 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 834 835 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 836 m_freem(npe->ix_m); 837 npe->ix_m = NULL; 838 839 td = &q[NPE_QM_Q_NPE(entry)]; 840 *td->tail = npe; 841 td->tail = &npe->ix_next; 842 td->count++; 843 } 844 845 if (q[NPE_B].count) 846 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 847 if (q[NPE_C].count) 848 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 849 #undef P2V 850 } 851 852 static __inline struct mbuf * 853 npe_getcl(void) 854 { 855 struct mbuf *m; 856 857 MGETHDR(m, M_DONTWAIT, MT_DATA); 858 if (m != NULL) { 859 MCLGET(m, M_DONTWAIT); 860 if ((m->m_flags & M_EXT) == 0) { 861 m_freem(m); 862 m = NULL; 863 } 864 } 865 return (m); 866 } 867 868 static int 869 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 870 { 871 struct npehwbuf *hw; 872 int error; 873 874 if (m == NULL) { 875 m = npe_getcl(); 876 if (m == NULL) 877 return ENOBUFS; 878 } 879 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 880 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 881 /* backload payload and align ip hdr */ 882 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 883 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 884 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 885 BUS_DMA_READ|BUS_DMA_NOWAIT); 886 if (error != 0) { 887 m_freem(m); 888 return error; 889 } 890 hw = npe->ix_hw; 891 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 892 /* NB: NPE requires length be a multiple of 64 */ 893 /* NB: buffer length is shifted in word */ 894 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 895 hw->ix_ne[0].next = 0; 896 npe->ix_m = m; 897 /* Flush the memory in the mbuf */ 898 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 899 BUS_DMASYNC_PREREAD); 900 return 0; 901 } 902 903 /* 904 * RX q processing for a specific NPE. Claim entries 905 * from the hardware queue and pass the frames up the 906 * stack. Pass the rx buffers to the free list. 907 */ 908 static void 909 npe_rxdone(int qid, void *arg) 910 { 911 #define P2V(a, dma) \ 912 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 913 struct npe_softc *sc = arg; 914 struct npedma *dma = &sc->rxdma; 915 uint32_t entry; 916 917 while (ixpqmgr_qread(qid, &entry) == 0) { 918 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 919 struct mbuf *m; 920 921 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 922 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 923 /* 924 * Allocate a new mbuf to replenish the rx buffer. 925 * If doing so fails we drop the rx'd frame so we 926 * can reuse the previous mbuf. When we're able to 927 * allocate a new mbuf dispatch the mbuf w/ rx'd 928 * data up the stack and replace it with the newly 929 * allocated one. 930 */ 931 m = npe_getcl(); 932 if (m != NULL) { 933 struct mbuf *mrx = npe->ix_m; 934 struct npehwbuf *hw = npe->ix_hw; 935 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 936 937 /* Flush mbuf memory for rx'd data */ 938 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 939 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 940 941 /* XXX flush hw buffer; works now 'cuz coherent */ 942 /* set m_len etc. per rx frame size */ 943 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 944 mrx->m_pkthdr.len = mrx->m_len; 945 mrx->m_pkthdr.rcvif = ifp; 946 /* Don't add M_HASFCS. See below */ 947 948 #if 1 949 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 950 log(LOG_INFO, "%s: too short frame (len=%d)\n", 951 sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 952 /* Back out "newly allocated" mbuf. */ 953 m_freem(m); 954 ifp->if_ierrors++; 955 goto fail; 956 } 957 if ((ifp->if_flags & IFF_PROMISC) == 0) { 958 struct ether_header *eh; 959 960 /* 961 * Workaround for "Non-Intel XScale Technology 962 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 963 * matches the filter (both unicast and 964 * multicast). 965 */ 966 eh = mtod(mrx, struct ether_header *); 967 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 968 /* unicast */ 969 970 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 971 /* discard it */ 972 #if 0 973 printf("discard it\n"); 974 #endif 975 /* 976 * Back out "newly allocated" 977 * mbuf. 978 */ 979 m_freem(m); 980 goto fail; 981 } 982 } else if (memcmp(eh->ether_dhost, 983 etherbroadcastaddr, 6) == 0) { 984 /* Always accept broadcast packet*/ 985 } else { 986 struct ethercom *ec = &sc->sc_ethercom; 987 struct ether_multi *enm; 988 struct ether_multistep step; 989 int match = 0; 990 991 /* multicast */ 992 993 ETHER_FIRST_MULTI(step, ec, enm); 994 while (enm != NULL) { 995 uint64_t lowint, highint, dest; 996 997 lowint = MAC2UINT64(enm->enm_addrlo); 998 highint = MAC2UINT64(enm->enm_addrhi); 999 dest = MAC2UINT64(eh->ether_dhost); 1000 #if 0 1001 printf("%llx\n", lowint); 1002 printf("%llx\n", dest); 1003 printf("%llx\n", highint); 1004 #endif 1005 if ((lowint <= dest) && (dest <= highint)) { 1006 match = 1; 1007 break; 1008 } 1009 ETHER_NEXT_MULTI(step, enm); 1010 } 1011 if (match == 0) { 1012 /* discard it */ 1013 #if 0 1014 printf("discard it(M)\n"); 1015 #endif 1016 /* 1017 * Back out "newly allocated" 1018 * mbuf. 1019 */ 1020 m_freem(m); 1021 goto fail; 1022 } 1023 } 1024 } 1025 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1026 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1027 sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 1028 /* Back out "newly allocated" mbuf. */ 1029 m_freem(m); 1030 ifp->if_ierrors++; 1031 goto fail; 1032 } 1033 #endif 1034 1035 /* 1036 * Trim FCS! 1037 * NPE always adds the FCS by this driver's setting, 1038 * so we always trim it here and not add M_HASFCS. 1039 */ 1040 m_adj(mrx, -ETHER_CRC_LEN); 1041 1042 ifp->if_ipackets++; 1043 #if NBPFILTER > 0 1044 /* 1045 * Tap off here if there is a bpf listener. 1046 */ 1047 if (__predict_false(ifp->if_bpf)) 1048 bpf_mtap(ifp->if_bpf, mrx); 1049 #endif 1050 ifp->if_input(ifp, mrx); 1051 } else { 1052 fail: 1053 /* discard frame and re-use mbuf */ 1054 m = npe->ix_m; 1055 } 1056 if (npe_rxbuf_init(sc, npe, m) == 0) { 1057 /* return npe buf to rx free list */ 1058 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1059 } else { 1060 /* XXX should not happen */ 1061 } 1062 } 1063 #undef P2V 1064 } 1065 1066 static void 1067 npe_startxmit(struct npe_softc *sc) 1068 { 1069 struct npedma *dma = &sc->txdma; 1070 int i; 1071 1072 sc->tx_free = NULL; 1073 for (i = 0; i < dma->nbuf; i++) { 1074 struct npebuf *npe = &dma->buf[i]; 1075 if (npe->ix_m != NULL) { 1076 /* NB: should not happen */ 1077 printf("%s: %s: free mbuf at entry %u\n", 1078 sc->sc_dev.dv_xname, __func__, i); 1079 m_freem(npe->ix_m); 1080 } 1081 npe->ix_m = NULL; 1082 npe->ix_next = sc->tx_free; 1083 sc->tx_free = npe; 1084 } 1085 } 1086 1087 static void 1088 npe_startrecv(struct npe_softc *sc) 1089 { 1090 struct npedma *dma = &sc->rxdma; 1091 struct npebuf *npe; 1092 int i; 1093 1094 for (i = 0; i < dma->nbuf; i++) { 1095 npe = &dma->buf[i]; 1096 npe_rxbuf_init(sc, npe, npe->ix_m); 1097 /* set npe buf on rx free list */ 1098 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1099 } 1100 } 1101 1102 static void 1103 npeinit_macreg(struct npe_softc *sc) 1104 { 1105 1106 /* 1107 * Reset MAC core. 1108 */ 1109 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1110 DELAY(NPE_MAC_RESET_DELAY); 1111 /* configure MAC to generate MDC clock */ 1112 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1113 1114 /* disable transmitter and reciver in the MAC */ 1115 WR4(sc, NPE_MAC_RX_CNTRL1, 1116 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1117 WR4(sc, NPE_MAC_TX_CNTRL1, 1118 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1119 1120 /* 1121 * Set the MAC core registers. 1122 */ 1123 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1124 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1125 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1126 /* thresholds determined by NPE firmware FS */ 1127 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1128 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1129 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1130 /* tx fifo threshold (bytes) */ 1131 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1132 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1133 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1134 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1135 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1136 /* assumes MII mode */ 1137 WR4(sc, NPE_MAC_TX_CNTRL1, 1138 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1139 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1140 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1141 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1142 /* XXX pad strip? */ 1143 WR4(sc, NPE_MAC_RX_CNTRL1, 1144 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1145 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1146 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1147 } 1148 1149 /* 1150 * Reset and initialize the chip 1151 */ 1152 static void 1153 npeinit_locked(void *xsc) 1154 { 1155 struct npe_softc *sc = xsc; 1156 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1157 1158 /* Cancel any pending I/O. */ 1159 npestop(ifp, 0); 1160 1161 /* Reset the chip to a known state. */ 1162 npeinit_macreg(sc); 1163 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1164 npe_ifmedia_change(ifp); 1165 npe_setmcast(sc); 1166 1167 npe_startxmit(sc); 1168 npe_startrecv(sc); 1169 1170 ifp->if_flags |= IFF_RUNNING; 1171 ifp->if_flags &= ~IFF_OACTIVE; 1172 ifp->if_timer = 0; /* just in case */ 1173 1174 /* enable transmitter and reciver in the MAC */ 1175 WR4(sc, NPE_MAC_RX_CNTRL1, 1176 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1177 WR4(sc, NPE_MAC_TX_CNTRL1, 1178 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1179 1180 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1181 } 1182 1183 static int 1184 npeinit(struct ifnet *ifp) 1185 { 1186 struct npe_softc *sc = ifp->if_softc; 1187 int s; 1188 1189 s = splnet(); 1190 npeinit_locked(sc); 1191 splx(s); 1192 1193 return (0); 1194 } 1195 1196 /* 1197 * Defragment an mbuf chain, returning at most maxfrags separate 1198 * mbufs+clusters. If this is not possible NULL is returned and 1199 * the original mbuf chain is left in it's present (potentially 1200 * modified) state. We use two techniques: collapsing consecutive 1201 * mbufs and replacing consecutive mbufs by a cluster. 1202 */ 1203 static __inline struct mbuf * 1204 npe_defrag(struct mbuf *m0) 1205 { 1206 struct mbuf *m; 1207 1208 MGETHDR(m, M_DONTWAIT, MT_DATA); 1209 if (m == NULL) 1210 return (NULL); 1211 M_COPY_PKTHDR(m, m0); 1212 1213 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1214 MCLGET(m, M_DONTWAIT); 1215 if ((m->m_flags & M_EXT) == 0) { 1216 m_freem(m); 1217 return (NULL); 1218 } 1219 } 1220 1221 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1222 m_freem(m0); 1223 1224 return (m); 1225 } 1226 1227 /* 1228 * Dequeue packets and place on the h/w transmit queue. 1229 */ 1230 static void 1231 npestart(struct ifnet *ifp) 1232 { 1233 struct npe_softc *sc = ifp->if_softc; 1234 struct npebuf *npe; 1235 struct npehwbuf *hw; 1236 struct mbuf *m, *n; 1237 bus_dma_segment_t *segs; 1238 int nseg, len, error, i; 1239 uint32_t next; 1240 1241 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1242 return; 1243 1244 while (sc->tx_free != NULL) { 1245 IFQ_DEQUEUE(&ifp->if_snd, m); 1246 if (m == NULL) 1247 break; 1248 npe = sc->tx_free; 1249 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1250 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1251 if (error == EFBIG) { 1252 n = npe_defrag(m); 1253 if (n == NULL) { 1254 printf("%s: %s: too many fragments\n", 1255 sc->sc_dev.dv_xname, __func__); 1256 m_freem(m); 1257 return; /* XXX? */ 1258 } 1259 m = n; 1260 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1261 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1262 } 1263 if (error != 0) { 1264 printf("%s: %s: error %u\n", 1265 sc->sc_dev.dv_xname, __func__, error); 1266 m_freem(m); 1267 return; /* XXX? */ 1268 } 1269 sc->tx_free = npe->ix_next; 1270 1271 #if NBPFILTER > 0 1272 /* 1273 * Tap off here if there is a bpf listener. 1274 */ 1275 if (__predict_false(ifp->if_bpf)) 1276 bpf_mtap(ifp->if_bpf, m); 1277 #endif 1278 1279 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1280 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1281 1282 npe->ix_m = m; 1283 hw = npe->ix_hw; 1284 len = m->m_pkthdr.len; 1285 nseg = npe->ix_map->dm_nsegs; 1286 segs = npe->ix_map->dm_segs; 1287 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1288 for (i = 0; i < nseg; i++) { 1289 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1290 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1291 hw->ix_ne[i].next = htobe32(next); 1292 1293 len = 0; /* zero for segments > 1 */ 1294 next += sizeof(hw->ix_ne[0]); 1295 } 1296 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1297 /* XXX flush descriptor instead of using uncached memory */ 1298 1299 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1300 __func__, sc->tx_qid, npe->ix_neaddr, 1301 hw->ix_ne[0].data, hw->ix_ne[0].len); 1302 /* stick it on the tx q */ 1303 /* XXX add vlan priority */ 1304 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1305 1306 ifp->if_timer = 5; 1307 } 1308 if (sc->tx_free == NULL) 1309 ifp->if_flags |= IFF_OACTIVE; 1310 } 1311 1312 static void 1313 npe_stopxmit(struct npe_softc *sc) 1314 { 1315 struct npedma *dma = &sc->txdma; 1316 int i; 1317 1318 /* XXX qmgr */ 1319 for (i = 0; i < dma->nbuf; i++) { 1320 struct npebuf *npe = &dma->buf[i]; 1321 1322 if (npe->ix_m != NULL) { 1323 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1324 m_freem(npe->ix_m); 1325 npe->ix_m = NULL; 1326 } 1327 } 1328 } 1329 1330 static void 1331 npe_stoprecv(struct npe_softc *sc) 1332 { 1333 struct npedma *dma = &sc->rxdma; 1334 int i; 1335 1336 /* XXX qmgr */ 1337 for (i = 0; i < dma->nbuf; i++) { 1338 struct npebuf *npe = &dma->buf[i]; 1339 1340 if (npe->ix_m != NULL) { 1341 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1342 m_freem(npe->ix_m); 1343 npe->ix_m = NULL; 1344 } 1345 } 1346 } 1347 1348 /* 1349 * Turn off interrupts, and stop the nic. 1350 */ 1351 void 1352 npestop(struct ifnet *ifp, int disable) 1353 { 1354 struct npe_softc *sc = ifp->if_softc; 1355 1356 /* disable transmitter and reciver in the MAC */ 1357 WR4(sc, NPE_MAC_RX_CNTRL1, 1358 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1359 WR4(sc, NPE_MAC_TX_CNTRL1, 1360 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1361 1362 callout_stop(&sc->sc_tick_ch); 1363 1364 npe_stopxmit(sc); 1365 npe_stoprecv(sc); 1366 /* XXX go into loopback & drain q's? */ 1367 /* XXX but beware of disabling tx above */ 1368 1369 /* 1370 * The MAC core rx/tx disable may leave the MAC hardware in an 1371 * unpredictable state. A hw reset is executed before resetting 1372 * all the MAC parameters to a known value. 1373 */ 1374 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1375 DELAY(NPE_MAC_RESET_DELAY); 1376 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1377 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1378 1379 ifp->if_timer = 0; 1380 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1381 } 1382 1383 void 1384 npewatchdog(struct ifnet *ifp) 1385 { 1386 struct npe_softc *sc = ifp->if_softc; 1387 int s; 1388 1389 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1390 s = splnet(); 1391 ifp->if_oerrors++; 1392 npeinit_locked(sc); 1393 splx(s); 1394 } 1395 1396 static int 1397 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1398 { 1399 struct npe_softc *sc = ifp->if_softc; 1400 struct ifreq *ifr = (struct ifreq *) data; 1401 int s, error = 0; 1402 1403 s = splnet(); 1404 1405 switch (cmd) { 1406 case SIOCSIFMEDIA: 1407 case SIOCGIFMEDIA: 1408 #if 0 /* not yet */ 1409 /* Flow control requires full-duplex mode. */ 1410 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1411 (ifr->ifr_media & IFM_FDX) == 0) 1412 ifr->ifr_media &= ~IFM_ETH_FMASK; 1413 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1414 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1415 /* We can do both TXPAUSE and RXPAUSE. */ 1416 ifr->ifr_media |= 1417 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1418 } 1419 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1420 } 1421 #endif 1422 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1423 break; 1424 case SIOCSIFFLAGS: 1425 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) { 1426 /* 1427 * If interface is marked down and it is running, 1428 * then stop and disable it. 1429 */ 1430 (*ifp->if_stop)(ifp, 1); 1431 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) { 1432 /* 1433 * If interface is marked up and it is stopped, then 1434 * start it. 1435 */ 1436 error = (*ifp->if_init)(ifp); 1437 } else if ((ifp->if_flags & IFF_UP) != 0) { 1438 int diff; 1439 1440 /* Up (AND RUNNING). */ 1441 1442 diff = (ifp->if_flags ^ sc->sc_if_flags) 1443 & (IFF_PROMISC|IFF_ALLMULTI); 1444 if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 1445 /* 1446 * If the difference bettween last flag and 1447 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1448 * set multicast filter only (don't reset to 1449 * prevent link down). 1450 */ 1451 npe_setmcast(sc); 1452 } else { 1453 /* 1454 * Reset the interface to pick up changes in 1455 * any other flags that affect the hardware 1456 * state. 1457 */ 1458 error = (*ifp->if_init)(ifp); 1459 } 1460 } 1461 sc->sc_if_flags = ifp->if_flags; 1462 break; 1463 default: 1464 error = ether_ioctl(ifp, cmd, data); 1465 if (error == ENETRESET) { 1466 /* 1467 * Multicast list has changed; set the hardware filter 1468 * accordingly. 1469 */ 1470 npe_setmcast(sc); 1471 error = 0; 1472 } 1473 } 1474 1475 npestart(ifp); 1476 1477 splx(s); 1478 return error; 1479 } 1480 1481 /* 1482 * Setup a traffic class -> rx queue mapping. 1483 */ 1484 static int 1485 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1486 { 1487 int npeid = npeconfig[sc->sc_unit].npeid; 1488 uint32_t msg[2]; 1489 1490 msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix; 1491 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1492 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1493 } 1494 1495 /* 1496 * Update and reset the statistics in the NPE. 1497 */ 1498 static int 1499 npe_updatestats(struct npe_softc *sc) 1500 { 1501 uint32_t msg[2]; 1502 1503 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1504 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1505 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1506 } 1507 1508 #if 0 1509 /* 1510 * Get the current statistics block. 1511 */ 1512 static int 1513 npe_getstats(struct npe_softc *sc) 1514 { 1515 uint32_t msg[2]; 1516 1517 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1518 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1519 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1520 } 1521 1522 /* 1523 * Query the image id of the loaded firmware. 1524 */ 1525 static uint32_t 1526 npe_getimageid(struct npe_softc *sc) 1527 { 1528 uint32_t msg[2]; 1529 1530 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1531 msg[1] = 0; 1532 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1533 } 1534 1535 /* 1536 * Enable/disable loopback. 1537 */ 1538 static int 1539 npe_setloopback(struct npe_softc *sc, int ena) 1540 { 1541 uint32_t msg[2]; 1542 1543 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1544 msg[1] = 0; 1545 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1546 } 1547 #endif 1548 1549 /* 1550 * MII bus support routines. 1551 * 1552 * NB: ixp425 has one PHY per NPE 1553 */ 1554 static uint32_t 1555 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1556 { 1557 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1558 uint32_t v; 1559 1560 /* NB: registers are known to be sequential */ 1561 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1562 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1563 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1564 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1565 return v; 1566 #undef MII_RD4 1567 } 1568 1569 static void 1570 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1571 { 1572 #define MII_WR4(sc, reg, v) \ 1573 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1574 1575 /* NB: registers are known to be sequential */ 1576 MII_WR4(sc, reg+0, cmd & 0xff); 1577 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1578 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1579 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1580 #undef MII_WR4 1581 } 1582 1583 static int 1584 npe_mii_mdio_wait(struct npe_softc *sc) 1585 { 1586 #define MAXTRIES 100 /* XXX */ 1587 uint32_t v; 1588 int i; 1589 1590 for (i = 0; i < MAXTRIES; i++) { 1591 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1592 if ((v & NPE_MII_GO) == 0) 1593 return 1; 1594 } 1595 return 0; /* NB: timeout */ 1596 #undef MAXTRIES 1597 } 1598 1599 static int 1600 npe_miibus_readreg(struct device *self, int phy, int reg) 1601 { 1602 struct npe_softc *sc = (void *)self; 1603 uint32_t v; 1604 1605 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1606 return 0xffff; 1607 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1608 | NPE_MII_GO; 1609 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1610 if (npe_mii_mdio_wait(sc)) 1611 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1612 else 1613 v = 0xffff | NPE_MII_READ_FAIL; 1614 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1615 #undef MAXTRIES 1616 } 1617 1618 static void 1619 npe_miibus_writereg(struct device *self, int phy, int reg, int data) 1620 { 1621 struct npe_softc *sc = (void *)self; 1622 uint32_t v; 1623 1624 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1625 return; 1626 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1627 | data | NPE_MII_WRITE 1628 | NPE_MII_GO; 1629 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1630 /* XXX complain about timeout */ 1631 (void) npe_mii_mdio_wait(sc); 1632 } 1633 1634 static void 1635 npe_miibus_statchg(struct device *self) 1636 { 1637 struct npe_softc *sc = (void *)self; 1638 uint32_t tx1, rx1; 1639 1640 /* sync MAC duplex state */ 1641 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1642 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1643 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1644 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1645 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1646 } else { 1647 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1648 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1649 } 1650 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1651 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1652 } 1653
Indexes created Thu Oct 02 10:09:58 GMT 2025