ixp425_if_npe.c revision 1.34
1 /* $NetBSD: ixp425_if_npe.c,v 1.34 2018/06/26 06:47:58 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.34 2018/06/26 06:47:58 msaitoh Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/socket.h> 58 #include <sys/endian.h> 59 #include <sys/ioctl.h> 60 #include <sys/syslog.h> 61 62 #include <sys/bus.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rndsource.h> 72 73 #include <arm/xscale/ixp425reg.h> 74 #include <arm/xscale/ixp425var.h> 75 #include <arm/xscale/ixp425_qmgr.h> 76 #include <arm/xscale/ixp425_npevar.h> 77 #include <arm/xscale/ixp425_if_npereg.h> 78 79 #include <dev/mii/miivar.h> 80 81 #include "locators.h" 82 83 struct npebuf { 84 struct npebuf *ix_next; /* chain to next buffer */ 85 void *ix_m; /* backpointer to mbuf */ 86 bus_dmamap_t ix_map; /* bus dma map for associated data */ 87 struct npehwbuf *ix_hw; /* associated h/w block */ 88 uint32_t ix_neaddr; /* phys address of ix_hw */ 89 }; 90 91 struct npedma { 92 const char* name; 93 int nbuf; /* # npebuf's allocated */ 94 bus_dmamap_t m_map; 95 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 96 bus_dmamap_t buf_map; 97 bus_addr_t buf_phys; /* phys addr of buffers */ 98 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 99 }; 100 101 struct npe_softc { 102 device_t sc_dev; 103 struct ethercom sc_ethercom; 104 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 105 struct mii_data sc_mii; 106 bus_space_tag_t sc_iot; 107 bus_dma_tag_t sc_dt; 108 bus_space_handle_t sc_ioh; /* MAC register window */ 109 bus_space_handle_t sc_miih; /* MII register window */ 110 struct ixpnpe_softc *sc_npe; /* NPE support */ 111 int sc_unit; 112 int sc_phy; 113 struct callout sc_tick_ch; /* Tick callout */ 114 struct npedma txdma; 115 struct npebuf *tx_free; /* list of free tx buffers */ 116 struct npedma rxdma; 117 int rx_qid; /* rx qid */ 118 int rx_freeqid; /* rx free buffers qid */ 119 int tx_qid; /* tx qid */ 120 int tx_doneqid; /* tx completed qid */ 121 struct npestats *sc_stats; 122 bus_dmamap_t sc_stats_map; 123 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 124 int sc_if_flags; /* keep last if_flags */ 125 krndsource_t rnd_source; /* random source */ 126 }; 127 128 /* 129 * Per-unit static configuration for IXP425. The tx and 130 * rx free Q id's are fixed by the NPE microcode. The 131 * rx Q id's are programmed to be separate to simplify 132 * multi-port processing. It may be better to handle 133 * all traffic through one Q (as done by the Intel drivers). 134 * 135 * Note that the PHY's are accessible only from MAC A 136 * on the IXP425. This and other platform-specific 137 * assumptions probably need to be handled through hints. 138 */ 139 static const struct { 140 const char *desc; /* device description */ 141 int npeid; /* NPE assignment */ 142 int macport; /* Port number of the MAC */ 143 uint32_t imageid; /* NPE firmware image id */ 144 uint32_t regbase; 145 int regsize; 146 uint32_t miibase; 147 int miisize; 148 uint8_t rx_qid; 149 uint8_t rx_freeqid; 150 uint8_t tx_qid; 151 uint8_t tx_doneqid; 152 } npeconfig[NPE_PORTS_MAX] = { 153 { .desc = "IXP NPE-B", 154 .npeid = NPE_B, 155 .macport = 0x10, 156 .imageid = IXP425_NPE_B_IMAGEID, 157 .regbase = IXP425_MAC_A_HWBASE, 158 .regsize = IXP425_MAC_A_SIZE, 159 .miibase = IXP425_MAC_A_HWBASE, 160 .miisize = IXP425_MAC_A_SIZE, 161 .rx_qid = 4, 162 .rx_freeqid = 27, 163 .tx_qid = 24, 164 .tx_doneqid = 31 165 }, 166 { .desc = "IXP NPE-C", 167 .npeid = NPE_C, 168 .macport = 0x20, 169 .imageid = IXP425_NPE_C_IMAGEID, 170 .regbase = IXP425_MAC_B_HWBASE, 171 .regsize = IXP425_MAC_B_SIZE, 172 .miibase = IXP425_MAC_A_HWBASE, 173 .miisize = IXP425_MAC_A_SIZE, 174 .rx_qid = 12, 175 .rx_freeqid = 28, 176 .tx_qid = 25, 177 .tx_doneqid = 31 178 }, 179 }; 180 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 181 182 static __inline uint32_t 183 RD4(struct npe_softc *sc, bus_size_t off) 184 { 185 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 186 } 187 188 static __inline void 189 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 190 { 191 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 192 } 193 194 static int npe_activate(struct npe_softc *); 195 #if 0 196 static void npe_deactivate(struct npe_softc *); 197 #endif 198 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 199 static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 200 static void npe_getmac(struct npe_softc *sc); 201 static void npe_txdone(int qid, void *arg); 202 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 203 struct mbuf *); 204 static void npe_rxdone(int qid, void *arg); 205 static void npeinit_macreg(struct npe_softc *); 206 static int npeinit(struct ifnet *); 207 static void npeinit_resetcb(void *); 208 static void npeinit_locked(void *); 209 static void npestart(struct ifnet *); 210 static void npestop(struct ifnet *, int); 211 static void npewatchdog(struct ifnet *); 212 static int npeioctl(struct ifnet * ifp, u_long, void *); 213 214 static int npe_setrxqosentry(struct npe_softc *, int classix, 215 int trafclass, int qid); 216 static int npe_updatestats(struct npe_softc *); 217 #if 0 218 static int npe_getstats(struct npe_softc *); 219 static uint32_t npe_getimageid(struct npe_softc *); 220 static int npe_setloopback(struct npe_softc *, int ena); 221 #endif 222 223 static int npe_miibus_readreg(device_t, int, int); 224 static void npe_miibus_writereg(device_t, int, int, int); 225 static void npe_miibus_statchg(struct ifnet *); 226 227 static int npe_debug; 228 #define DPRINTF(sc, fmt, ...) do { \ 229 if (npe_debug) printf(fmt, __VA_ARGS__); \ 230 } while (0) 231 #define DPRINTFn(n, sc, fmt, ...) do { \ 232 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 233 } while (0) 234 235 #define NPE_TXBUF 128 236 #define NPE_RXBUF 64 237 238 #ifndef ETHER_ALIGN 239 #define ETHER_ALIGN 2 /* XXX: Ditch this */ 240 #endif 241 242 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 243 + ((uint64_t)addr[1] << 32) \ 244 + ((uint64_t)addr[2] << 24) \ 245 + ((uint64_t)addr[3] << 16) \ 246 + ((uint64_t)addr[4] << 8) \ 247 + (uint64_t)addr[5]) 248 249 /* NB: all tx done processing goes through one queue */ 250 static int tx_doneqid = -1; 251 252 void (*npe_getmac_md)(int, uint8_t *); 253 254 static int npe_match(device_t, cfdata_t, void *); 255 static void npe_attach(device_t, device_t, void *); 256 257 CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 258 npe_match, npe_attach, NULL, NULL); 259 260 static int 261 npe_match(device_t parent, cfdata_t cf, void *arg) 262 { 263 struct ixpnpe_attach_args *na = arg; 264 265 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 266 } 267 268 static void 269 npe_attach(device_t parent, device_t self, void *arg) 270 { 271 struct npe_softc *sc = device_private(self); 272 struct ixpnpe_softc *isc = device_private(parent); 273 struct ixpnpe_attach_args *na = arg; 274 struct ifnet *ifp; 275 276 aprint_naive("\n"); 277 aprint_normal(": Ethernet co-processor\n"); 278 279 sc->sc_dev = self; 280 sc->sc_iot = na->na_iot; 281 sc->sc_dt = na->na_dt; 282 sc->sc_npe = na->na_npe; 283 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 284 sc->sc_phy = na->na_phy; 285 286 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 287 memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 288 289 callout_init(&sc->sc_tick_ch, 0); 290 291 if (npe_activate(sc)) { 292 aprint_error_dev(sc->sc_dev, 293 "Failed to activate NPE (missing microcode?)\n"); 294 return; 295 } 296 297 npe_getmac(sc); 298 npeinit_macreg(sc); 299 300 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 301 ether_sprintf(sc->sc_enaddr)); 302 303 ifp = &sc->sc_ethercom.ec_if; 304 sc->sc_mii.mii_ifp = ifp; 305 sc->sc_mii.mii_readreg = npe_miibus_readreg; 306 sc->sc_mii.mii_writereg = npe_miibus_writereg; 307 sc->sc_mii.mii_statchg = npe_miibus_statchg; 308 sc->sc_ethercom.ec_mii = &sc->sc_mii; 309 310 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 311 npe_ifmedia_status); 312 313 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 314 MII_OFFSET_ANY, MIIF_DOPAUSE); 315 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 316 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 317 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 318 } else 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 320 321 ifp->if_softc = sc; 322 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_start = npestart; 325 ifp->if_ioctl = npeioctl; 326 ifp->if_watchdog = npewatchdog; 327 ifp->if_init = npeinit; 328 ifp->if_stop = npestop; 329 IFQ_SET_READY(&ifp->if_snd); 330 331 /* VLAN capable */ 332 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 333 334 if_attach(ifp); 335 if_deferred_start_init(ifp, NULL); 336 ether_ifattach(ifp, sc->sc_enaddr); 337 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 338 RND_TYPE_NET, RND_FLAG_DEFAULT); 339 340 /* callback function to reset MAC */ 341 isc->macresetcbfunc = npeinit_resetcb; 342 isc->macresetcbarg = sc; 343 } 344 345 /* 346 * Compute and install the multicast filter. 347 */ 348 static void 349 npe_setmcast(struct npe_softc *sc) 350 { 351 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 352 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 353 uint32_t reg; 354 uint32_t msg[2]; 355 int i; 356 357 /* Always use filter. Is here a correct position? */ 358 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 359 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 360 361 if (ifp->if_flags & IFF_PROMISC) { 362 memset(mask, 0, ETHER_ADDR_LEN); 363 memset(addr, 0, ETHER_ADDR_LEN); 364 } else if (ifp->if_flags & IFF_ALLMULTI) { 365 static const uint8_t allmulti[ETHER_ADDR_LEN] = 366 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 367 all_multi: 368 memcpy(mask, allmulti, ETHER_ADDR_LEN); 369 memcpy(addr, allmulti, ETHER_ADDR_LEN); 370 } else { 371 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 372 struct ether_multistep step; 373 struct ether_multi *enm; 374 375 memset(clr, 0, ETHER_ADDR_LEN); 376 memset(set, 0xff, ETHER_ADDR_LEN); 377 378 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 379 while (enm != NULL) { 380 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 381 ifp->if_flags |= IFF_ALLMULTI; 382 goto all_multi; 383 } 384 385 for (i = 0; i < ETHER_ADDR_LEN; i++) { 386 clr[i] |= enm->enm_addrlo[i]; 387 set[i] &= enm->enm_addrlo[i]; 388 } 389 390 ETHER_NEXT_MULTI(step, enm); 391 } 392 393 for (i = 0; i < ETHER_ADDR_LEN; i++) { 394 mask[i] = set[i] | ~clr[i]; 395 addr[i] = set[i]; 396 } 397 } 398 399 /* 400 * Write the mask and address registers. 401 */ 402 for (i = 0; i < ETHER_ADDR_LEN; i++) { 403 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 404 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 405 } 406 407 msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 408 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 409 msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 410 | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 411 | (addr[5] << 8) | mask[5]; 412 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 413 } 414 415 static int 416 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 417 const char *name, int nbuf, int maxseg) 418 { 419 bus_dma_segment_t seg; 420 int rseg, error, i; 421 void *hwbuf; 422 size_t size; 423 424 memset(dma, 0, sizeof(*dma)); 425 426 dma->name = name; 427 dma->nbuf = nbuf; 428 429 size = nbuf * sizeof(struct npehwbuf); 430 431 /* XXX COHERENT for now */ 432 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 433 1, &rseg, BUS_DMA_NOWAIT); 434 if (error) { 435 aprint_error_dev(sc->sc_dev, 436 "unable to %s for %s %s buffers, error %u\n", 437 "allocate memory", dma->name, "h/w", error); 438 } 439 440 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 441 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 442 if (error) { 443 aprint_error_dev(sc->sc_dev, 444 "unable to %s for %s %s buffers, error %u\n", 445 "map memory", dma->name, "h/w", error); 446 free_dmamem: 447 bus_dmamem_free(sc->sc_dt, &seg, rseg); 448 return error; 449 } 450 dma->hwbuf = (void *)hwbuf; 451 452 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 453 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 454 if (error) { 455 aprint_error_dev(sc->sc_dev, 456 "unable to %s for %s %s buffers, error %u\n", 457 "create map", dma->name, "h/w", error); 458 unmap_dmamem: 459 dma->hwbuf = NULL; 460 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 461 goto free_dmamem; 462 } 463 464 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 465 BUS_DMA_NOWAIT); 466 if (error) { 467 aprint_error_dev(sc->sc_dev, 468 "unable to %s for %s %s buffers, error %u\n", 469 "load map", dma->name, "h/w", error); 470 destroy_dmamap: 471 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 472 goto unmap_dmamem; 473 } 474 475 /* XXX M_TEMP */ 476 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 477 if (dma->buf == NULL) { 478 aprint_error_dev(sc->sc_dev, 479 "unable to %s for %s %s buffers, error %u\n", 480 "allocate memory", dma->name, "h/w", error); 481 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 482 error = ENOMEM; 483 goto destroy_dmamap; 484 } 485 486 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 487 for (i = 0; i < dma->nbuf; i++) { 488 struct npebuf *npe = &dma->buf[i]; 489 struct npehwbuf *hw = &dma->hwbuf[i]; 490 491 /* calculate offset to shared area */ 492 npe->ix_neaddr = dma->buf_phys + 493 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 494 KASSERT((npe->ix_neaddr & 0x1f) == 0); 495 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 496 MCLBYTES, 0, 0, &npe->ix_map); 497 if (error != 0) { 498 aprint_error_dev(sc->sc_dev, 499 "unable to %s for %s buffer %u, error %u\n", 500 "create dmamap", dma->name, i, error); 501 /* XXXSCW: Free up maps... */ 502 return error; 503 } 504 npe->ix_hw = hw; 505 } 506 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 507 BUS_DMASYNC_PREWRITE); 508 return 0; 509 } 510 511 #if 0 512 static void 513 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 514 { 515 int i; 516 517 /* XXXSCW: Clean this up */ 518 519 if (dma->hwbuf != NULL) { 520 for (i = 0; i < dma->nbuf; i++) { 521 struct npebuf *npe = &dma->buf[i]; 522 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 523 } 524 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 525 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 526 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 527 } 528 if (dma->buf != NULL) 529 free(dma->buf, M_TEMP); 530 memset(dma, 0, sizeof(*dma)); 531 } 532 #endif 533 534 static int 535 npe_activate(struct npe_softc *sc) 536 { 537 bus_dma_segment_t seg; 538 int unit = sc->sc_unit; 539 int error, i, rseg; 540 void *statbuf; 541 542 /* load NPE firmware and start it running */ 543 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 544 if (error != 0) 545 return error; 546 547 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 548 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 549 aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 550 npeconfig[unit].regbase, npeconfig[unit].regsize); 551 return ENOMEM; 552 } 553 554 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 555 /* 556 * The PHY's are only accessible from one MAC (it appears) 557 * so for other MAC's setup an additional mapping for 558 * frobbing the PHY registers. 559 */ 560 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 561 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 562 aprint_error_dev(sc->sc_dev, 563 "Cannot map MII registers 0x%x:0x%x\n", 564 npeconfig[unit].miibase, npeconfig[unit].miisize); 565 return ENOMEM; 566 } 567 } else 568 sc->sc_miih = sc->sc_ioh; 569 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 570 if (error != 0) 571 return error; 572 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 573 if (error != 0) 574 return error; 575 576 /* setup statistics block */ 577 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 578 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 579 if (error) { 580 aprint_error_dev(sc->sc_dev, 581 "unable to %s for %s, error %u\n", 582 "allocate memory", "stats block", error); 583 return error; 584 } 585 586 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 587 &statbuf, BUS_DMA_NOWAIT); 588 if (error) { 589 aprint_error_dev(sc->sc_dev, 590 "unable to %s for %s, error %u\n", 591 "map memory", "stats block", error); 592 return error; 593 } 594 sc->sc_stats = (void *)statbuf; 595 596 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 597 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 598 &sc->sc_stats_map); 599 if (error) { 600 aprint_error_dev(sc->sc_dev, 601 "unable to %s for %s, error %u\n", 602 "create map", "stats block", error); 603 return error; 604 } 605 606 error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 607 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 608 if (error) { 609 aprint_error_dev(sc->sc_dev, 610 "unable to %s for %s, error %u\n", 611 "load map", "stats block", error); 612 return error; 613 } 614 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 615 616 /* XXX disable half-bridge LEARNING+FILTERING feature */ 617 618 /* 619 * Setup h/w rx/tx queues. There are four q's: 620 * rx inbound q of rx'd frames 621 * rx_free pool of ixpbuf's for receiving frames 622 * tx outbound q of frames to send 623 * tx_done q of tx frames that have been processed 624 * 625 * The NPE handles the actual tx/rx process and the q manager 626 * handles the queues. The driver just writes entries to the 627 * q manager mailbox's and gets callbacks when there are rx'd 628 * frames to process or tx'd frames to reap. These callbacks 629 * are controlled by the q configurations; e.g. we get a 630 * callback when tx_done has 2 or more frames to process and 631 * when the rx q has at least one frame. These setings can 632 * changed at the time the q is configured. 633 */ 634 sc->rx_qid = npeconfig[unit].rx_qid; 635 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 636 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 637 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 638 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 639 /* tell the NPE to direct all traffic to rx_qid */ 640 #if 0 641 for (i = 0; i < 8; i++) 642 #else 643 printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 644 for (i = 0; i < 4; i++) 645 #endif 646 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 647 648 sc->tx_qid = npeconfig[unit].tx_qid; 649 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 650 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 651 if (tx_doneqid == -1) { 652 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 653 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 654 tx_doneqid = sc->tx_doneqid; 655 } 656 657 KASSERT(npes[npeconfig[unit].npeid] == NULL); 658 npes[npeconfig[unit].npeid] = sc; 659 660 return 0; 661 } 662 663 #if 0 664 static void 665 npe_deactivate(struct npe_softc *sc); 666 { 667 int unit = sc->sc_unit; 668 669 npes[npeconfig[unit].npeid] = NULL; 670 671 /* XXX disable q's */ 672 if (sc->sc_npe != NULL) 673 ixpnpe_stop(sc->sc_npe); 674 if (sc->sc_stats != NULL) { 675 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 676 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 677 sc->sc_stats_map); 678 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 679 } 680 if (sc->sc_stats_tag != NULL) 681 bus_dma_tag_destroy(sc->sc_stats_tag); 682 npe_dma_destroy(sc, &sc->txdma); 683 npe_dma_destroy(sc, &sc->rxdma); 684 bus_generic_detach(sc->sc_dev); 685 if (sc->sc_mii) 686 device_delete_child(sc->sc_dev, sc->sc_mii); 687 #if 0 688 /* XXX sc_ioh and sc_miih */ 689 if (sc->mem_res) 690 bus_release_resource(dev, SYS_RES_IOPORT, 691 rman_get_rid(sc->mem_res), sc->mem_res); 692 sc->mem_res = 0; 693 #endif 694 } 695 #endif 696 697 /* 698 * Notify the world which media we're using. 699 */ 700 static void 701 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 702 { 703 struct npe_softc *sc = ifp->if_softc; 704 705 mii_pollstat(&sc->sc_mii); 706 707 ifmr->ifm_active = sc->sc_mii.mii_media_active; 708 ifmr->ifm_status = sc->sc_mii.mii_media_status; 709 } 710 711 static void 712 npe_addstats(struct npe_softc *sc) 713 { 714 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 715 struct npestats *ns = sc->sc_stats; 716 717 ifp->if_oerrors += 718 be32toh(ns->dot3StatsInternalMacTransmitErrors) 719 + be32toh(ns->dot3StatsCarrierSenseErrors) 720 + be32toh(ns->TxVLANIdFilterDiscards) 721 ; 722 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 723 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 724 + be32toh(ns->RxOverrunDiscards) 725 + be32toh(ns->RxUnderflowEntryDiscards) 726 ; 727 ifp->if_collisions += 728 be32toh(ns->dot3StatsSingleCollisionFrames) 729 + be32toh(ns->dot3StatsMultipleCollisionFrames) 730 ; 731 } 732 733 static void 734 npe_tick(void *xsc) 735 { 736 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 737 struct npe_softc *sc = xsc; 738 uint32_t msg[2]; 739 740 /* 741 * NB: to avoid sleeping with the softc lock held we 742 * split the NPE msg processing into two parts. The 743 * request for statistics is sent w/o waiting for a 744 * reply and then on the next tick we retrieve the 745 * results. This works because npe_tick is the only 746 * code that talks via the mailbox's (except at setup). 747 * This likely can be handled better. 748 */ 749 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 750 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 751 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 752 npe_addstats(sc); 753 } 754 npe_updatestats(sc); 755 mii_tick(&sc->sc_mii); 756 757 /* schedule next poll */ 758 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 759 #undef ACK 760 } 761 762 static void 763 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 764 { 765 766 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 767 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 768 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 769 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 770 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 771 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 772 } 773 774 static void 775 npe_getmac(struct npe_softc *sc) 776 { 777 uint8_t *eaddr = sc->sc_enaddr; 778 779 if (npe_getmac_md != NULL) { 780 (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 781 } else { 782 /* 783 * Some system's unicast address appears to be loaded from 784 * EEPROM on reset 785 */ 786 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 787 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 788 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 789 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 790 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 791 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 792 } 793 } 794 795 struct txdone { 796 struct npebuf *head; 797 struct npebuf **tail; 798 int count; 799 }; 800 801 static __inline void 802 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 803 { 804 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 805 806 *td->tail = sc->tx_free; 807 sc->tx_free = td->head; 808 /* 809 * We're no longer busy, so clear the busy flag and call the 810 * start routine to xmit more packets. 811 */ 812 ifp->if_opackets += td->count; 813 ifp->if_flags &= ~IFF_OACTIVE; 814 ifp->if_timer = 0; 815 if_schedule_deferred_start(ifp); 816 } 817 818 /* 819 * Q manager callback on tx done queue. Reap mbufs 820 * and return tx buffers to the free list. Finally 821 * restart output. Note the microcode has only one 822 * txdone q wired into it so we must use the NPE ID 823 * returned with each npehwbuf to decide where to 824 * send buffers. 825 */ 826 static void 827 npe_txdone(int qid, void *arg) 828 { 829 #define P2V(a, dma) \ 830 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 831 struct npe_softc *sc; 832 struct npebuf *npe; 833 struct txdone *td, q[NPE_MAX]; 834 uint32_t entry; 835 836 /* XXX no NPE-A support */ 837 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 838 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 839 /* XXX max # at a time? */ 840 while (ixpqmgr_qread(qid, &entry) == 0) { 841 sc = npes[NPE_QM_Q_NPE(entry)]; 842 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 843 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 844 rnd_add_uint32(&sc->rnd_source, entry); 845 846 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 847 m_freem(npe->ix_m); 848 npe->ix_m = NULL; 849 850 td = &q[NPE_QM_Q_NPE(entry)]; 851 *td->tail = npe; 852 td->tail = &npe->ix_next; 853 td->count++; 854 } 855 856 if (q[NPE_B].count) 857 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 858 if (q[NPE_C].count) 859 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 860 #undef P2V 861 } 862 863 static __inline struct mbuf * 864 npe_getcl(void) 865 { 866 struct mbuf *m; 867 868 MGETHDR(m, M_DONTWAIT, MT_DATA); 869 if (m != NULL) { 870 MCLGET(m, M_DONTWAIT); 871 if ((m->m_flags & M_EXT) == 0) { 872 m_freem(m); 873 m = NULL; 874 } 875 } 876 return (m); 877 } 878 879 static int 880 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 881 { 882 struct npehwbuf *hw; 883 int error; 884 885 if (m == NULL) { 886 m = npe_getcl(); 887 if (m == NULL) 888 return ENOBUFS; 889 } 890 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 891 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 892 /* backload payload and align ip hdr */ 893 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 894 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 895 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 896 BUS_DMA_READ|BUS_DMA_NOWAIT); 897 if (error != 0) { 898 m_freem(m); 899 return error; 900 } 901 hw = npe->ix_hw; 902 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 903 /* NB: NPE requires length be a multiple of 64 */ 904 /* NB: buffer length is shifted in word */ 905 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 906 hw->ix_ne[0].next = 0; 907 npe->ix_m = m; 908 /* Flush the memory in the mbuf */ 909 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 910 BUS_DMASYNC_PREREAD); 911 return 0; 912 } 913 914 /* 915 * RX q processing for a specific NPE. Claim entries 916 * from the hardware queue and pass the frames up the 917 * stack. Pass the rx buffers to the free list. 918 */ 919 static void 920 npe_rxdone(int qid, void *arg) 921 { 922 #define P2V(a, dma) \ 923 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 924 struct npe_softc *sc = arg; 925 struct npedma *dma = &sc->rxdma; 926 uint32_t entry; 927 928 while (ixpqmgr_qread(qid, &entry) == 0) { 929 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 930 struct mbuf *m; 931 932 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 933 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 934 rnd_add_uint32(&sc->rnd_source, entry); 935 /* 936 * Allocate a new mbuf to replenish the rx buffer. 937 * If doing so fails we drop the rx'd frame so we 938 * can reuse the previous mbuf. When we're able to 939 * allocate a new mbuf dispatch the mbuf w/ rx'd 940 * data up the stack and replace it with the newly 941 * allocated one. 942 */ 943 m = npe_getcl(); 944 if (m != NULL) { 945 struct mbuf *mrx = npe->ix_m; 946 struct npehwbuf *hw = npe->ix_hw; 947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 948 949 /* Flush mbuf memory for rx'd data */ 950 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 951 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 952 953 /* XXX flush hw buffer; works now 'cuz coherent */ 954 /* set m_len etc. per rx frame size */ 955 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 956 mrx->m_pkthdr.len = mrx->m_len; 957 m_set_rcvif(mrx, ifp); 958 /* Don't add M_HASFCS. See below */ 959 960 #if 1 961 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 962 log(LOG_INFO, "%s: too short frame (len=%d)\n", 963 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 964 /* Back out "newly allocated" mbuf. */ 965 m_freem(m); 966 ifp->if_ierrors++; 967 goto fail; 968 } 969 if ((ifp->if_flags & IFF_PROMISC) == 0) { 970 struct ether_header *eh; 971 972 /* 973 * Workaround for "Non-Intel XScale Technology 974 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 975 * matches the filter (both unicast and 976 * multicast). 977 */ 978 eh = mtod(mrx, struct ether_header *); 979 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 980 /* unicast */ 981 982 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 983 /* discard it */ 984 #if 0 985 printf("discard it\n"); 986 #endif 987 /* 988 * Back out "newly allocated" 989 * mbuf. 990 */ 991 m_freem(m); 992 goto fail; 993 } 994 } else if (memcmp(eh->ether_dhost, 995 etherbroadcastaddr, 6) == 0) { 996 /* Always accept broadcast packet*/ 997 } else { 998 struct ethercom *ec = &sc->sc_ethercom; 999 struct ether_multi *enm; 1000 struct ether_multistep step; 1001 int match = 0; 1002 1003 /* multicast */ 1004 1005 ETHER_FIRST_MULTI(step, ec, enm); 1006 while (enm != NULL) { 1007 uint64_t lowint, highint, dest; 1008 1009 lowint = MAC2UINT64(enm->enm_addrlo); 1010 highint = MAC2UINT64(enm->enm_addrhi); 1011 dest = MAC2UINT64(eh->ether_dhost); 1012 #if 0 1013 printf("%llx\n", lowint); 1014 printf("%llx\n", dest); 1015 printf("%llx\n", highint); 1016 #endif 1017 if ((lowint <= dest) && (dest <= highint)) { 1018 match = 1; 1019 break; 1020 } 1021 ETHER_NEXT_MULTI(step, enm); 1022 } 1023 if (match == 0) { 1024 /* discard it */ 1025 #if 0 1026 printf("discard it(M)\n"); 1027 #endif 1028 /* 1029 * Back out "newly allocated" 1030 * mbuf. 1031 */ 1032 m_freem(m); 1033 goto fail; 1034 } 1035 } 1036 } 1037 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1038 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1039 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 1040 /* Back out "newly allocated" mbuf. */ 1041 m_freem(m); 1042 ifp->if_ierrors++; 1043 goto fail; 1044 } 1045 #endif 1046 1047 /* 1048 * Trim FCS! 1049 * NPE always adds the FCS by this driver's setting, 1050 * so we always trim it here and not add M_HASFCS. 1051 */ 1052 m_adj(mrx, -ETHER_CRC_LEN); 1053 1054 /* 1055 * Tap off here if there is a bpf listener. 1056 */ 1057 1058 if_percpuq_enqueue(ifp->if_percpuq, mrx); 1059 } else { 1060 fail: 1061 /* discard frame and re-use mbuf */ 1062 m = npe->ix_m; 1063 } 1064 if (npe_rxbuf_init(sc, npe, m) == 0) { 1065 /* return npe buf to rx free list */ 1066 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1067 } else { 1068 /* XXX should not happen */ 1069 } 1070 } 1071 #undef P2V 1072 } 1073 1074 static void 1075 npe_startxmit(struct npe_softc *sc) 1076 { 1077 struct npedma *dma = &sc->txdma; 1078 int i; 1079 1080 sc->tx_free = NULL; 1081 for (i = 0; i < dma->nbuf; i++) { 1082 struct npebuf *npe = &dma->buf[i]; 1083 if (npe->ix_m != NULL) { 1084 /* NB: should not happen */ 1085 printf("%s: %s: free mbuf at entry %u\n", 1086 device_xname(sc->sc_dev), __func__, i); 1087 m_freem(npe->ix_m); 1088 } 1089 npe->ix_m = NULL; 1090 npe->ix_next = sc->tx_free; 1091 sc->tx_free = npe; 1092 } 1093 } 1094 1095 static void 1096 npe_startrecv(struct npe_softc *sc) 1097 { 1098 struct npedma *dma = &sc->rxdma; 1099 struct npebuf *npe; 1100 int i; 1101 1102 for (i = 0; i < dma->nbuf; i++) { 1103 npe = &dma->buf[i]; 1104 npe_rxbuf_init(sc, npe, npe->ix_m); 1105 /* set npe buf on rx free list */ 1106 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1107 } 1108 } 1109 1110 static void 1111 npeinit_macreg(struct npe_softc *sc) 1112 { 1113 1114 /* 1115 * Reset MAC core. 1116 */ 1117 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1118 DELAY(NPE_MAC_RESET_DELAY); 1119 /* configure MAC to generate MDC clock */ 1120 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1121 1122 /* disable transmitter and reciver in the MAC */ 1123 WR4(sc, NPE_MAC_RX_CNTRL1, 1124 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1125 WR4(sc, NPE_MAC_TX_CNTRL1, 1126 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1127 1128 /* 1129 * Set the MAC core registers. 1130 */ 1131 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1132 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1133 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1134 /* thresholds determined by NPE firmware FS */ 1135 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1136 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1137 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1138 /* tx fifo threshold (bytes) */ 1139 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1140 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1141 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1142 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1143 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1144 /* assumes MII mode */ 1145 WR4(sc, NPE_MAC_TX_CNTRL1, 1146 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1147 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1148 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1149 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1150 /* XXX pad strip? */ 1151 WR4(sc, NPE_MAC_RX_CNTRL1, 1152 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1153 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1154 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1155 } 1156 1157 static void 1158 npeinit_resetcb(void *xsc) 1159 { 1160 struct npe_softc *sc = xsc; 1161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162 uint32_t msg[2]; 1163 1164 ifp->if_oerrors++; 1165 npeinit_locked(sc); 1166 1167 msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1168 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1169 msg[1] = 0; 1170 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1171 } 1172 1173 /* 1174 * Reset and initialize the chip 1175 */ 1176 static void 1177 npeinit_locked(void *xsc) 1178 { 1179 struct npe_softc *sc = xsc; 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 1182 /* Cancel any pending I/O. */ 1183 npestop(ifp, 0); 1184 1185 /* Reset the chip to a known state. */ 1186 npeinit_macreg(sc); 1187 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1188 ether_mediachange(ifp); 1189 npe_setmcast(sc); 1190 1191 npe_startxmit(sc); 1192 npe_startrecv(sc); 1193 1194 ifp->if_flags |= IFF_RUNNING; 1195 ifp->if_flags &= ~IFF_OACTIVE; 1196 ifp->if_timer = 0; /* just in case */ 1197 1198 /* enable transmitter and reciver in the MAC */ 1199 WR4(sc, NPE_MAC_RX_CNTRL1, 1200 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1201 WR4(sc, NPE_MAC_TX_CNTRL1, 1202 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1203 1204 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1205 } 1206 1207 static int 1208 npeinit(struct ifnet *ifp) 1209 { 1210 struct npe_softc *sc = ifp->if_softc; 1211 int s; 1212 1213 s = splnet(); 1214 npeinit_locked(sc); 1215 splx(s); 1216 1217 return (0); 1218 } 1219 1220 /* 1221 * Defragment an mbuf chain, returning at most maxfrags separate 1222 * mbufs+clusters. If this is not possible NULL is returned and 1223 * the original mbuf chain is left in its present (potentially 1224 * modified) state. We use two techniques: collapsing consecutive 1225 * mbufs and replacing consecutive mbufs by a cluster. 1226 */ 1227 static __inline struct mbuf * 1228 npe_defrag(struct mbuf *m0) 1229 { 1230 struct mbuf *m; 1231 1232 MGETHDR(m, M_DONTWAIT, MT_DATA); 1233 if (m == NULL) 1234 return (NULL); 1235 M_COPY_PKTHDR(m, m0); 1236 1237 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1238 MCLGET(m, M_DONTWAIT); 1239 if ((m->m_flags & M_EXT) == 0) { 1240 m_freem(m); 1241 return (NULL); 1242 } 1243 } 1244 1245 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1246 m_freem(m0); 1247 1248 return (m); 1249 } 1250 1251 /* 1252 * Dequeue packets and place on the h/w transmit queue. 1253 */ 1254 static void 1255 npestart(struct ifnet *ifp) 1256 { 1257 struct npe_softc *sc = ifp->if_softc; 1258 struct npebuf *npe; 1259 struct npehwbuf *hw; 1260 struct mbuf *m, *n; 1261 bus_dma_segment_t *segs; 1262 int nseg, len, error, i; 1263 uint32_t next; 1264 1265 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1266 return; 1267 1268 while (sc->tx_free != NULL) { 1269 IFQ_DEQUEUE(&ifp->if_snd, m); 1270 if (m == NULL) 1271 break; 1272 npe = sc->tx_free; 1273 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1274 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1275 if (error == EFBIG) { 1276 n = npe_defrag(m); 1277 if (n == NULL) { 1278 printf("%s: %s: too many fragments\n", 1279 device_xname(sc->sc_dev), __func__); 1280 m_freem(m); 1281 return; /* XXX? */ 1282 } 1283 m = n; 1284 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1285 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1286 } 1287 if (error != 0) { 1288 printf("%s: %s: error %u\n", 1289 device_xname(sc->sc_dev), __func__, error); 1290 m_freem(m); 1291 return; /* XXX? */ 1292 } 1293 sc->tx_free = npe->ix_next; 1294 1295 /* 1296 * Tap off here if there is a bpf listener. 1297 */ 1298 bpf_mtap(ifp, m, BPF_D_OUT); 1299 1300 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1301 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1302 1303 npe->ix_m = m; 1304 hw = npe->ix_hw; 1305 len = m->m_pkthdr.len; 1306 nseg = npe->ix_map->dm_nsegs; 1307 segs = npe->ix_map->dm_segs; 1308 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1309 for (i = 0; i < nseg; i++) { 1310 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1311 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1312 hw->ix_ne[i].next = htobe32(next); 1313 1314 len = 0; /* zero for segments > 1 */ 1315 next += sizeof(hw->ix_ne[0]); 1316 } 1317 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1318 /* XXX flush descriptor instead of using uncached memory */ 1319 1320 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1321 __func__, sc->tx_qid, npe->ix_neaddr, 1322 hw->ix_ne[0].data, hw->ix_ne[0].len); 1323 /* stick it on the tx q */ 1324 /* XXX add vlan priority */ 1325 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1326 1327 ifp->if_timer = 5; 1328 } 1329 if (sc->tx_free == NULL) 1330 ifp->if_flags |= IFF_OACTIVE; 1331 } 1332 1333 static void 1334 npe_stopxmit(struct npe_softc *sc) 1335 { 1336 struct npedma *dma = &sc->txdma; 1337 int i; 1338 1339 /* XXX qmgr */ 1340 for (i = 0; i < dma->nbuf; i++) { 1341 struct npebuf *npe = &dma->buf[i]; 1342 1343 if (npe->ix_m != NULL) { 1344 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1345 m_freem(npe->ix_m); 1346 npe->ix_m = NULL; 1347 } 1348 } 1349 } 1350 1351 static void 1352 npe_stoprecv(struct npe_softc *sc) 1353 { 1354 struct npedma *dma = &sc->rxdma; 1355 int i; 1356 1357 /* XXX qmgr */ 1358 for (i = 0; i < dma->nbuf; i++) { 1359 struct npebuf *npe = &dma->buf[i]; 1360 1361 if (npe->ix_m != NULL) { 1362 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1363 m_freem(npe->ix_m); 1364 npe->ix_m = NULL; 1365 } 1366 } 1367 } 1368 1369 /* 1370 * Turn off interrupts, and stop the nic. 1371 */ 1372 void 1373 npestop(struct ifnet *ifp, int disable) 1374 { 1375 struct npe_softc *sc = ifp->if_softc; 1376 1377 /* disable transmitter and reciver in the MAC */ 1378 WR4(sc, NPE_MAC_RX_CNTRL1, 1379 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1380 WR4(sc, NPE_MAC_TX_CNTRL1, 1381 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1382 1383 callout_stop(&sc->sc_tick_ch); 1384 1385 npe_stopxmit(sc); 1386 npe_stoprecv(sc); 1387 /* XXX go into loopback & drain q's? */ 1388 /* XXX but beware of disabling tx above */ 1389 1390 /* 1391 * The MAC core rx/tx disable may leave the MAC hardware in an 1392 * unpredictable state. A hw reset is executed before resetting 1393 * all the MAC parameters to a known value. 1394 */ 1395 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1396 DELAY(NPE_MAC_RESET_DELAY); 1397 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1398 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1399 1400 ifp->if_timer = 0; 1401 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1402 } 1403 1404 void 1405 npewatchdog(struct ifnet *ifp) 1406 { 1407 struct npe_softc *sc = ifp->if_softc; 1408 int s; 1409 1410 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1411 s = splnet(); 1412 ifp->if_oerrors++; 1413 npeinit_locked(sc); 1414 splx(s); 1415 } 1416 1417 static int 1418 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1419 { 1420 struct npe_softc *sc = ifp->if_softc; 1421 struct ifreq *ifr = (struct ifreq *) data; 1422 int s, error = 0; 1423 1424 s = splnet(); 1425 1426 switch (cmd) { 1427 case SIOCSIFMEDIA: 1428 case SIOCGIFMEDIA: 1429 #if 0 /* not yet */ 1430 /* Flow control requires full-duplex mode. */ 1431 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1432 (ifr->ifr_media & IFM_FDX) == 0) 1433 ifr->ifr_media &= ~IFM_ETH_FMASK; 1434 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1435 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1436 /* We can do both TXPAUSE and RXPAUSE. */ 1437 ifr->ifr_media |= 1438 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1439 } 1440 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1441 } 1442 #endif 1443 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1444 break; 1445 case SIOCSIFFLAGS: 1446 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) { 1447 /* 1448 * If interface is marked down and it is running, 1449 * then stop and disable it. 1450 */ 1451 (*ifp->if_stop)(ifp, 1); 1452 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) { 1453 /* 1454 * If interface is marked up and it is stopped, then 1455 * start it. 1456 */ 1457 error = (*ifp->if_init)(ifp); 1458 } else if ((ifp->if_flags & IFF_UP) != 0) { 1459 int diff; 1460 1461 /* Up (AND RUNNING). */ 1462 1463 diff = (ifp->if_flags ^ sc->sc_if_flags) 1464 & (IFF_PROMISC|IFF_ALLMULTI); 1465 if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 1466 /* 1467 * If the difference bettween last flag and 1468 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1469 * set multicast filter only (don't reset to 1470 * prevent link down). 1471 */ 1472 npe_setmcast(sc); 1473 } else { 1474 /* 1475 * Reset the interface to pick up changes in 1476 * any other flags that affect the hardware 1477 * state. 1478 */ 1479 error = (*ifp->if_init)(ifp); 1480 } 1481 } 1482 sc->sc_if_flags = ifp->if_flags; 1483 break; 1484 default: 1485 error = ether_ioctl(ifp, cmd, data); 1486 if (error == ENETRESET) { 1487 /* 1488 * Multicast list has changed; set the hardware filter 1489 * accordingly. 1490 */ 1491 npe_setmcast(sc); 1492 error = 0; 1493 } 1494 } 1495 1496 npestart(ifp); 1497 1498 splx(s); 1499 return error; 1500 } 1501 1502 /* 1503 * Setup a traffic class -> rx queue mapping. 1504 */ 1505 static int 1506 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1507 { 1508 int npeid = npeconfig[sc->sc_unit].npeid; 1509 uint32_t msg[2]; 1510 1511 msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1512 | classix; 1513 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1514 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1515 } 1516 1517 /* 1518 * Update and reset the statistics in the NPE. 1519 */ 1520 static int 1521 npe_updatestats(struct npe_softc *sc) 1522 { 1523 uint32_t msg[2]; 1524 1525 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1526 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1527 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1528 } 1529 1530 #if 0 1531 /* 1532 * Get the current statistics block. 1533 */ 1534 static int 1535 npe_getstats(struct npe_softc *sc) 1536 { 1537 uint32_t msg[2]; 1538 1539 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1540 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1541 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1542 } 1543 1544 /* 1545 * Query the image id of the loaded firmware. 1546 */ 1547 static uint32_t 1548 npe_getimageid(struct npe_softc *sc) 1549 { 1550 uint32_t msg[2]; 1551 1552 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1553 msg[1] = 0; 1554 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1555 } 1556 1557 /* 1558 * Enable/disable loopback. 1559 */ 1560 static int 1561 npe_setloopback(struct npe_softc *sc, int ena) 1562 { 1563 uint32_t msg[2]; 1564 1565 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1566 msg[1] = 0; 1567 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1568 } 1569 #endif 1570 1571 /* 1572 * MII bus support routines. 1573 * 1574 * NB: ixp425 has one PHY per NPE 1575 */ 1576 static uint32_t 1577 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1578 { 1579 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1580 uint32_t v; 1581 1582 /* NB: registers are known to be sequential */ 1583 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1584 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1585 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1586 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1587 return v; 1588 #undef MII_RD4 1589 } 1590 1591 static void 1592 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1593 { 1594 #define MII_WR4(sc, reg, v) \ 1595 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1596 1597 /* NB: registers are known to be sequential */ 1598 MII_WR4(sc, reg+0, cmd & 0xff); 1599 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1600 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1601 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1602 #undef MII_WR4 1603 } 1604 1605 static int 1606 npe_mii_mdio_wait(struct npe_softc *sc) 1607 { 1608 #define MAXTRIES 100 /* XXX */ 1609 uint32_t v; 1610 int i; 1611 1612 for (i = 0; i < MAXTRIES; i++) { 1613 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1614 if ((v & NPE_MII_GO) == 0) 1615 return 1; 1616 } 1617 return 0; /* NB: timeout */ 1618 #undef MAXTRIES 1619 } 1620 1621 static int 1622 npe_miibus_readreg(device_t self, int phy, int reg) 1623 { 1624 struct npe_softc *sc = device_private(self); 1625 uint32_t v; 1626 1627 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1628 return 0xffff; 1629 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1630 | NPE_MII_GO; 1631 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1632 if (npe_mii_mdio_wait(sc)) 1633 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1634 else 1635 v = 0xffff | NPE_MII_READ_FAIL; 1636 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1637 #undef MAXTRIES 1638 } 1639 1640 static void 1641 npe_miibus_writereg(device_t self, int phy, int reg, int data) 1642 { 1643 struct npe_softc *sc = device_private(self); 1644 uint32_t v; 1645 1646 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1647 return; 1648 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1649 | data | NPE_MII_WRITE 1650 | NPE_MII_GO; 1651 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1652 /* XXX complain about timeout */ 1653 (void) npe_mii_mdio_wait(sc); 1654 } 1655 1656 static void 1657 npe_miibus_statchg(struct ifnet *ifp) 1658 { 1659 struct npe_softc *sc = ifp->if_softc; 1660 uint32_t tx1, rx1; 1661 uint32_t randoff; 1662 1663 /* sync MAC duplex state */ 1664 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1665 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1666 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1667 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1668 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1669 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1670 } else { 1671 struct timeval now; 1672 getmicrotime(&now); 1673 randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1674 & 0x7f; 1675 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1676 + randoff); 1677 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1678 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1679 } 1680 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1681 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1682 } 1683
Indexes created Thu Oct 02 10:09:58 GMT 2025