ixp425_if_npe.c revision 1.40
1 /* $NetBSD: ixp425_if_npe.c,v 1.40 2019/05/23 10:40:39 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.40 2019/05/23 10:40:39 msaitoh Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/socket.h> 58 #include <sys/endian.h> 59 #include <sys/ioctl.h> 60 #include <sys/syslog.h> 61 #include <sys/bus.h> 62 #include <sys/rndsource.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 #include <net/bpf.h> 69 70 #include <arm/xscale/ixp425reg.h> 71 #include <arm/xscale/ixp425var.h> 72 #include <arm/xscale/ixp425_qmgr.h> 73 #include <arm/xscale/ixp425_npevar.h> 74 #include <arm/xscale/ixp425_if_npereg.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include "locators.h" 79 80 struct npebuf { 81 struct npebuf *ix_next; /* chain to next buffer */ 82 void *ix_m; /* backpointer to mbuf */ 83 bus_dmamap_t ix_map; /* bus dma map for associated data */ 84 struct npehwbuf *ix_hw; /* associated h/w block */ 85 uint32_t ix_neaddr; /* phys address of ix_hw */ 86 }; 87 88 struct npedma { 89 const char* name; 90 int nbuf; /* # npebuf's allocated */ 91 bus_dmamap_t m_map; 92 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 93 bus_dmamap_t buf_map; 94 bus_addr_t buf_phys; /* phys addr of buffers */ 95 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 96 }; 97 98 struct npe_softc { 99 device_t sc_dev; 100 struct ethercom sc_ethercom; 101 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 102 struct mii_data sc_mii; 103 bus_space_tag_t sc_iot; 104 bus_dma_tag_t sc_dt; 105 bus_space_handle_t sc_ioh; /* MAC register window */ 106 bus_space_handle_t sc_miih; /* MII register window */ 107 struct ixpnpe_softc *sc_npe; /* NPE support */ 108 int sc_unit; 109 int sc_phy; 110 struct callout sc_tick_ch; /* Tick callout */ 111 struct npedma txdma; 112 struct npebuf *tx_free; /* list of free tx buffers */ 113 struct npedma rxdma; 114 int rx_qid; /* rx qid */ 115 int rx_freeqid; /* rx free buffers qid */ 116 int tx_qid; /* tx qid */ 117 int tx_doneqid; /* tx completed qid */ 118 struct npestats *sc_stats; 119 bus_dmamap_t sc_stats_map; 120 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 121 int sc_if_flags; /* keep last if_flags */ 122 krndsource_t rnd_source; /* random source */ 123 }; 124 125 /* 126 * Per-unit static configuration for IXP425. The tx and 127 * rx free Q id's are fixed by the NPE microcode. The 128 * rx Q id's are programmed to be separate to simplify 129 * multi-port processing. It may be better to handle 130 * all traffic through one Q (as done by the Intel drivers). 131 * 132 * Note that the PHY's are accessible only from MAC A 133 * on the IXP425. This and other platform-specific 134 * assumptions probably need to be handled through hints. 135 */ 136 static const struct { 137 const char *desc; /* device description */ 138 int npeid; /* NPE assignment */ 139 int macport; /* Port number of the MAC */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .macport = 0x10, 153 .imageid = IXP425_NPE_B_IMAGEID, 154 .regbase = IXP425_MAC_A_HWBASE, 155 .regsize = IXP425_MAC_A_SIZE, 156 .miibase = IXP425_MAC_A_HWBASE, 157 .miisize = IXP425_MAC_A_SIZE, 158 .rx_qid = 4, 159 .rx_freeqid = 27, 160 .tx_qid = 24, 161 .tx_doneqid = 31 162 }, 163 { .desc = "IXP NPE-C", 164 .npeid = NPE_C, 165 .macport = 0x20, 166 .imageid = IXP425_NPE_C_IMAGEID, 167 .regbase = IXP425_MAC_B_HWBASE, 168 .regsize = IXP425_MAC_B_SIZE, 169 .miibase = IXP425_MAC_A_HWBASE, 170 .miisize = IXP425_MAC_A_SIZE, 171 .rx_qid = 12, 172 .rx_freeqid = 28, 173 .tx_qid = 25, 174 .tx_doneqid = 31 175 }, 176 }; 177 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 178 179 static __inline uint32_t 180 RD4(struct npe_softc *sc, bus_size_t off) 181 { 182 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 183 } 184 185 static __inline void 186 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 187 { 188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 189 } 190 191 static int npe_activate(struct npe_softc *); 192 #if 0 193 static void npe_deactivate(struct npe_softc *); 194 #endif 195 static void npe_ifmedia_status(struct ifnet *, struct ifmediareq *); 196 static void npe_setmac(struct npe_softc *, const u_char *); 197 static void npe_getmac(struct npe_softc *); 198 static void npe_txdone(int, void *); 199 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 200 struct mbuf *); 201 static void npe_rxdone(int, void *); 202 static void npeinit_macreg(struct npe_softc *); 203 static int npeinit(struct ifnet *); 204 static void npeinit_resetcb(void *); 205 static void npeinit_locked(void *); 206 static void npestart(struct ifnet *); 207 static void npestop(struct ifnet *, int); 208 static void npewatchdog(struct ifnet *); 209 static int npeioctl(struct ifnet *, u_long, void *); 210 211 static int npe_setrxqosentry(struct npe_softc *, int, int, int); 212 static int npe_updatestats(struct npe_softc *); 213 #if 0 214 static int npe_getstats(struct npe_softc *); 215 static uint32_t npe_getimageid(struct npe_softc *); 216 static int npe_setloopback(struct npe_softc *, int); 217 #endif 218 219 static int npe_miibus_readreg(device_t, int, int, uint16_t *); 220 static int npe_miibus_writereg(device_t, int, int, uint16_t); 221 static void npe_miibus_statchg(struct ifnet *); 222 223 static int npe_debug; 224 #define DPRINTF(sc, fmt, ...) do { \ 225 if (npe_debug) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 #define DPRINTFn(n, sc, fmt, ...) do { \ 228 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 229 } while (0) 230 231 #define NPE_TXBUF 128 232 #define NPE_RXBUF 64 233 234 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 235 + ((uint64_t)addr[1] << 32) \ 236 + ((uint64_t)addr[2] << 24) \ 237 + ((uint64_t)addr[3] << 16) \ 238 + ((uint64_t)addr[4] << 8) \ 239 + (uint64_t)addr[5]) 240 241 /* NB: all tx done processing goes through one queue */ 242 static int tx_doneqid = -1; 243 244 void (*npe_getmac_md)(int, uint8_t *); 245 246 static int npe_match(device_t, cfdata_t, void *); 247 static void npe_attach(device_t, device_t, void *); 248 249 CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 250 npe_match, npe_attach, NULL, NULL); 251 252 static int 253 npe_match(device_t parent, cfdata_t cf, void *arg) 254 { 255 struct ixpnpe_attach_args *na = arg; 256 257 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 258 } 259 260 static void 261 npe_attach(device_t parent, device_t self, void *arg) 262 { 263 struct npe_softc *sc = device_private(self); 264 struct ixpnpe_softc *isc = device_private(parent); 265 struct ixpnpe_attach_args *na = arg; 266 struct ifnet *ifp; 267 struct mii_data * const mii = &sc->sc_mii; 268 269 aprint_naive("\n"); 270 aprint_normal(": Ethernet co-processor\n"); 271 272 sc->sc_dev = self; 273 sc->sc_iot = na->na_iot; 274 sc->sc_dt = na->na_dt; 275 sc->sc_npe = na->na_npe; 276 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 277 sc->sc_phy = na->na_phy; 278 279 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 280 memset(mii, 0, sizeof(*mii)); 281 282 callout_init(&sc->sc_tick_ch, 0); 283 284 if (npe_activate(sc)) { 285 aprint_error_dev(sc->sc_dev, 286 "Failed to activate NPE (missing microcode?)\n"); 287 return; 288 } 289 290 npe_getmac(sc); 291 npeinit_macreg(sc); 292 293 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 294 ether_sprintf(sc->sc_enaddr)); 295 296 ifp = &sc->sc_ethercom.ec_if; 297 mii->mii_ifp = ifp; 298 mii->mii_readreg = npe_miibus_readreg; 299 mii->mii_writereg = npe_miibus_writereg; 300 mii->mii_statchg = npe_miibus_statchg; 301 sc->sc_ethercom.ec_mii = mii; 302 303 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 304 npe_ifmedia_status); 305 306 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 307 MII_OFFSET_ANY, MIIF_DOPAUSE); 308 if (LIST_FIRST(&mii->mii_phys) == NULL) { 309 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 310 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 311 } else 312 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 313 314 ifp->if_softc = sc; 315 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 317 ifp->if_start = npestart; 318 ifp->if_ioctl = npeioctl; 319 ifp->if_watchdog = npewatchdog; 320 ifp->if_init = npeinit; 321 ifp->if_stop = npestop; 322 IFQ_SET_READY(&ifp->if_snd); 323 324 /* VLAN capable */ 325 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 326 327 if_attach(ifp); 328 if_deferred_start_init(ifp, NULL); 329 ether_ifattach(ifp, sc->sc_enaddr); 330 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 331 RND_TYPE_NET, RND_FLAG_DEFAULT); 332 333 /* callback function to reset MAC */ 334 isc->macresetcbfunc = npeinit_resetcb; 335 isc->macresetcbarg = sc; 336 } 337 338 /* 339 * Compute and install the multicast filter. 340 */ 341 static void 342 npe_setmcast(struct npe_softc *sc) 343 { 344 struct ethercom *ec = &sc->sc_ethercom; 345 struct ifnet *ifp = &ec->ec_if; 346 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 347 uint32_t reg; 348 uint32_t msg[2]; 349 int i; 350 351 /* Always use filter. Is here a correct position? */ 352 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 353 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 354 355 if (ifp->if_flags & IFF_PROMISC) { 356 memset(mask, 0, ETHER_ADDR_LEN); 357 memset(addr, 0, ETHER_ADDR_LEN); 358 } else if (ifp->if_flags & IFF_ALLMULTI) { 359 static const uint8_t allmulti[ETHER_ADDR_LEN] = 360 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 361 all_multi: 362 memcpy(mask, allmulti, ETHER_ADDR_LEN); 363 memcpy(addr, allmulti, ETHER_ADDR_LEN); 364 } else { 365 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 366 struct ether_multistep step; 367 struct ether_multi *enm; 368 369 memset(clr, 0, ETHER_ADDR_LEN); 370 memset(set, 0xff, ETHER_ADDR_LEN); 371 372 ETHER_FIRST_MULTI(step, ec, enm); 373 while (enm != NULL) { 374 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 375 ETHER_ADDR_LEN)) { 376 ifp->if_flags |= IFF_ALLMULTI; 377 goto all_multi; 378 } 379 380 for (i = 0; i < ETHER_ADDR_LEN; i++) { 381 clr[i] |= enm->enm_addrlo[i]; 382 set[i] &= enm->enm_addrlo[i]; 383 } 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 388 for (i = 0; i < ETHER_ADDR_LEN; i++) { 389 mask[i] = set[i] | ~clr[i]; 390 addr[i] = set[i]; 391 } 392 } 393 394 /* 395 * Write the mask and address registers. 396 */ 397 for (i = 0; i < ETHER_ADDR_LEN; i++) { 398 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 399 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 400 } 401 402 msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 403 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 404 msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 405 | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 406 | (addr[5] << 8) | mask[5]; 407 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 408 } 409 410 static int 411 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 412 const char *name, int nbuf, int maxseg) 413 { 414 bus_dma_segment_t seg; 415 int rseg, error, i; 416 void *hwbuf; 417 size_t size; 418 419 memset(dma, 0, sizeof(*dma)); 420 421 dma->name = name; 422 dma->nbuf = nbuf; 423 424 size = nbuf * sizeof(struct npehwbuf); 425 426 /* XXX COHERENT for now */ 427 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 428 1, &rseg, BUS_DMA_NOWAIT); 429 if (error) { 430 aprint_error_dev(sc->sc_dev, 431 "unable to %s for %s %s buffers, error %u\n", 432 "allocate memory", dma->name, "h/w", error); 433 } 434 435 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 436 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 437 if (error) { 438 aprint_error_dev(sc->sc_dev, 439 "unable to %s for %s %s buffers, error %u\n", 440 "map memory", dma->name, "h/w", error); 441 free_dmamem: 442 bus_dmamem_free(sc->sc_dt, &seg, rseg); 443 return error; 444 } 445 dma->hwbuf = (void *)hwbuf; 446 447 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 448 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 449 if (error) { 450 aprint_error_dev(sc->sc_dev, 451 "unable to %s for %s %s buffers, error %u\n", 452 "create map", dma->name, "h/w", error); 453 unmap_dmamem: 454 dma->hwbuf = NULL; 455 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 456 goto free_dmamem; 457 } 458 459 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 460 BUS_DMA_NOWAIT); 461 if (error) { 462 aprint_error_dev(sc->sc_dev, 463 "unable to %s for %s %s buffers, error %u\n", 464 "load map", dma->name, "h/w", error); 465 destroy_dmamap: 466 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 467 goto unmap_dmamem; 468 } 469 470 /* XXX M_TEMP */ 471 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, 472 M_NOWAIT | M_ZERO); 473 if (dma->buf == NULL) { 474 aprint_error_dev(sc->sc_dev, 475 "unable to %s for %s %s buffers, error %u\n", 476 "allocate memory", dma->name, "h/w", error); 477 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 478 error = ENOMEM; 479 goto destroy_dmamap; 480 } 481 482 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 483 for (i = 0; i < dma->nbuf; i++) { 484 struct npebuf *npe = &dma->buf[i]; 485 struct npehwbuf *hw = &dma->hwbuf[i]; 486 487 /* Calculate offset to shared area */ 488 npe->ix_neaddr = dma->buf_phys + 489 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 490 KASSERT((npe->ix_neaddr & 0x1f) == 0); 491 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 492 MCLBYTES, 0, 0, &npe->ix_map); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, 495 "unable to %s for %s buffer %u, error %u\n", 496 "create dmamap", dma->name, i, error); 497 /* XXXSCW: Free up maps... */ 498 return error; 499 } 500 npe->ix_hw = hw; 501 } 502 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 503 BUS_DMASYNC_PREWRITE); 504 return 0; 505 } 506 507 #if 0 508 static void 509 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 510 { 511 int i; 512 513 /* XXXSCW: Clean this up */ 514 515 if (dma->hwbuf != NULL) { 516 for (i = 0; i < dma->nbuf; i++) { 517 struct npebuf *npe = &dma->buf[i]; 518 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 519 } 520 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 521 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 522 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 523 } 524 if (dma->buf != NULL) 525 free(dma->buf, M_TEMP); 526 memset(dma, 0, sizeof(*dma)); 527 } 528 #endif 529 530 static int 531 npe_activate(struct npe_softc *sc) 532 { 533 bus_dma_segment_t seg; 534 int unit = sc->sc_unit; 535 int error, i, rseg; 536 void *statbuf; 537 538 /* load NPE firmware and start it running */ 539 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 540 if (error != 0) 541 return error; 542 543 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 544 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 545 aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 546 npeconfig[unit].regbase, npeconfig[unit].regsize); 547 return ENOMEM; 548 } 549 550 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 551 /* 552 * The PHY's are only accessible from one MAC (it appears) 553 * so for other MAC's setup an additional mapping for 554 * frobbing the PHY registers. 555 */ 556 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 557 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 558 aprint_error_dev(sc->sc_dev, 559 "Cannot map MII registers 0x%x:0x%x\n", 560 npeconfig[unit].miibase, npeconfig[unit].miisize); 561 return ENOMEM; 562 } 563 } else 564 sc->sc_miih = sc->sc_ioh; 565 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 566 if (error != 0) 567 return error; 568 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 569 if (error != 0) 570 return error; 571 572 /* setup statistics block */ 573 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 574 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 575 if (error) { 576 aprint_error_dev(sc->sc_dev, 577 "unable to %s for %s, error %u\n", 578 "allocate memory", "stats block", error); 579 return error; 580 } 581 582 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 583 &statbuf, BUS_DMA_NOWAIT); 584 if (error) { 585 aprint_error_dev(sc->sc_dev, 586 "unable to %s for %s, error %u\n", 587 "map memory", "stats block", error); 588 return error; 589 } 590 sc->sc_stats = (void *)statbuf; 591 592 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 593 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 594 &sc->sc_stats_map); 595 if (error) { 596 aprint_error_dev(sc->sc_dev, 597 "unable to %s for %s, error %u\n", 598 "create map", "stats block", error); 599 return error; 600 } 601 602 error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 603 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 604 if (error) { 605 aprint_error_dev(sc->sc_dev, 606 "unable to %s for %s, error %u\n", 607 "load map", "stats block", error); 608 return error; 609 } 610 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 611 612 /* XXX disable half-bridge LEARNING+FILTERING feature */ 613 614 /* 615 * Setup h/w rx/tx queues. There are four q's: 616 * rx inbound q of rx'd frames 617 * rx_free pool of ixpbuf's for receiving frames 618 * tx outbound q of frames to send 619 * tx_done q of tx frames that have been processed 620 * 621 * The NPE handles the actual tx/rx process and the q manager 622 * handles the queues. The driver just writes entries to the 623 * q manager mailbox's and gets callbacks when there are rx'd 624 * frames to process or tx'd frames to reap. These callbacks 625 * are controlled by the q configurations; e.g. we get a 626 * callback when tx_done has 2 or more frames to process and 627 * when the rx q has at least one frame. These setings can 628 * changed at the time the q is configured. 629 */ 630 sc->rx_qid = npeconfig[unit].rx_qid; 631 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 632 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 633 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 634 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 635 /* tell the NPE to direct all traffic to rx_qid */ 636 #if 0 637 for (i = 0; i < 8; i++) 638 #else 639 printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 640 for (i = 0; i < 4; i++) 641 #endif 642 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 643 644 sc->tx_qid = npeconfig[unit].tx_qid; 645 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 646 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 647 if (tx_doneqid == -1) { 648 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 649 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 650 tx_doneqid = sc->tx_doneqid; 651 } 652 653 KASSERT(npes[npeconfig[unit].npeid] == NULL); 654 npes[npeconfig[unit].npeid] = sc; 655 656 return 0; 657 } 658 659 #if 0 660 static void 661 npe_deactivate(struct npe_softc *sc); 662 { 663 int unit = sc->sc_unit; 664 665 npes[npeconfig[unit].npeid] = NULL; 666 667 /* XXX disable q's */ 668 if (sc->sc_npe != NULL) 669 ixpnpe_stop(sc->sc_npe); 670 if (sc->sc_stats != NULL) { 671 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 672 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 673 sc->sc_stats_map); 674 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 675 } 676 if (sc->sc_stats_tag != NULL) 677 bus_dma_tag_destroy(sc->sc_stats_tag); 678 npe_dma_destroy(sc, &sc->txdma); 679 npe_dma_destroy(sc, &sc->rxdma); 680 bus_generic_detach(sc->sc_dev); 681 if (sc->sc_mii) 682 device_delete_child(sc->sc_dev, sc->sc_mii); 683 #if 0 684 /* XXX sc_ioh and sc_miih */ 685 if (sc->mem_res) 686 bus_release_resource(dev, SYS_RES_IOPORT, 687 rman_get_rid(sc->mem_res), sc->mem_res); 688 sc->mem_res = 0; 689 #endif 690 } 691 #endif 692 693 /* 694 * Notify the world which media we're using. 695 */ 696 static void 697 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 698 { 699 struct npe_softc *sc = ifp->if_softc; 700 701 mii_pollstat(&sc->sc_mii); 702 703 ifmr->ifm_active = sc->sc_mii.mii_media_active; 704 ifmr->ifm_status = sc->sc_mii.mii_media_status; 705 } 706 707 static void 708 npe_addstats(struct npe_softc *sc) 709 { 710 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 711 struct npestats *ns = sc->sc_stats; 712 713 ifp->if_oerrors += 714 be32toh(ns->dot3StatsInternalMacTransmitErrors) 715 + be32toh(ns->dot3StatsCarrierSenseErrors) 716 + be32toh(ns->TxVLANIdFilterDiscards) 717 ; 718 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 719 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 720 + be32toh(ns->RxOverrunDiscards) 721 + be32toh(ns->RxUnderflowEntryDiscards) 722 ; 723 ifp->if_collisions += 724 be32toh(ns->dot3StatsSingleCollisionFrames) 725 + be32toh(ns->dot3StatsMultipleCollisionFrames) 726 ; 727 } 728 729 static void 730 npe_tick(void *xsc) 731 { 732 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 733 struct npe_softc *sc = xsc; 734 uint32_t msg[2]; 735 736 /* 737 * NB: to avoid sleeping with the softc lock held we 738 * split the NPE msg processing into two parts. The 739 * request for statistics is sent w/o waiting for a 740 * reply and then on the next tick we retrieve the 741 * results. This works because npe_tick is the only 742 * code that talks via the mailbox's (except at setup). 743 * This likely can be handled better. 744 */ 745 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 746 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 747 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 748 npe_addstats(sc); 749 } 750 npe_updatestats(sc); 751 mii_tick(&sc->sc_mii); 752 753 /* Schedule next poll */ 754 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 755 #undef ACK 756 } 757 758 static void 759 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 760 { 761 762 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 763 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 764 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 765 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 766 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 767 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 768 } 769 770 static void 771 npe_getmac(struct npe_softc *sc) 772 { 773 uint8_t *eaddr = sc->sc_enaddr; 774 775 if (npe_getmac_md != NULL) { 776 (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 777 } else { 778 /* 779 * Some system's unicast address appears to be loaded from 780 * EEPROM on reset 781 */ 782 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 783 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 784 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 785 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 786 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 787 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 788 } 789 } 790 791 struct txdone { 792 struct npebuf *head; 793 struct npebuf **tail; 794 int count; 795 }; 796 797 static __inline void 798 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 799 { 800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 801 802 *td->tail = sc->tx_free; 803 sc->tx_free = td->head; 804 /* 805 * We're no longer busy, so clear the busy flag and call the 806 * start routine to xmit more packets. 807 */ 808 ifp->if_opackets += td->count; 809 ifp->if_flags &= ~IFF_OACTIVE; 810 ifp->if_timer = 0; 811 if_schedule_deferred_start(ifp); 812 } 813 814 /* 815 * Q manager callback on tx done queue. Reap mbufs 816 * and return tx buffers to the free list. Finally 817 * restart output. Note the microcode has only one 818 * txdone q wired into it so we must use the NPE ID 819 * returned with each npehwbuf to decide where to 820 * send buffers. 821 */ 822 static void 823 npe_txdone(int qid, void *arg) 824 { 825 #define P2V(a, dma) \ 826 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 827 struct npe_softc *sc; 828 struct npebuf *npe; 829 struct txdone *td, q[NPE_MAX]; 830 uint32_t entry; 831 832 /* XXX no NPE-A support */ 833 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 834 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 835 /* XXX max # at a time? */ 836 while (ixpqmgr_qread(qid, &entry) == 0) { 837 sc = npes[NPE_QM_Q_NPE(entry)]; 838 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 839 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 840 rnd_add_uint32(&sc->rnd_source, entry); 841 842 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 843 m_freem(npe->ix_m); 844 npe->ix_m = NULL; 845 846 td = &q[NPE_QM_Q_NPE(entry)]; 847 *td->tail = npe; 848 td->tail = &npe->ix_next; 849 td->count++; 850 } 851 852 if (q[NPE_B].count) 853 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 854 if (q[NPE_C].count) 855 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 856 #undef P2V 857 } 858 859 static __inline struct mbuf * 860 npe_getcl(void) 861 { 862 struct mbuf *m; 863 864 MGETHDR(m, M_DONTWAIT, MT_DATA); 865 if (m != NULL) { 866 MCLGET(m, M_DONTWAIT); 867 if ((m->m_flags & M_EXT) == 0) { 868 m_freem(m); 869 m = NULL; 870 } 871 } 872 return m; 873 } 874 875 static int 876 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 877 { 878 struct npehwbuf *hw; 879 int error; 880 881 if (m == NULL) { 882 m = npe_getcl(); 883 if (m == NULL) 884 return ENOBUFS; 885 } 886 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 887 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 888 /* backload payload and align ip hdr */ 889 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 890 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 891 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 892 BUS_DMA_READ | BUS_DMA_NOWAIT); 893 if (error != 0) { 894 m_freem(m); 895 return error; 896 } 897 hw = npe->ix_hw; 898 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 899 /* NB: NPE requires length be a multiple of 64 */ 900 /* NB: buffer length is shifted in word */ 901 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 902 hw->ix_ne[0].next = 0; 903 npe->ix_m = m; 904 /* Flush the memory in the mbuf */ 905 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 906 BUS_DMASYNC_PREREAD); 907 return 0; 908 } 909 910 /* 911 * RX q processing for a specific NPE. Claim entries 912 * from the hardware queue and pass the frames up the 913 * stack. Pass the rx buffers to the free list. 914 */ 915 static void 916 npe_rxdone(int qid, void *arg) 917 { 918 #define P2V(a, dma) \ 919 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 920 struct npe_softc *sc = arg; 921 struct npedma *dma = &sc->rxdma; 922 uint32_t entry; 923 924 while (ixpqmgr_qread(qid, &entry) == 0) { 925 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 926 struct mbuf *m; 927 928 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 929 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 930 rnd_add_uint32(&sc->rnd_source, entry); 931 /* 932 * Allocate a new mbuf to replenish the rx buffer. 933 * If doing so fails we drop the rx'd frame so we 934 * can reuse the previous mbuf. When we're able to 935 * allocate a new mbuf dispatch the mbuf w/ rx'd 936 * data up the stack and replace it with the newly 937 * allocated one. 938 */ 939 m = npe_getcl(); 940 if (m != NULL) { 941 struct mbuf *mrx = npe->ix_m; 942 struct npehwbuf *hw = npe->ix_hw; 943 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 944 945 /* Flush mbuf memory for rx'd data */ 946 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 947 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 948 949 /* XXX flush hw buffer; works now 'cuz coherent */ 950 /* set m_len etc. per rx frame size */ 951 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 952 mrx->m_pkthdr.len = mrx->m_len; 953 m_set_rcvif(mrx, ifp); 954 /* Don't add M_HASFCS. See below */ 955 956 #if 1 957 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 958 log(LOG_INFO, "%s: too short frame (len=%d)\n", 959 device_xname(sc->sc_dev), 960 mrx->m_pkthdr.len); 961 /* Back out "newly allocated" mbuf. */ 962 m_freem(m); 963 ifp->if_ierrors++; 964 goto fail; 965 } 966 if ((ifp->if_flags & IFF_PROMISC) == 0) { 967 struct ether_header *eh; 968 969 /* 970 * Workaround for "Non-Intel XScale Technology 971 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 972 * matches the filter (both unicast and 973 * multicast). 974 */ 975 eh = mtod(mrx, struct ether_header *); 976 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 977 /* Unicast */ 978 979 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 980 /* Discard it */ 981 #if 0 982 printf("discard it\n"); 983 #endif 984 /* 985 * Back out "newly allocated" 986 * mbuf. 987 */ 988 m_freem(m); 989 goto fail; 990 } 991 } else if (memcmp(eh->ether_dhost, 992 etherbroadcastaddr, 6) == 0) { 993 /* Always accept broadcast packet*/ 994 } else { 995 struct ethercom *ec = &sc->sc_ethercom; 996 struct ether_multi *enm; 997 struct ether_multistep step; 998 int match = 0; 999 1000 /* Multicast */ 1001 1002 ETHER_FIRST_MULTI(step, ec, enm); 1003 while (enm != NULL) { 1004 uint64_t lowint, highint, dest; 1005 1006 lowint = MAC2UINT64(enm->enm_addrlo); 1007 highint = MAC2UINT64(enm->enm_addrhi); 1008 dest = MAC2UINT64(eh->ether_dhost); 1009 #if 0 1010 printf("%llx\n", lowint); 1011 printf("%llx\n", dest); 1012 printf("%llx\n", highint); 1013 #endif 1014 if ((lowint <= dest) && (dest <= highint)) { 1015 match = 1; 1016 break; 1017 } 1018 ETHER_NEXT_MULTI(step, enm); 1019 } 1020 if (match == 0) { 1021 /* Discard it */ 1022 #if 0 1023 printf("discard it(M)\n"); 1024 #endif 1025 /* 1026 * Back out "newly allocated" 1027 * mbuf. 1028 */ 1029 m_freem(m); 1030 goto fail; 1031 } 1032 } 1033 } 1034 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1035 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1036 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 1037 /* Back out "newly allocated" mbuf. */ 1038 m_freem(m); 1039 ifp->if_ierrors++; 1040 goto fail; 1041 } 1042 #endif 1043 1044 /* 1045 * Trim FCS! 1046 * NPE always adds the FCS by this driver's setting, 1047 * so we always trim it here and not add M_HASFCS. 1048 */ 1049 m_adj(mrx, -ETHER_CRC_LEN); 1050 1051 /* 1052 * Tap off here if there is a bpf listener. 1053 */ 1054 1055 if_percpuq_enqueue(ifp->if_percpuq, mrx); 1056 } else { 1057 fail: 1058 /* discard frame and re-use mbuf */ 1059 m = npe->ix_m; 1060 } 1061 if (npe_rxbuf_init(sc, npe, m) == 0) { 1062 /* return npe buf to rx free list */ 1063 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1064 } else { 1065 /* XXX should not happen */ 1066 } 1067 } 1068 #undef P2V 1069 } 1070 1071 static void 1072 npe_startxmit(struct npe_softc *sc) 1073 { 1074 struct npedma *dma = &sc->txdma; 1075 int i; 1076 1077 sc->tx_free = NULL; 1078 for (i = 0; i < dma->nbuf; i++) { 1079 struct npebuf *npe = &dma->buf[i]; 1080 if (npe->ix_m != NULL) { 1081 /* NB: should not happen */ 1082 printf("%s: %s: free mbuf at entry %u\n", 1083 device_xname(sc->sc_dev), __func__, i); 1084 m_freem(npe->ix_m); 1085 } 1086 npe->ix_m = NULL; 1087 npe->ix_next = sc->tx_free; 1088 sc->tx_free = npe; 1089 } 1090 } 1091 1092 static void 1093 npe_startrecv(struct npe_softc *sc) 1094 { 1095 struct npedma *dma = &sc->rxdma; 1096 struct npebuf *npe; 1097 int i; 1098 1099 for (i = 0; i < dma->nbuf; i++) { 1100 npe = &dma->buf[i]; 1101 npe_rxbuf_init(sc, npe, npe->ix_m); 1102 /* Set npe buf on rx free list */ 1103 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1104 } 1105 } 1106 1107 static void 1108 npeinit_macreg(struct npe_softc *sc) 1109 { 1110 1111 /* 1112 * Reset MAC core. 1113 */ 1114 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1115 DELAY(NPE_MAC_RESET_DELAY); 1116 /* Configure MAC to generate MDC clock */ 1117 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1118 1119 /* Disable transmitter and reciver in the MAC */ 1120 WR4(sc, NPE_MAC_RX_CNTRL1, 1121 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1122 WR4(sc, NPE_MAC_TX_CNTRL1, 1123 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1124 1125 /* 1126 * Set the MAC core registers. 1127 */ 1128 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1129 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1130 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1131 /* Thresholds determined by NPE firmware FS */ 1132 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1133 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1134 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1135 /* tx fifo threshold (bytes) */ 1136 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1137 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1138 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1139 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1140 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1141 /* assumes MII mode */ 1142 WR4(sc, NPE_MAC_TX_CNTRL1, 1143 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1144 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1145 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1146 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1147 /* XXX pad strip? */ 1148 WR4(sc, NPE_MAC_RX_CNTRL1, 1149 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1150 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1151 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1152 } 1153 1154 static void 1155 npeinit_resetcb(void *xsc) 1156 { 1157 struct npe_softc *sc = xsc; 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 uint32_t msg[2]; 1160 1161 ifp->if_oerrors++; 1162 npeinit_locked(sc); 1163 1164 msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1165 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1166 msg[1] = 0; 1167 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1168 } 1169 1170 /* 1171 * Reset and initialize the chip 1172 */ 1173 static void 1174 npeinit_locked(void *xsc) 1175 { 1176 struct npe_softc *sc = xsc; 1177 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1178 1179 /* Cancel any pending I/O. */ 1180 npestop(ifp, 0); 1181 1182 /* Reset the chip to a known state. */ 1183 npeinit_macreg(sc); 1184 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1185 ether_mediachange(ifp); 1186 npe_setmcast(sc); 1187 1188 npe_startxmit(sc); 1189 npe_startrecv(sc); 1190 1191 ifp->if_flags |= IFF_RUNNING; 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 ifp->if_timer = 0; /* just in case */ 1194 1195 /* Enable transmitter and reciver in the MAC */ 1196 WR4(sc, NPE_MAC_RX_CNTRL1, 1197 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1198 WR4(sc, NPE_MAC_TX_CNTRL1, 1199 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1200 1201 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1202 } 1203 1204 static int 1205 npeinit(struct ifnet *ifp) 1206 { 1207 struct npe_softc *sc = ifp->if_softc; 1208 int s; 1209 1210 s = splnet(); 1211 npeinit_locked(sc); 1212 splx(s); 1213 1214 return 0; 1215 } 1216 1217 /* 1218 * Defragment an mbuf chain, returning at most maxfrags separate 1219 * mbufs+clusters. If this is not possible NULL is returned and 1220 * the original mbuf chain is left in its present (potentially 1221 * modified) state. We use two techniques: collapsing consecutive 1222 * mbufs and replacing consecutive mbufs by a cluster. 1223 */ 1224 static __inline struct mbuf * 1225 npe_defrag(struct mbuf *m0) 1226 { 1227 struct mbuf *m; 1228 1229 MGETHDR(m, M_DONTWAIT, MT_DATA); 1230 if (m == NULL) 1231 return NULL; 1232 m_copy_pkthdr(m, m0); 1233 1234 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1235 MCLGET(m, M_DONTWAIT); 1236 if ((m->m_flags & M_EXT) == 0) { 1237 m_freem(m); 1238 return NULL; 1239 } 1240 } 1241 1242 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1243 m_freem(m0); 1244 1245 return m; 1246 } 1247 1248 /* 1249 * Dequeue packets and place on the h/w transmit queue. 1250 */ 1251 static void 1252 npestart(struct ifnet *ifp) 1253 { 1254 struct npe_softc *sc = ifp->if_softc; 1255 struct npebuf *npe; 1256 struct npehwbuf *hw; 1257 struct mbuf *m, *n; 1258 bus_dma_segment_t *segs; 1259 int nseg, len, error, i; 1260 uint32_t next; 1261 1262 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1263 return; 1264 1265 while (sc->tx_free != NULL) { 1266 IFQ_DEQUEUE(&ifp->if_snd, m); 1267 if (m == NULL) 1268 break; 1269 npe = sc->tx_free; 1270 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1271 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1272 if (error == EFBIG) { 1273 n = npe_defrag(m); 1274 if (n == NULL) { 1275 printf("%s: %s: too many fragments\n", 1276 device_xname(sc->sc_dev), __func__); 1277 m_freem(m); 1278 return; /* XXX? */ 1279 } 1280 m = n; 1281 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1282 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1283 } 1284 if (error != 0) { 1285 printf("%s: %s: error %u\n", 1286 device_xname(sc->sc_dev), __func__, error); 1287 m_freem(m); 1288 return; /* XXX? */ 1289 } 1290 sc->tx_free = npe->ix_next; 1291 1292 /* 1293 * Tap off here if there is a bpf listener. 1294 */ 1295 bpf_mtap(ifp, m, BPF_D_OUT); 1296 1297 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1298 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1299 1300 npe->ix_m = m; 1301 hw = npe->ix_hw; 1302 len = m->m_pkthdr.len; 1303 nseg = npe->ix_map->dm_nsegs; 1304 segs = npe->ix_map->dm_segs; 1305 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1306 for (i = 0; i < nseg; i++) { 1307 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1308 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1309 hw->ix_ne[i].next = htobe32(next); 1310 1311 len = 0; /* zero for segments > 1 */ 1312 next += sizeof(hw->ix_ne[0]); 1313 } 1314 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1315 /* XXX flush descriptor instead of using uncached memory */ 1316 1317 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1318 __func__, sc->tx_qid, npe->ix_neaddr, 1319 hw->ix_ne[0].data, hw->ix_ne[0].len); 1320 /* stick it on the tx q */ 1321 /* XXX add vlan priority */ 1322 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1323 1324 ifp->if_timer = 5; 1325 } 1326 if (sc->tx_free == NULL) 1327 ifp->if_flags |= IFF_OACTIVE; 1328 } 1329 1330 static void 1331 npe_stopxmit(struct npe_softc *sc) 1332 { 1333 struct npedma *dma = &sc->txdma; 1334 int i; 1335 1336 /* XXX qmgr */ 1337 for (i = 0; i < dma->nbuf; i++) { 1338 struct npebuf *npe = &dma->buf[i]; 1339 1340 if (npe->ix_m != NULL) { 1341 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1342 m_freem(npe->ix_m); 1343 npe->ix_m = NULL; 1344 } 1345 } 1346 } 1347 1348 static void 1349 npe_stoprecv(struct npe_softc *sc) 1350 { 1351 struct npedma *dma = &sc->rxdma; 1352 int i; 1353 1354 /* XXX qmgr */ 1355 for (i = 0; i < dma->nbuf; i++) { 1356 struct npebuf *npe = &dma->buf[i]; 1357 1358 if (npe->ix_m != NULL) { 1359 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1360 m_freem(npe->ix_m); 1361 npe->ix_m = NULL; 1362 } 1363 } 1364 } 1365 1366 /* 1367 * Turn off interrupts, and stop the nic. 1368 */ 1369 void 1370 npestop(struct ifnet *ifp, int disable) 1371 { 1372 struct npe_softc *sc = ifp->if_softc; 1373 1374 /* Disable transmitter and reciver in the MAC */ 1375 WR4(sc, NPE_MAC_RX_CNTRL1, 1376 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1377 WR4(sc, NPE_MAC_TX_CNTRL1, 1378 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1379 1380 callout_stop(&sc->sc_tick_ch); 1381 1382 npe_stopxmit(sc); 1383 npe_stoprecv(sc); 1384 /* XXX go into loopback & drain q's? */ 1385 /* XXX but beware of disabling tx above */ 1386 1387 /* 1388 * The MAC core rx/tx disable may leave the MAC hardware in an 1389 * unpredictable state. A hw reset is executed before resetting 1390 * all the MAC parameters to a known value. 1391 */ 1392 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1393 DELAY(NPE_MAC_RESET_DELAY); 1394 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1395 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1396 1397 ifp->if_timer = 0; 1398 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1399 } 1400 1401 void 1402 npewatchdog(struct ifnet *ifp) 1403 { 1404 struct npe_softc *sc = ifp->if_softc; 1405 int s; 1406 1407 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1408 s = splnet(); 1409 ifp->if_oerrors++; 1410 npeinit_locked(sc); 1411 splx(s); 1412 } 1413 1414 static int 1415 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1416 { 1417 struct npe_softc *sc = ifp->if_softc; 1418 struct ifreq *ifr = (struct ifreq *) data; 1419 int s, error = 0; 1420 1421 s = splnet(); 1422 1423 switch (cmd) { 1424 case SIOCSIFMEDIA: 1425 #if 0 /* not yet */ 1426 /* Flow control requires full-duplex mode. */ 1427 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1428 (ifr->ifr_media & IFM_FDX) == 0) 1429 ifr->ifr_media &= ~IFM_ETH_FMASK; 1430 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1431 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1432 /* We can do both TXPAUSE and RXPAUSE. */ 1433 ifr->ifr_media |= 1434 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1435 } 1436 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1437 } 1438 #endif 1439 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1440 break; 1441 case SIOCSIFFLAGS: 1442 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) { 1443 /* 1444 * If interface is marked down and it is running, 1445 * then stop and disable it. 1446 */ 1447 (*ifp->if_stop)(ifp, 1); 1448 } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) { 1449 /* 1450 * If interface is marked up and it is stopped, then 1451 * start it. 1452 */ 1453 error = (*ifp->if_init)(ifp); 1454 } else if ((ifp->if_flags & IFF_UP) != 0) { 1455 int diff; 1456 1457 /* Up (AND RUNNING). */ 1458 1459 diff = (ifp->if_flags ^ sc->sc_if_flags) 1460 & (IFF_PROMISC | IFF_ALLMULTI); 1461 if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1462 /* 1463 * If the difference bettween last flag and 1464 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1465 * set multicast filter only (don't reset to 1466 * prevent link down). 1467 */ 1468 npe_setmcast(sc); 1469 } else { 1470 /* 1471 * Reset the interface to pick up changes in 1472 * any other flags that affect the hardware 1473 * state. 1474 */ 1475 error = (*ifp->if_init)(ifp); 1476 } 1477 } 1478 sc->sc_if_flags = ifp->if_flags; 1479 break; 1480 default: 1481 error = ether_ioctl(ifp, cmd, data); 1482 if (error == ENETRESET) { 1483 /* 1484 * Multicast list has changed; set the hardware filter 1485 * accordingly. 1486 */ 1487 npe_setmcast(sc); 1488 error = 0; 1489 } 1490 } 1491 1492 npestart(ifp); 1493 1494 splx(s); 1495 return error; 1496 } 1497 1498 /* 1499 * Setup a traffic class -> rx queue mapping. 1500 */ 1501 static int 1502 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1503 { 1504 int npeid = npeconfig[sc->sc_unit].npeid; 1505 uint32_t msg[2]; 1506 1507 msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1508 | classix; 1509 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1510 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1511 } 1512 1513 /* 1514 * Update and reset the statistics in the NPE. 1515 */ 1516 static int 1517 npe_updatestats(struct npe_softc *sc) 1518 { 1519 uint32_t msg[2]; 1520 1521 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1522 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1523 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1524 } 1525 1526 #if 0 1527 /* 1528 * Get the current statistics block. 1529 */ 1530 static int 1531 npe_getstats(struct npe_softc *sc) 1532 { 1533 uint32_t msg[2]; 1534 1535 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1536 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1537 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1538 } 1539 1540 /* 1541 * Query the image id of the loaded firmware. 1542 */ 1543 static uint32_t 1544 npe_getimageid(struct npe_softc *sc) 1545 { 1546 uint32_t msg[2]; 1547 1548 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1549 msg[1] = 0; 1550 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1551 } 1552 1553 /* 1554 * Enable/disable loopback. 1555 */ 1556 static int 1557 npe_setloopback(struct npe_softc *sc, int ena) 1558 { 1559 uint32_t msg[2]; 1560 1561 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1562 msg[1] = 0; 1563 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1564 } 1565 #endif 1566 1567 /* 1568 * MII bus support routines. 1569 * 1570 * NB: ixp425 has one PHY per NPE 1571 */ 1572 static uint32_t 1573 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1574 { 1575 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1576 uint32_t v; 1577 1578 /* NB: registers are known to be sequential */ 1579 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1580 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1581 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1582 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1583 return v; 1584 #undef MII_RD4 1585 } 1586 1587 static void 1588 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1589 { 1590 #define MII_WR4(sc, reg, v) \ 1591 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1592 1593 /* NB: registers are known to be sequential */ 1594 MII_WR4(sc, reg+0, cmd & 0xff); 1595 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1596 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1597 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1598 #undef MII_WR4 1599 } 1600 1601 static int 1602 npe_mii_mdio_wait(struct npe_softc *sc) 1603 { 1604 #define MAXTRIES 100 /* XXX */ 1605 uint32_t v; 1606 int i; 1607 1608 for (i = 0; i < MAXTRIES; i++) { 1609 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1610 if ((v & NPE_MII_GO) == 0) 1611 return 0; 1612 } 1613 return ETIMEDOUT; 1614 #undef MAXTRIES 1615 } 1616 1617 static int 1618 npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val) 1619 { 1620 struct npe_softc *sc = device_private(self); 1621 uint32_t v; 1622 1623 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1624 return -1; 1625 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1626 | NPE_MII_GO; 1627 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1628 if (npe_mii_mdio_wait(sc) == 0) 1629 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1630 else 1631 v = 0xffff | NPE_MII_READ_FAIL; 1632 1633 if ((v & NPE_MII_READ_FAIL) != 0) 1634 return -1; 1635 1636 *val = v & 0xffff; 1637 return 0; 1638 #undef MAXTRIES 1639 } 1640 1641 static int 1642 npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val) 1643 { 1644 struct npe_softc *sc = device_private(self); 1645 uint32_t v; 1646 1647 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1648 return -1; 1649 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1650 | val | NPE_MII_WRITE 1651 | NPE_MII_GO; 1652 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1653 1654 return npe_mii_mdio_wait(sc); 1655 } 1656 1657 static void 1658 npe_miibus_statchg(struct ifnet *ifp) 1659 { 1660 struct npe_softc *sc = ifp->if_softc; 1661 uint32_t tx1, rx1; 1662 uint32_t randoff; 1663 1664 /* Sync MAC duplex state */ 1665 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1666 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1667 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1668 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1669 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1670 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1671 } else { 1672 struct timeval now; 1673 getmicrotime(&now); 1674 randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1675 & 0x7f; 1676 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1677 + randoff); 1678 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1679 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1680 } 1681 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1682 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1683 } 1684
Indexes created Thu Oct 02 10:09:58 GMT 2025