ixp425_if_npe.c revision 1.42
1 /* $NetBSD: ixp425_if_npe.c,v 1.42 2019/09/13 07:55:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.42 2019/09/13 07:55:06 msaitoh Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/socket.h> 58 #include <sys/endian.h> 59 #include <sys/ioctl.h> 60 #include <sys/syslog.h> 61 #include <sys/bus.h> 62 #include <sys/rndsource.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 #include <net/bpf.h> 69 70 #include <arm/xscale/ixp425reg.h> 71 #include <arm/xscale/ixp425var.h> 72 #include <arm/xscale/ixp425_qmgr.h> 73 #include <arm/xscale/ixp425_npevar.h> 74 #include <arm/xscale/ixp425_if_npereg.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include "locators.h" 79 80 struct npebuf { 81 struct npebuf *ix_next; /* chain to next buffer */ 82 void *ix_m; /* backpointer to mbuf */ 83 bus_dmamap_t ix_map; /* bus dma map for associated data */ 84 struct npehwbuf *ix_hw; /* associated h/w block */ 85 uint32_t ix_neaddr; /* phys address of ix_hw */ 86 }; 87 88 struct npedma { 89 const char* name; 90 int nbuf; /* # npebuf's allocated */ 91 bus_dmamap_t m_map; 92 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 93 bus_dmamap_t buf_map; 94 bus_addr_t buf_phys; /* phys addr of buffers */ 95 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 96 }; 97 98 struct npe_softc { 99 device_t sc_dev; 100 struct ethercom sc_ethercom; 101 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 102 struct mii_data sc_mii; 103 bus_space_tag_t sc_iot; 104 bus_dma_tag_t sc_dt; 105 bus_space_handle_t sc_ioh; /* MAC register window */ 106 bus_space_handle_t sc_miih; /* MII register window */ 107 struct ixpnpe_softc *sc_npe; /* NPE support */ 108 int sc_unit; 109 int sc_phy; 110 struct callout sc_tick_ch; /* Tick callout */ 111 struct npedma txdma; 112 struct npebuf *tx_free; /* list of free tx buffers */ 113 struct npedma rxdma; 114 int rx_qid; /* rx qid */ 115 int rx_freeqid; /* rx free buffers qid */ 116 int tx_qid; /* tx qid */ 117 int tx_doneqid; /* tx completed qid */ 118 struct npestats *sc_stats; 119 bus_dmamap_t sc_stats_map; 120 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 121 u_short sc_if_flags; /* keep last if_flags */ 122 krndsource_t rnd_source; /* random source */ 123 }; 124 125 /* 126 * Per-unit static configuration for IXP425. The tx and 127 * rx free Q id's are fixed by the NPE microcode. The 128 * rx Q id's are programmed to be separate to simplify 129 * multi-port processing. It may be better to handle 130 * all traffic through one Q (as done by the Intel drivers). 131 * 132 * Note that the PHY's are accessible only from MAC A 133 * on the IXP425. This and other platform-specific 134 * assumptions probably need to be handled through hints. 135 */ 136 static const struct { 137 const char *desc; /* device description */ 138 int npeid; /* NPE assignment */ 139 int macport; /* Port number of the MAC */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .macport = 0x10, 153 .imageid = IXP425_NPE_B_IMAGEID, 154 .regbase = IXP425_MAC_A_HWBASE, 155 .regsize = IXP425_MAC_A_SIZE, 156 .miibase = IXP425_MAC_A_HWBASE, 157 .miisize = IXP425_MAC_A_SIZE, 158 .rx_qid = 4, 159 .rx_freeqid = 27, 160 .tx_qid = 24, 161 .tx_doneqid = 31 162 }, 163 { .desc = "IXP NPE-C", 164 .npeid = NPE_C, 165 .macport = 0x20, 166 .imageid = IXP425_NPE_C_IMAGEID, 167 .regbase = IXP425_MAC_B_HWBASE, 168 .regsize = IXP425_MAC_B_SIZE, 169 .miibase = IXP425_MAC_A_HWBASE, 170 .miisize = IXP425_MAC_A_SIZE, 171 .rx_qid = 12, 172 .rx_freeqid = 28, 173 .tx_qid = 25, 174 .tx_doneqid = 31 175 }, 176 }; 177 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 178 179 static __inline uint32_t 180 RD4(struct npe_softc *sc, bus_size_t off) 181 { 182 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 183 } 184 185 static __inline void 186 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 187 { 188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 189 } 190 191 static int npe_activate(struct npe_softc *); 192 #if 0 193 static void npe_deactivate(struct npe_softc *); 194 #endif 195 static void npe_ifmedia_status(struct ifnet *, struct ifmediareq *); 196 static void npe_setmac(struct npe_softc *, const u_char *); 197 static void npe_getmac(struct npe_softc *); 198 static void npe_txdone(int, void *); 199 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 200 struct mbuf *); 201 static void npe_rxdone(int, void *); 202 static void npeinit_macreg(struct npe_softc *); 203 static int npeinit(struct ifnet *); 204 static void npeinit_resetcb(void *); 205 static void npeinit_locked(void *); 206 static void npestart(struct ifnet *); 207 static void npestop(struct ifnet *, int); 208 static void npewatchdog(struct ifnet *); 209 static int npeioctl(struct ifnet *, u_long, void *); 210 211 static int npe_setrxqosentry(struct npe_softc *, int, int, int); 212 static int npe_updatestats(struct npe_softc *); 213 #if 0 214 static int npe_getstats(struct npe_softc *); 215 static uint32_t npe_getimageid(struct npe_softc *); 216 static int npe_setloopback(struct npe_softc *, int); 217 #endif 218 219 static int npe_miibus_readreg(device_t, int, int, uint16_t *); 220 static int npe_miibus_writereg(device_t, int, int, uint16_t); 221 static void npe_miibus_statchg(struct ifnet *); 222 223 static int npe_debug; 224 #define DPRINTF(sc, fmt, ...) do { \ 225 if (npe_debug) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 #define DPRINTFn(n, sc, fmt, ...) do { \ 228 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 229 } while (0) 230 231 #define NPE_TXBUF 128 232 #define NPE_RXBUF 64 233 234 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 235 + ((uint64_t)addr[1] << 32) \ 236 + ((uint64_t)addr[2] << 24) \ 237 + ((uint64_t)addr[3] << 16) \ 238 + ((uint64_t)addr[4] << 8) \ 239 + (uint64_t)addr[5]) 240 241 /* NB: all tx done processing goes through one queue */ 242 static int tx_doneqid = -1; 243 244 void (*npe_getmac_md)(int, uint8_t *); 245 246 static int npe_match(device_t, cfdata_t, void *); 247 static void npe_attach(device_t, device_t, void *); 248 249 CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 250 npe_match, npe_attach, NULL, NULL); 251 252 static int 253 npe_match(device_t parent, cfdata_t cf, void *arg) 254 { 255 struct ixpnpe_attach_args *na = arg; 256 257 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 258 } 259 260 static void 261 npe_attach(device_t parent, device_t self, void *arg) 262 { 263 struct npe_softc *sc = device_private(self); 264 struct ixpnpe_softc *isc = device_private(parent); 265 struct ixpnpe_attach_args *na = arg; 266 struct ifnet *ifp; 267 struct mii_data * const mii = &sc->sc_mii; 268 269 aprint_naive("\n"); 270 aprint_normal(": Ethernet co-processor\n"); 271 272 sc->sc_dev = self; 273 sc->sc_iot = na->na_iot; 274 sc->sc_dt = na->na_dt; 275 sc->sc_npe = na->na_npe; 276 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 277 sc->sc_phy = na->na_phy; 278 279 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 280 memset(mii, 0, sizeof(*mii)); 281 282 callout_init(&sc->sc_tick_ch, 0); 283 284 if (npe_activate(sc)) { 285 aprint_error_dev(sc->sc_dev, 286 "Failed to activate NPE (missing microcode?)\n"); 287 return; 288 } 289 290 npe_getmac(sc); 291 npeinit_macreg(sc); 292 293 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 294 ether_sprintf(sc->sc_enaddr)); 295 296 ifp = &sc->sc_ethercom.ec_if; 297 mii->mii_ifp = ifp; 298 mii->mii_readreg = npe_miibus_readreg; 299 mii->mii_writereg = npe_miibus_writereg; 300 mii->mii_statchg = npe_miibus_statchg; 301 sc->sc_ethercom.ec_mii = mii; 302 303 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 304 npe_ifmedia_status); 305 306 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 307 MII_OFFSET_ANY, MIIF_DOPAUSE); 308 if (LIST_FIRST(&mii->mii_phys) == NULL) { 309 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 310 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 311 } else 312 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 313 314 ifp->if_softc = sc; 315 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 317 ifp->if_start = npestart; 318 ifp->if_ioctl = npeioctl; 319 ifp->if_watchdog = npewatchdog; 320 ifp->if_init = npeinit; 321 ifp->if_stop = npestop; 322 IFQ_SET_READY(&ifp->if_snd); 323 324 /* VLAN capable */ 325 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 326 327 if_attach(ifp); 328 if_deferred_start_init(ifp, NULL); 329 ether_ifattach(ifp, sc->sc_enaddr); 330 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 331 RND_TYPE_NET, RND_FLAG_DEFAULT); 332 333 /* callback function to reset MAC */ 334 isc->macresetcbfunc = npeinit_resetcb; 335 isc->macresetcbarg = sc; 336 } 337 338 /* 339 * Compute and install the multicast filter. 340 */ 341 static void 342 npe_setmcast(struct npe_softc *sc) 343 { 344 struct ethercom *ec = &sc->sc_ethercom; 345 struct ifnet *ifp = &ec->ec_if; 346 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 347 uint32_t reg; 348 uint32_t msg[2]; 349 int i; 350 351 /* Always use filter. Is here a correct position? */ 352 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 353 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 354 355 if (ifp->if_flags & IFF_PROMISC) { 356 memset(mask, 0, ETHER_ADDR_LEN); 357 memset(addr, 0, ETHER_ADDR_LEN); 358 } else if (ifp->if_flags & IFF_ALLMULTI) { 359 static const uint8_t allmulti[ETHER_ADDR_LEN] = 360 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 361 all_multi: 362 memcpy(mask, allmulti, ETHER_ADDR_LEN); 363 memcpy(addr, allmulti, ETHER_ADDR_LEN); 364 } else { 365 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 366 struct ether_multistep step; 367 struct ether_multi *enm; 368 369 memset(clr, 0, ETHER_ADDR_LEN); 370 memset(set, 0xff, ETHER_ADDR_LEN); 371 372 ETHER_LOCK(ec); 373 ETHER_FIRST_MULTI(step, ec, enm); 374 while (enm != NULL) { 375 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 376 ETHER_ADDR_LEN)) { 377 ifp->if_flags |= IFF_ALLMULTI; 378 ETHER_UNLOCK(ec); 379 goto all_multi; 380 } 381 382 for (i = 0; i < ETHER_ADDR_LEN; i++) { 383 clr[i] |= enm->enm_addrlo[i]; 384 set[i] &= enm->enm_addrlo[i]; 385 } 386 387 ETHER_NEXT_MULTI(step, enm); 388 } 389 ETHER_UNLOCK(ec); 390 391 for (i = 0; i < ETHER_ADDR_LEN; i++) { 392 mask[i] = set[i] | ~clr[i]; 393 addr[i] = set[i]; 394 } 395 } 396 397 /* 398 * Write the mask and address registers. 399 */ 400 for (i = 0; i < ETHER_ADDR_LEN; i++) { 401 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 402 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 403 } 404 405 msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 406 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 407 msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 408 | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 409 | (addr[5] << 8) | mask[5]; 410 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 411 } 412 413 static int 414 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 415 const char *name, int nbuf, int maxseg) 416 { 417 bus_dma_segment_t seg; 418 int rseg, error, i; 419 void *hwbuf; 420 size_t size; 421 422 memset(dma, 0, sizeof(*dma)); 423 424 dma->name = name; 425 dma->nbuf = nbuf; 426 427 size = nbuf * sizeof(struct npehwbuf); 428 429 /* XXX COHERENT for now */ 430 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 431 1, &rseg, BUS_DMA_NOWAIT); 432 if (error) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to %s for %s %s buffers, error %u\n", 435 "allocate memory", dma->name, "h/w", error); 436 } 437 438 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 440 if (error) { 441 aprint_error_dev(sc->sc_dev, 442 "unable to %s for %s %s buffers, error %u\n", 443 "map memory", dma->name, "h/w", error); 444 free_dmamem: 445 bus_dmamem_free(sc->sc_dt, &seg, rseg); 446 return error; 447 } 448 dma->hwbuf = (void *)hwbuf; 449 450 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 451 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 452 if (error) { 453 aprint_error_dev(sc->sc_dev, 454 "unable to %s for %s %s buffers, error %u\n", 455 "create map", dma->name, "h/w", error); 456 unmap_dmamem: 457 dma->hwbuf = NULL; 458 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 459 goto free_dmamem; 460 } 461 462 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 463 BUS_DMA_NOWAIT); 464 if (error) { 465 aprint_error_dev(sc->sc_dev, 466 "unable to %s for %s %s buffers, error %u\n", 467 "load map", dma->name, "h/w", error); 468 destroy_dmamap: 469 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 470 goto unmap_dmamem; 471 } 472 473 /* XXX M_TEMP */ 474 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, 475 M_NOWAIT | M_ZERO); 476 if (dma->buf == NULL) { 477 aprint_error_dev(sc->sc_dev, 478 "unable to %s for %s %s buffers, error %u\n", 479 "allocate memory", dma->name, "h/w", error); 480 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 481 error = ENOMEM; 482 goto destroy_dmamap; 483 } 484 485 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 486 for (i = 0; i < dma->nbuf; i++) { 487 struct npebuf *npe = &dma->buf[i]; 488 struct npehwbuf *hw = &dma->hwbuf[i]; 489 490 /* Calculate offset to shared area */ 491 npe->ix_neaddr = dma->buf_phys + 492 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 493 KASSERT((npe->ix_neaddr & 0x1f) == 0); 494 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 495 MCLBYTES, 0, 0, &npe->ix_map); 496 if (error != 0) { 497 aprint_error_dev(sc->sc_dev, 498 "unable to %s for %s buffer %u, error %u\n", 499 "create dmamap", dma->name, i, error); 500 /* XXXSCW: Free up maps... */ 501 return error; 502 } 503 npe->ix_hw = hw; 504 } 505 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 506 BUS_DMASYNC_PREWRITE); 507 return 0; 508 } 509 510 #if 0 511 static void 512 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 513 { 514 int i; 515 516 /* XXXSCW: Clean this up */ 517 518 if (dma->hwbuf != NULL) { 519 for (i = 0; i < dma->nbuf; i++) { 520 struct npebuf *npe = &dma->buf[i]; 521 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 522 } 523 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 524 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 525 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 526 } 527 if (dma->buf != NULL) 528 free(dma->buf, M_TEMP); 529 memset(dma, 0, sizeof(*dma)); 530 } 531 #endif 532 533 static int 534 npe_activate(struct npe_softc *sc) 535 { 536 bus_dma_segment_t seg; 537 int unit = sc->sc_unit; 538 int error, i, rseg; 539 void *statbuf; 540 541 /* load NPE firmware and start it running */ 542 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 543 if (error != 0) 544 return error; 545 546 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 547 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 548 aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 549 npeconfig[unit].regbase, npeconfig[unit].regsize); 550 return ENOMEM; 551 } 552 553 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 554 /* 555 * The PHY's are only accessible from one MAC (it appears) 556 * so for other MAC's setup an additional mapping for 557 * frobbing the PHY registers. 558 */ 559 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 560 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 561 aprint_error_dev(sc->sc_dev, 562 "Cannot map MII registers 0x%x:0x%x\n", 563 npeconfig[unit].miibase, npeconfig[unit].miisize); 564 return ENOMEM; 565 } 566 } else 567 sc->sc_miih = sc->sc_ioh; 568 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 569 if (error != 0) 570 return error; 571 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 572 if (error != 0) 573 return error; 574 575 /* setup statistics block */ 576 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 577 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 578 if (error) { 579 aprint_error_dev(sc->sc_dev, 580 "unable to %s for %s, error %u\n", 581 "allocate memory", "stats block", error); 582 return error; 583 } 584 585 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 586 &statbuf, BUS_DMA_NOWAIT); 587 if (error) { 588 aprint_error_dev(sc->sc_dev, 589 "unable to %s for %s, error %u\n", 590 "map memory", "stats block", error); 591 return error; 592 } 593 sc->sc_stats = (void *)statbuf; 594 595 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 596 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 597 &sc->sc_stats_map); 598 if (error) { 599 aprint_error_dev(sc->sc_dev, 600 "unable to %s for %s, error %u\n", 601 "create map", "stats block", error); 602 return error; 603 } 604 605 error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 606 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 607 if (error) { 608 aprint_error_dev(sc->sc_dev, 609 "unable to %s for %s, error %u\n", 610 "load map", "stats block", error); 611 return error; 612 } 613 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 614 615 /* XXX disable half-bridge LEARNING+FILTERING feature */ 616 617 /* 618 * Setup h/w rx/tx queues. There are four q's: 619 * rx inbound q of rx'd frames 620 * rx_free pool of ixpbuf's for receiving frames 621 * tx outbound q of frames to send 622 * tx_done q of tx frames that have been processed 623 * 624 * The NPE handles the actual tx/rx process and the q manager 625 * handles the queues. The driver just writes entries to the 626 * q manager mailbox's and gets callbacks when there are rx'd 627 * frames to process or tx'd frames to reap. These callbacks 628 * are controlled by the q configurations; e.g. we get a 629 * callback when tx_done has 2 or more frames to process and 630 * when the rx q has at least one frame. These setings can 631 * changed at the time the q is configured. 632 */ 633 sc->rx_qid = npeconfig[unit].rx_qid; 634 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 635 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 636 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 637 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 638 /* tell the NPE to direct all traffic to rx_qid */ 639 #if 0 640 for (i = 0; i < 8; i++) 641 #else 642 printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 643 for (i = 0; i < 4; i++) 644 #endif 645 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 646 647 sc->tx_qid = npeconfig[unit].tx_qid; 648 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 649 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 650 if (tx_doneqid == -1) { 651 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 652 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 653 tx_doneqid = sc->tx_doneqid; 654 } 655 656 KASSERT(npes[npeconfig[unit].npeid] == NULL); 657 npes[npeconfig[unit].npeid] = sc; 658 659 return 0; 660 } 661 662 #if 0 663 static void 664 npe_deactivate(struct npe_softc *sc); 665 { 666 int unit = sc->sc_unit; 667 668 npes[npeconfig[unit].npeid] = NULL; 669 670 /* XXX disable q's */ 671 if (sc->sc_npe != NULL) 672 ixpnpe_stop(sc->sc_npe); 673 if (sc->sc_stats != NULL) { 674 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 675 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 676 sc->sc_stats_map); 677 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 678 } 679 if (sc->sc_stats_tag != NULL) 680 bus_dma_tag_destroy(sc->sc_stats_tag); 681 npe_dma_destroy(sc, &sc->txdma); 682 npe_dma_destroy(sc, &sc->rxdma); 683 bus_generic_detach(sc->sc_dev); 684 if (sc->sc_mii) 685 device_delete_child(sc->sc_dev, sc->sc_mii); 686 #if 0 687 /* XXX sc_ioh and sc_miih */ 688 if (sc->mem_res) 689 bus_release_resource(dev, SYS_RES_IOPORT, 690 rman_get_rid(sc->mem_res), sc->mem_res); 691 sc->mem_res = 0; 692 #endif 693 } 694 #endif 695 696 /* 697 * Notify the world which media we're using. 698 */ 699 static void 700 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 701 { 702 struct npe_softc *sc = ifp->if_softc; 703 704 mii_pollstat(&sc->sc_mii); 705 706 ifmr->ifm_active = sc->sc_mii.mii_media_active; 707 ifmr->ifm_status = sc->sc_mii.mii_media_status; 708 } 709 710 static void 711 npe_addstats(struct npe_softc *sc) 712 { 713 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 714 struct npestats *ns = sc->sc_stats; 715 716 ifp->if_oerrors += 717 be32toh(ns->dot3StatsInternalMacTransmitErrors) 718 + be32toh(ns->dot3StatsCarrierSenseErrors) 719 + be32toh(ns->TxVLANIdFilterDiscards) 720 ; 721 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 722 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 723 + be32toh(ns->RxOverrunDiscards) 724 + be32toh(ns->RxUnderflowEntryDiscards) 725 ; 726 ifp->if_collisions += 727 be32toh(ns->dot3StatsSingleCollisionFrames) 728 + be32toh(ns->dot3StatsMultipleCollisionFrames) 729 ; 730 } 731 732 static void 733 npe_tick(void *xsc) 734 { 735 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 736 struct npe_softc *sc = xsc; 737 uint32_t msg[2]; 738 739 /* 740 * NB: to avoid sleeping with the softc lock held we 741 * split the NPE msg processing into two parts. The 742 * request for statistics is sent w/o waiting for a 743 * reply and then on the next tick we retrieve the 744 * results. This works because npe_tick is the only 745 * code that talks via the mailbox's (except at setup). 746 * This likely can be handled better. 747 */ 748 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 749 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 750 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 751 npe_addstats(sc); 752 } 753 npe_updatestats(sc); 754 mii_tick(&sc->sc_mii); 755 756 /* Schedule next poll */ 757 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 758 #undef ACK 759 } 760 761 static void 762 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 763 { 764 765 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 766 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 767 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 768 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 769 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 770 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 771 } 772 773 static void 774 npe_getmac(struct npe_softc *sc) 775 { 776 uint8_t *eaddr = sc->sc_enaddr; 777 778 if (npe_getmac_md != NULL) { 779 (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 780 } else { 781 /* 782 * Some system's unicast address appears to be loaded from 783 * EEPROM on reset 784 */ 785 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 786 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 787 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 788 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 789 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 790 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 791 } 792 } 793 794 struct txdone { 795 struct npebuf *head; 796 struct npebuf **tail; 797 int count; 798 }; 799 800 static __inline void 801 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 802 { 803 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 804 805 *td->tail = sc->tx_free; 806 sc->tx_free = td->head; 807 /* 808 * We're no longer busy, so clear the busy flag and call the 809 * start routine to xmit more packets. 810 */ 811 ifp->if_opackets += td->count; 812 ifp->if_flags &= ~IFF_OACTIVE; 813 ifp->if_timer = 0; 814 if_schedule_deferred_start(ifp); 815 } 816 817 /* 818 * Q manager callback on tx done queue. Reap mbufs 819 * and return tx buffers to the free list. Finally 820 * restart output. Note the microcode has only one 821 * txdone q wired into it so we must use the NPE ID 822 * returned with each npehwbuf to decide where to 823 * send buffers. 824 */ 825 static void 826 npe_txdone(int qid, void *arg) 827 { 828 #define P2V(a, dma) \ 829 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 830 struct npe_softc *sc; 831 struct npebuf *npe; 832 struct txdone *td, q[NPE_MAX]; 833 uint32_t entry; 834 835 /* XXX no NPE-A support */ 836 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 837 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 838 /* XXX max # at a time? */ 839 while (ixpqmgr_qread(qid, &entry) == 0) { 840 sc = npes[NPE_QM_Q_NPE(entry)]; 841 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 842 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 843 rnd_add_uint32(&sc->rnd_source, entry); 844 845 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 846 m_freem(npe->ix_m); 847 npe->ix_m = NULL; 848 849 td = &q[NPE_QM_Q_NPE(entry)]; 850 *td->tail = npe; 851 td->tail = &npe->ix_next; 852 td->count++; 853 } 854 855 if (q[NPE_B].count) 856 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 857 if (q[NPE_C].count) 858 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 859 #undef P2V 860 } 861 862 static __inline struct mbuf * 863 npe_getcl(void) 864 { 865 struct mbuf *m; 866 867 MGETHDR(m, M_DONTWAIT, MT_DATA); 868 if (m != NULL) { 869 MCLGET(m, M_DONTWAIT); 870 if ((m->m_flags & M_EXT) == 0) { 871 m_freem(m); 872 m = NULL; 873 } 874 } 875 return m; 876 } 877 878 static int 879 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 880 { 881 struct npehwbuf *hw; 882 int error; 883 884 if (m == NULL) { 885 m = npe_getcl(); 886 if (m == NULL) 887 return ENOBUFS; 888 } 889 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 890 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 891 /* backload payload and align ip hdr */ 892 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 893 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 894 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 895 BUS_DMA_READ | BUS_DMA_NOWAIT); 896 if (error != 0) { 897 m_freem(m); 898 return error; 899 } 900 hw = npe->ix_hw; 901 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 902 /* NB: NPE requires length be a multiple of 64 */ 903 /* NB: buffer length is shifted in word */ 904 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 905 hw->ix_ne[0].next = 0; 906 npe->ix_m = m; 907 /* Flush the memory in the mbuf */ 908 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 909 BUS_DMASYNC_PREREAD); 910 return 0; 911 } 912 913 /* 914 * RX q processing for a specific NPE. Claim entries 915 * from the hardware queue and pass the frames up the 916 * stack. Pass the rx buffers to the free list. 917 */ 918 static void 919 npe_rxdone(int qid, void *arg) 920 { 921 #define P2V(a, dma) \ 922 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 923 struct npe_softc *sc = arg; 924 struct npedma *dma = &sc->rxdma; 925 uint32_t entry; 926 927 while (ixpqmgr_qread(qid, &entry) == 0) { 928 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 929 struct mbuf *m; 930 931 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 932 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 933 rnd_add_uint32(&sc->rnd_source, entry); 934 /* 935 * Allocate a new mbuf to replenish the rx buffer. 936 * If doing so fails we drop the rx'd frame so we 937 * can reuse the previous mbuf. When we're able to 938 * allocate a new mbuf dispatch the mbuf w/ rx'd 939 * data up the stack and replace it with the newly 940 * allocated one. 941 */ 942 m = npe_getcl(); 943 if (m != NULL) { 944 struct mbuf *mrx = npe->ix_m; 945 struct npehwbuf *hw = npe->ix_hw; 946 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 947 948 /* Flush mbuf memory for rx'd data */ 949 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 950 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 951 952 /* XXX flush hw buffer; works now 'cuz coherent */ 953 /* set m_len etc. per rx frame size */ 954 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 955 mrx->m_pkthdr.len = mrx->m_len; 956 m_set_rcvif(mrx, ifp); 957 /* Don't add M_HASFCS. See below */ 958 959 #if 1 960 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 961 log(LOG_INFO, "%s: too short frame (len=%d)\n", 962 device_xname(sc->sc_dev), 963 mrx->m_pkthdr.len); 964 /* Back out "newly allocated" mbuf. */ 965 m_freem(m); 966 ifp->if_ierrors++; 967 goto fail; 968 } 969 if ((ifp->if_flags & IFF_PROMISC) == 0) { 970 struct ether_header *eh; 971 972 /* 973 * Workaround for "Non-Intel XScale Technology 974 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 975 * matches the filter (both unicast and 976 * multicast). 977 */ 978 eh = mtod(mrx, struct ether_header *); 979 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 980 /* Unicast */ 981 982 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 983 /* Discard it */ 984 #if 0 985 printf("discard it\n"); 986 #endif 987 /* 988 * Back out "newly allocated" 989 * mbuf. 990 */ 991 m_freem(m); 992 goto fail; 993 } 994 } else if (memcmp(eh->ether_dhost, 995 etherbroadcastaddr, 6) == 0) { 996 /* Always accept broadcast packet*/ 997 } else { 998 struct ethercom *ec = &sc->sc_ethercom; 999 struct ether_multi *enm; 1000 struct ether_multistep step; 1001 int match = 0; 1002 1003 /* Multicast */ 1004 1005 ETHER_LOCK(ec); 1006 ETHER_FIRST_MULTI(step, ec, enm); 1007 while (enm != NULL) { 1008 uint64_t lowint, highint, dest; 1009 1010 lowint = MAC2UINT64(enm->enm_addrlo); 1011 highint = MAC2UINT64(enm->enm_addrhi); 1012 dest = MAC2UINT64(eh->ether_dhost); 1013 #if 0 1014 printf("%llx\n", lowint); 1015 printf("%llx\n", dest); 1016 printf("%llx\n", highint); 1017 #endif 1018 if ((lowint <= dest) && (dest <= highint)) { 1019 match = 1; 1020 break; 1021 } 1022 ETHER_NEXT_MULTI(step, enm); 1023 } 1024 ETHER_UNLOCK(ec); 1025 1026 if (match == 0) { 1027 /* Discard it */ 1028 #if 0 1029 printf("discard it(M)\n"); 1030 #endif 1031 /* 1032 * Back out "newly allocated" 1033 * mbuf. 1034 */ 1035 m_freem(m); 1036 goto fail; 1037 } 1038 } 1039 } 1040 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1041 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1042 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 1043 /* Back out "newly allocated" mbuf. */ 1044 m_freem(m); 1045 ifp->if_ierrors++; 1046 goto fail; 1047 } 1048 #endif 1049 1050 /* 1051 * Trim FCS! 1052 * NPE always adds the FCS by this driver's setting, 1053 * so we always trim it here and not add M_HASFCS. 1054 */ 1055 m_adj(mrx, -ETHER_CRC_LEN); 1056 1057 /* 1058 * Tap off here if there is a bpf listener. 1059 */ 1060 1061 if_percpuq_enqueue(ifp->if_percpuq, mrx); 1062 } else { 1063 fail: 1064 /* discard frame and re-use mbuf */ 1065 m = npe->ix_m; 1066 } 1067 if (npe_rxbuf_init(sc, npe, m) == 0) { 1068 /* return npe buf to rx free list */ 1069 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1070 } else { 1071 /* XXX should not happen */ 1072 } 1073 } 1074 #undef P2V 1075 } 1076 1077 static void 1078 npe_startxmit(struct npe_softc *sc) 1079 { 1080 struct npedma *dma = &sc->txdma; 1081 int i; 1082 1083 sc->tx_free = NULL; 1084 for (i = 0; i < dma->nbuf; i++) { 1085 struct npebuf *npe = &dma->buf[i]; 1086 if (npe->ix_m != NULL) { 1087 /* NB: should not happen */ 1088 printf("%s: %s: free mbuf at entry %u\n", 1089 device_xname(sc->sc_dev), __func__, i); 1090 m_freem(npe->ix_m); 1091 } 1092 npe->ix_m = NULL; 1093 npe->ix_next = sc->tx_free; 1094 sc->tx_free = npe; 1095 } 1096 } 1097 1098 static void 1099 npe_startrecv(struct npe_softc *sc) 1100 { 1101 struct npedma *dma = &sc->rxdma; 1102 struct npebuf *npe; 1103 int i; 1104 1105 for (i = 0; i < dma->nbuf; i++) { 1106 npe = &dma->buf[i]; 1107 npe_rxbuf_init(sc, npe, npe->ix_m); 1108 /* Set npe buf on rx free list */ 1109 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1110 } 1111 } 1112 1113 static void 1114 npeinit_macreg(struct npe_softc *sc) 1115 { 1116 1117 /* 1118 * Reset MAC core. 1119 */ 1120 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1121 DELAY(NPE_MAC_RESET_DELAY); 1122 /* Configure MAC to generate MDC clock */ 1123 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1124 1125 /* Disable transmitter and reciver in the MAC */ 1126 WR4(sc, NPE_MAC_RX_CNTRL1, 1127 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1128 WR4(sc, NPE_MAC_TX_CNTRL1, 1129 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1130 1131 /* 1132 * Set the MAC core registers. 1133 */ 1134 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1135 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1136 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1137 /* Thresholds determined by NPE firmware FS */ 1138 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1139 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1140 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1141 /* tx fifo threshold (bytes) */ 1142 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1143 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1144 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1145 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1146 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1147 /* assumes MII mode */ 1148 WR4(sc, NPE_MAC_TX_CNTRL1, 1149 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1150 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1151 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1152 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1153 /* XXX pad strip? */ 1154 WR4(sc, NPE_MAC_RX_CNTRL1, 1155 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1156 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1157 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1158 } 1159 1160 static void 1161 npeinit_resetcb(void *xsc) 1162 { 1163 struct npe_softc *sc = xsc; 1164 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1165 uint32_t msg[2]; 1166 1167 ifp->if_oerrors++; 1168 npeinit_locked(sc); 1169 1170 msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1171 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1172 msg[1] = 0; 1173 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1174 } 1175 1176 /* 1177 * Reset and initialize the chip 1178 */ 1179 static void 1180 npeinit_locked(void *xsc) 1181 { 1182 struct npe_softc *sc = xsc; 1183 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1184 1185 /* Cancel any pending I/O. */ 1186 npestop(ifp, 0); 1187 1188 /* Reset the chip to a known state. */ 1189 npeinit_macreg(sc); 1190 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1191 ether_mediachange(ifp); 1192 npe_setmcast(sc); 1193 1194 npe_startxmit(sc); 1195 npe_startrecv(sc); 1196 1197 ifp->if_flags |= IFF_RUNNING; 1198 ifp->if_flags &= ~IFF_OACTIVE; 1199 ifp->if_timer = 0; /* just in case */ 1200 1201 /* Enable transmitter and reciver in the MAC */ 1202 WR4(sc, NPE_MAC_RX_CNTRL1, 1203 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1204 WR4(sc, NPE_MAC_TX_CNTRL1, 1205 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1206 1207 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1208 } 1209 1210 static int 1211 npeinit(struct ifnet *ifp) 1212 { 1213 struct npe_softc *sc = ifp->if_softc; 1214 int s; 1215 1216 s = splnet(); 1217 npeinit_locked(sc); 1218 splx(s); 1219 1220 return 0; 1221 } 1222 1223 /* 1224 * Defragment an mbuf chain, returning at most maxfrags separate 1225 * mbufs+clusters. If this is not possible NULL is returned and 1226 * the original mbuf chain is left in its present (potentially 1227 * modified) state. We use two techniques: collapsing consecutive 1228 * mbufs and replacing consecutive mbufs by a cluster. 1229 */ 1230 static __inline struct mbuf * 1231 npe_defrag(struct mbuf *m0) 1232 { 1233 struct mbuf *m; 1234 1235 MGETHDR(m, M_DONTWAIT, MT_DATA); 1236 if (m == NULL) 1237 return NULL; 1238 m_copy_pkthdr(m, m0); 1239 1240 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1241 MCLGET(m, M_DONTWAIT); 1242 if ((m->m_flags & M_EXT) == 0) { 1243 m_freem(m); 1244 return NULL; 1245 } 1246 } 1247 1248 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1249 m_freem(m0); 1250 1251 return m; 1252 } 1253 1254 /* 1255 * Dequeue packets and place on the h/w transmit queue. 1256 */ 1257 static void 1258 npestart(struct ifnet *ifp) 1259 { 1260 struct npe_softc *sc = ifp->if_softc; 1261 struct npebuf *npe; 1262 struct npehwbuf *hw; 1263 struct mbuf *m, *n; 1264 bus_dma_segment_t *segs; 1265 int nseg, len, error, i; 1266 uint32_t next; 1267 1268 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1269 return; 1270 1271 while (sc->tx_free != NULL) { 1272 IFQ_DEQUEUE(&ifp->if_snd, m); 1273 if (m == NULL) 1274 break; 1275 npe = sc->tx_free; 1276 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1277 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1278 if (error == EFBIG) { 1279 n = npe_defrag(m); 1280 if (n == NULL) { 1281 printf("%s: %s: too many fragments\n", 1282 device_xname(sc->sc_dev), __func__); 1283 m_freem(m); 1284 return; /* XXX? */ 1285 } 1286 m = n; 1287 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1288 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1289 } 1290 if (error != 0) { 1291 printf("%s: %s: error %u\n", 1292 device_xname(sc->sc_dev), __func__, error); 1293 m_freem(m); 1294 return; /* XXX? */ 1295 } 1296 sc->tx_free = npe->ix_next; 1297 1298 /* 1299 * Tap off here if there is a bpf listener. 1300 */ 1301 bpf_mtap(ifp, m, BPF_D_OUT); 1302 1303 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1304 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1305 1306 npe->ix_m = m; 1307 hw = npe->ix_hw; 1308 len = m->m_pkthdr.len; 1309 nseg = npe->ix_map->dm_nsegs; 1310 segs = npe->ix_map->dm_segs; 1311 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1312 for (i = 0; i < nseg; i++) { 1313 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1314 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1315 hw->ix_ne[i].next = htobe32(next); 1316 1317 len = 0; /* zero for segments > 1 */ 1318 next += sizeof(hw->ix_ne[0]); 1319 } 1320 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1321 /* XXX flush descriptor instead of using uncached memory */ 1322 1323 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1324 __func__, sc->tx_qid, npe->ix_neaddr, 1325 hw->ix_ne[0].data, hw->ix_ne[0].len); 1326 /* stick it on the tx q */ 1327 /* XXX add vlan priority */ 1328 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1329 1330 ifp->if_timer = 5; 1331 } 1332 if (sc->tx_free == NULL) 1333 ifp->if_flags |= IFF_OACTIVE; 1334 } 1335 1336 static void 1337 npe_stopxmit(struct npe_softc *sc) 1338 { 1339 struct npedma *dma = &sc->txdma; 1340 int i; 1341 1342 /* XXX qmgr */ 1343 for (i = 0; i < dma->nbuf; i++) { 1344 struct npebuf *npe = &dma->buf[i]; 1345 1346 if (npe->ix_m != NULL) { 1347 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1348 m_freem(npe->ix_m); 1349 npe->ix_m = NULL; 1350 } 1351 } 1352 } 1353 1354 static void 1355 npe_stoprecv(struct npe_softc *sc) 1356 { 1357 struct npedma *dma = &sc->rxdma; 1358 int i; 1359 1360 /* XXX qmgr */ 1361 for (i = 0; i < dma->nbuf; i++) { 1362 struct npebuf *npe = &dma->buf[i]; 1363 1364 if (npe->ix_m != NULL) { 1365 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1366 m_freem(npe->ix_m); 1367 npe->ix_m = NULL; 1368 } 1369 } 1370 } 1371 1372 /* 1373 * Turn off interrupts, and stop the nic. 1374 */ 1375 void 1376 npestop(struct ifnet *ifp, int disable) 1377 { 1378 struct npe_softc *sc = ifp->if_softc; 1379 1380 /* Disable transmitter and reciver in the MAC */ 1381 WR4(sc, NPE_MAC_RX_CNTRL1, 1382 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1383 WR4(sc, NPE_MAC_TX_CNTRL1, 1384 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1385 1386 callout_stop(&sc->sc_tick_ch); 1387 1388 npe_stopxmit(sc); 1389 npe_stoprecv(sc); 1390 /* XXX go into loopback & drain q's? */ 1391 /* XXX but beware of disabling tx above */ 1392 1393 /* 1394 * The MAC core rx/tx disable may leave the MAC hardware in an 1395 * unpredictable state. A hw reset is executed before resetting 1396 * all the MAC parameters to a known value. 1397 */ 1398 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1399 DELAY(NPE_MAC_RESET_DELAY); 1400 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1401 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1402 1403 ifp->if_timer = 0; 1404 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1405 } 1406 1407 void 1408 npewatchdog(struct ifnet *ifp) 1409 { 1410 struct npe_softc *sc = ifp->if_softc; 1411 int s; 1412 1413 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1414 s = splnet(); 1415 ifp->if_oerrors++; 1416 npeinit_locked(sc); 1417 splx(s); 1418 } 1419 1420 static int 1421 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1422 { 1423 struct npe_softc *sc = ifp->if_softc; 1424 struct ifreq *ifr = (struct ifreq *) data; 1425 int s, error = 0; 1426 1427 s = splnet(); 1428 1429 switch (cmd) { 1430 case SIOCSIFMEDIA: 1431 #if 0 /* not yet */ 1432 /* Flow control requires full-duplex mode. */ 1433 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1434 (ifr->ifr_media & IFM_FDX) == 0) 1435 ifr->ifr_media &= ~IFM_ETH_FMASK; 1436 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1437 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1438 /* We can do both TXPAUSE and RXPAUSE. */ 1439 ifr->ifr_media |= 1440 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1441 } 1442 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1443 } 1444 #endif 1445 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1446 break; 1447 case SIOCSIFFLAGS: 1448 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) { 1449 /* 1450 * If interface is marked down and it is running, 1451 * then stop and disable it. 1452 */ 1453 (*ifp->if_stop)(ifp, 1); 1454 } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) { 1455 /* 1456 * If interface is marked up and it is stopped, then 1457 * start it. 1458 */ 1459 error = (*ifp->if_init)(ifp); 1460 } else if ((ifp->if_flags & IFF_UP) != 0) { 1461 u_short diff; 1462 1463 /* Up (AND RUNNING). */ 1464 1465 diff = (ifp->if_flags ^ sc->sc_if_flags) 1466 & (IFF_PROMISC | IFF_ALLMULTI); 1467 if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1468 /* 1469 * If the difference bettween last flag and 1470 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1471 * set multicast filter only (don't reset to 1472 * prevent link down). 1473 */ 1474 npe_setmcast(sc); 1475 } else { 1476 /* 1477 * Reset the interface to pick up changes in 1478 * any other flags that affect the hardware 1479 * state. 1480 */ 1481 error = (*ifp->if_init)(ifp); 1482 } 1483 } 1484 sc->sc_if_flags = ifp->if_flags; 1485 break; 1486 default: 1487 error = ether_ioctl(ifp, cmd, data); 1488 if (error == ENETRESET) { 1489 /* 1490 * Multicast list has changed; set the hardware filter 1491 * accordingly. 1492 */ 1493 npe_setmcast(sc); 1494 error = 0; 1495 } 1496 } 1497 1498 npestart(ifp); 1499 1500 splx(s); 1501 return error; 1502 } 1503 1504 /* 1505 * Setup a traffic class -> rx queue mapping. 1506 */ 1507 static int 1508 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1509 { 1510 int npeid = npeconfig[sc->sc_unit].npeid; 1511 uint32_t msg[2]; 1512 1513 msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1514 | classix; 1515 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1516 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1517 } 1518 1519 /* 1520 * Update and reset the statistics in the NPE. 1521 */ 1522 static int 1523 npe_updatestats(struct npe_softc *sc) 1524 { 1525 uint32_t msg[2]; 1526 1527 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1528 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1529 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1530 } 1531 1532 #if 0 1533 /* 1534 * Get the current statistics block. 1535 */ 1536 static int 1537 npe_getstats(struct npe_softc *sc) 1538 { 1539 uint32_t msg[2]; 1540 1541 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1542 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1543 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1544 } 1545 1546 /* 1547 * Query the image id of the loaded firmware. 1548 */ 1549 static uint32_t 1550 npe_getimageid(struct npe_softc *sc) 1551 { 1552 uint32_t msg[2]; 1553 1554 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1555 msg[1] = 0; 1556 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1557 } 1558 1559 /* 1560 * Enable/disable loopback. 1561 */ 1562 static int 1563 npe_setloopback(struct npe_softc *sc, int ena) 1564 { 1565 uint32_t msg[2]; 1566 1567 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1568 msg[1] = 0; 1569 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1570 } 1571 #endif 1572 1573 /* 1574 * MII bus support routines. 1575 * 1576 * NB: ixp425 has one PHY per NPE 1577 */ 1578 static uint32_t 1579 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1580 { 1581 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1582 uint32_t v; 1583 1584 /* NB: registers are known to be sequential */ 1585 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1586 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1587 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1588 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1589 return v; 1590 #undef MII_RD4 1591 } 1592 1593 static void 1594 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1595 { 1596 #define MII_WR4(sc, reg, v) \ 1597 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1598 1599 /* NB: registers are known to be sequential */ 1600 MII_WR4(sc, reg+0, cmd & 0xff); 1601 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1602 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1603 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1604 #undef MII_WR4 1605 } 1606 1607 static int 1608 npe_mii_mdio_wait(struct npe_softc *sc) 1609 { 1610 #define MAXTRIES 100 /* XXX */ 1611 uint32_t v; 1612 int i; 1613 1614 for (i = 0; i < MAXTRIES; i++) { 1615 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1616 if ((v & NPE_MII_GO) == 0) 1617 return 0; 1618 } 1619 return ETIMEDOUT; 1620 #undef MAXTRIES 1621 } 1622 1623 static int 1624 npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val) 1625 { 1626 struct npe_softc *sc = device_private(self); 1627 uint32_t v; 1628 1629 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1630 return -1; 1631 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1632 | NPE_MII_GO; 1633 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1634 if (npe_mii_mdio_wait(sc) == 0) 1635 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1636 else 1637 v = 0xffff | NPE_MII_READ_FAIL; 1638 1639 if ((v & NPE_MII_READ_FAIL) != 0) 1640 return -1; 1641 1642 *val = v & 0xffff; 1643 return 0; 1644 #undef MAXTRIES 1645 } 1646 1647 static int 1648 npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val) 1649 { 1650 struct npe_softc *sc = device_private(self); 1651 uint32_t v; 1652 1653 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1654 return -1; 1655 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1656 | val | NPE_MII_WRITE 1657 | NPE_MII_GO; 1658 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1659 1660 return npe_mii_mdio_wait(sc); 1661 } 1662 1663 static void 1664 npe_miibus_statchg(struct ifnet *ifp) 1665 { 1666 struct npe_softc *sc = ifp->if_softc; 1667 uint32_t tx1, rx1; 1668 uint32_t randoff; 1669 1670 /* Sync MAC duplex state */ 1671 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1672 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1673 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1674 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1675 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1676 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1677 } else { 1678 struct timeval now; 1679 getmicrotime(&now); 1680 randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1681 & 0x7f; 1682 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1683 + randoff); 1684 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1685 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1686 } 1687 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1688 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1689 } 1690
Indexes created Thu Oct 02 10:09:58 GMT 2025