ixp425_if_npe.c revision 1.43
1 /* $NetBSD: ixp425_if_npe.c,v 1.43 2019/11/10 21:16:24 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.43 2019/11/10 21:16:24 chs Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/socket.h> 58 #include <sys/endian.h> 59 #include <sys/ioctl.h> 60 #include <sys/syslog.h> 61 #include <sys/bus.h> 62 #include <sys/rndsource.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 #include <net/bpf.h> 69 70 #include <arm/xscale/ixp425reg.h> 71 #include <arm/xscale/ixp425var.h> 72 #include <arm/xscale/ixp425_qmgr.h> 73 #include <arm/xscale/ixp425_npevar.h> 74 #include <arm/xscale/ixp425_if_npereg.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include "locators.h" 79 80 struct npebuf { 81 struct npebuf *ix_next; /* chain to next buffer */ 82 void *ix_m; /* backpointer to mbuf */ 83 bus_dmamap_t ix_map; /* bus dma map for associated data */ 84 struct npehwbuf *ix_hw; /* associated h/w block */ 85 uint32_t ix_neaddr; /* phys address of ix_hw */ 86 }; 87 88 struct npedma { 89 const char* name; 90 int nbuf; /* # npebuf's allocated */ 91 bus_dmamap_t m_map; 92 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 93 bus_dmamap_t buf_map; 94 bus_addr_t buf_phys; /* phys addr of buffers */ 95 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 96 }; 97 98 struct npe_softc { 99 device_t sc_dev; 100 struct ethercom sc_ethercom; 101 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 102 struct mii_data sc_mii; 103 bus_space_tag_t sc_iot; 104 bus_dma_tag_t sc_dt; 105 bus_space_handle_t sc_ioh; /* MAC register window */ 106 bus_space_handle_t sc_miih; /* MII register window */ 107 struct ixpnpe_softc *sc_npe; /* NPE support */ 108 int sc_unit; 109 int sc_phy; 110 struct callout sc_tick_ch; /* Tick callout */ 111 struct npedma txdma; 112 struct npebuf *tx_free; /* list of free tx buffers */ 113 struct npedma rxdma; 114 int rx_qid; /* rx qid */ 115 int rx_freeqid; /* rx free buffers qid */ 116 int tx_qid; /* tx qid */ 117 int tx_doneqid; /* tx completed qid */ 118 struct npestats *sc_stats; 119 bus_dmamap_t sc_stats_map; 120 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 121 u_short sc_if_flags; /* keep last if_flags */ 122 krndsource_t rnd_source; /* random source */ 123 }; 124 125 /* 126 * Per-unit static configuration for IXP425. The tx and 127 * rx free Q id's are fixed by the NPE microcode. The 128 * rx Q id's are programmed to be separate to simplify 129 * multi-port processing. It may be better to handle 130 * all traffic through one Q (as done by the Intel drivers). 131 * 132 * Note that the PHY's are accessible only from MAC A 133 * on the IXP425. This and other platform-specific 134 * assumptions probably need to be handled through hints. 135 */ 136 static const struct { 137 const char *desc; /* device description */ 138 int npeid; /* NPE assignment */ 139 int macport; /* Port number of the MAC */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .macport = 0x10, 153 .imageid = IXP425_NPE_B_IMAGEID, 154 .regbase = IXP425_MAC_A_HWBASE, 155 .regsize = IXP425_MAC_A_SIZE, 156 .miibase = IXP425_MAC_A_HWBASE, 157 .miisize = IXP425_MAC_A_SIZE, 158 .rx_qid = 4, 159 .rx_freeqid = 27, 160 .tx_qid = 24, 161 .tx_doneqid = 31 162 }, 163 { .desc = "IXP NPE-C", 164 .npeid = NPE_C, 165 .macport = 0x20, 166 .imageid = IXP425_NPE_C_IMAGEID, 167 .regbase = IXP425_MAC_B_HWBASE, 168 .regsize = IXP425_MAC_B_SIZE, 169 .miibase = IXP425_MAC_A_HWBASE, 170 .miisize = IXP425_MAC_A_SIZE, 171 .rx_qid = 12, 172 .rx_freeqid = 28, 173 .tx_qid = 25, 174 .tx_doneqid = 31 175 }, 176 }; 177 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 178 179 static __inline uint32_t 180 RD4(struct npe_softc *sc, bus_size_t off) 181 { 182 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 183 } 184 185 static __inline void 186 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 187 { 188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 189 } 190 191 static int npe_activate(struct npe_softc *); 192 #if 0 193 static void npe_deactivate(struct npe_softc *); 194 #endif 195 static void npe_ifmedia_status(struct ifnet *, struct ifmediareq *); 196 static void npe_setmac(struct npe_softc *, const u_char *); 197 static void npe_getmac(struct npe_softc *); 198 static void npe_txdone(int, void *); 199 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 200 struct mbuf *); 201 static void npe_rxdone(int, void *); 202 static void npeinit_macreg(struct npe_softc *); 203 static int npeinit(struct ifnet *); 204 static void npeinit_resetcb(void *); 205 static void npeinit_locked(void *); 206 static void npestart(struct ifnet *); 207 static void npestop(struct ifnet *, int); 208 static void npewatchdog(struct ifnet *); 209 static int npeioctl(struct ifnet *, u_long, void *); 210 211 static int npe_setrxqosentry(struct npe_softc *, int, int, int); 212 static int npe_updatestats(struct npe_softc *); 213 #if 0 214 static int npe_getstats(struct npe_softc *); 215 static uint32_t npe_getimageid(struct npe_softc *); 216 static int npe_setloopback(struct npe_softc *, int); 217 #endif 218 219 static int npe_miibus_readreg(device_t, int, int, uint16_t *); 220 static int npe_miibus_writereg(device_t, int, int, uint16_t); 221 static void npe_miibus_statchg(struct ifnet *); 222 223 static int npe_debug; 224 #define DPRINTF(sc, fmt, ...) do { \ 225 if (npe_debug) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 #define DPRINTFn(n, sc, fmt, ...) do { \ 228 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 229 } while (0) 230 231 #define NPE_TXBUF 128 232 #define NPE_RXBUF 64 233 234 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 235 + ((uint64_t)addr[1] << 32) \ 236 + ((uint64_t)addr[2] << 24) \ 237 + ((uint64_t)addr[3] << 16) \ 238 + ((uint64_t)addr[4] << 8) \ 239 + (uint64_t)addr[5]) 240 241 /* NB: all tx done processing goes through one queue */ 242 static int tx_doneqid = -1; 243 244 void (*npe_getmac_md)(int, uint8_t *); 245 246 static int npe_match(device_t, cfdata_t, void *); 247 static void npe_attach(device_t, device_t, void *); 248 249 CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 250 npe_match, npe_attach, NULL, NULL); 251 252 static int 253 npe_match(device_t parent, cfdata_t cf, void *arg) 254 { 255 struct ixpnpe_attach_args *na = arg; 256 257 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 258 } 259 260 static void 261 npe_attach(device_t parent, device_t self, void *arg) 262 { 263 struct npe_softc *sc = device_private(self); 264 struct ixpnpe_softc *isc = device_private(parent); 265 struct ixpnpe_attach_args *na = arg; 266 struct ifnet *ifp; 267 struct mii_data * const mii = &sc->sc_mii; 268 269 aprint_naive("\n"); 270 aprint_normal(": Ethernet co-processor\n"); 271 272 sc->sc_dev = self; 273 sc->sc_iot = na->na_iot; 274 sc->sc_dt = na->na_dt; 275 sc->sc_npe = na->na_npe; 276 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 277 sc->sc_phy = na->na_phy; 278 279 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 280 memset(mii, 0, sizeof(*mii)); 281 282 callout_init(&sc->sc_tick_ch, 0); 283 284 if (npe_activate(sc)) { 285 aprint_error_dev(sc->sc_dev, 286 "Failed to activate NPE (missing microcode?)\n"); 287 return; 288 } 289 290 npe_getmac(sc); 291 npeinit_macreg(sc); 292 293 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 294 ether_sprintf(sc->sc_enaddr)); 295 296 ifp = &sc->sc_ethercom.ec_if; 297 mii->mii_ifp = ifp; 298 mii->mii_readreg = npe_miibus_readreg; 299 mii->mii_writereg = npe_miibus_writereg; 300 mii->mii_statchg = npe_miibus_statchg; 301 sc->sc_ethercom.ec_mii = mii; 302 303 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 304 npe_ifmedia_status); 305 306 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 307 MII_OFFSET_ANY, MIIF_DOPAUSE); 308 if (LIST_FIRST(&mii->mii_phys) == NULL) { 309 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 310 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 311 } else 312 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 313 314 ifp->if_softc = sc; 315 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 317 ifp->if_start = npestart; 318 ifp->if_ioctl = npeioctl; 319 ifp->if_watchdog = npewatchdog; 320 ifp->if_init = npeinit; 321 ifp->if_stop = npestop; 322 IFQ_SET_READY(&ifp->if_snd); 323 324 /* VLAN capable */ 325 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 326 327 if_attach(ifp); 328 if_deferred_start_init(ifp, NULL); 329 ether_ifattach(ifp, sc->sc_enaddr); 330 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 331 RND_TYPE_NET, RND_FLAG_DEFAULT); 332 333 /* callback function to reset MAC */ 334 isc->macresetcbfunc = npeinit_resetcb; 335 isc->macresetcbarg = sc; 336 } 337 338 /* 339 * Compute and install the multicast filter. 340 */ 341 static void 342 npe_setmcast(struct npe_softc *sc) 343 { 344 struct ethercom *ec = &sc->sc_ethercom; 345 struct ifnet *ifp = &ec->ec_if; 346 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 347 uint32_t reg; 348 uint32_t msg[2]; 349 int i; 350 351 /* Always use filter. Is here a correct position? */ 352 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 353 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 354 355 if (ifp->if_flags & IFF_PROMISC) { 356 memset(mask, 0, ETHER_ADDR_LEN); 357 memset(addr, 0, ETHER_ADDR_LEN); 358 } else if (ifp->if_flags & IFF_ALLMULTI) { 359 static const uint8_t allmulti[ETHER_ADDR_LEN] = 360 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 361 all_multi: 362 memcpy(mask, allmulti, ETHER_ADDR_LEN); 363 memcpy(addr, allmulti, ETHER_ADDR_LEN); 364 } else { 365 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 366 struct ether_multistep step; 367 struct ether_multi *enm; 368 369 memset(clr, 0, ETHER_ADDR_LEN); 370 memset(set, 0xff, ETHER_ADDR_LEN); 371 372 ETHER_LOCK(ec); 373 ETHER_FIRST_MULTI(step, ec, enm); 374 while (enm != NULL) { 375 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 376 ETHER_ADDR_LEN)) { 377 ifp->if_flags |= IFF_ALLMULTI; 378 ETHER_UNLOCK(ec); 379 goto all_multi; 380 } 381 382 for (i = 0; i < ETHER_ADDR_LEN; i++) { 383 clr[i] |= enm->enm_addrlo[i]; 384 set[i] &= enm->enm_addrlo[i]; 385 } 386 387 ETHER_NEXT_MULTI(step, enm); 388 } 389 ETHER_UNLOCK(ec); 390 391 for (i = 0; i < ETHER_ADDR_LEN; i++) { 392 mask[i] = set[i] | ~clr[i]; 393 addr[i] = set[i]; 394 } 395 } 396 397 /* 398 * Write the mask and address registers. 399 */ 400 for (i = 0; i < ETHER_ADDR_LEN; i++) { 401 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 402 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 403 } 404 405 msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 406 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 407 msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 408 | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 409 | (addr[5] << 8) | mask[5]; 410 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 411 } 412 413 static int 414 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 415 const char *name, int nbuf, int maxseg) 416 { 417 bus_dma_segment_t seg; 418 int rseg, error, i; 419 void *hwbuf; 420 size_t size; 421 422 memset(dma, 0, sizeof(*dma)); 423 424 dma->name = name; 425 dma->nbuf = nbuf; 426 427 size = nbuf * sizeof(struct npehwbuf); 428 429 /* XXX COHERENT for now */ 430 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 431 1, &rseg, BUS_DMA_NOWAIT); 432 if (error) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to %s for %s %s buffers, error %u\n", 435 "allocate memory", dma->name, "h/w", error); 436 } 437 438 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 440 if (error) { 441 aprint_error_dev(sc->sc_dev, 442 "unable to %s for %s %s buffers, error %u\n", 443 "map memory", dma->name, "h/w", error); 444 free_dmamem: 445 bus_dmamem_free(sc->sc_dt, &seg, rseg); 446 return error; 447 } 448 dma->hwbuf = (void *)hwbuf; 449 450 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 451 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 452 if (error) { 453 aprint_error_dev(sc->sc_dev, 454 "unable to %s for %s %s buffers, error %u\n", 455 "create map", dma->name, "h/w", error); 456 unmap_dmamem: 457 dma->hwbuf = NULL; 458 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 459 goto free_dmamem; 460 } 461 462 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 463 BUS_DMA_NOWAIT); 464 if (error) { 465 aprint_error_dev(sc->sc_dev, 466 "unable to %s for %s %s buffers, error %u\n", 467 "load map", dma->name, "h/w", error); 468 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 469 goto unmap_dmamem; 470 } 471 472 /* XXX M_TEMP */ 473 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, 474 M_WAITOK | M_ZERO); 475 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 476 for (i = 0; i < dma->nbuf; i++) { 477 struct npebuf *npe = &dma->buf[i]; 478 struct npehwbuf *hw = &dma->hwbuf[i]; 479 480 /* Calculate offset to shared area */ 481 npe->ix_neaddr = dma->buf_phys + 482 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 483 KASSERT((npe->ix_neaddr & 0x1f) == 0); 484 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 485 MCLBYTES, 0, 0, &npe->ix_map); 486 if (error != 0) { 487 aprint_error_dev(sc->sc_dev, 488 "unable to %s for %s buffer %u, error %u\n", 489 "create dmamap", dma->name, i, error); 490 /* XXXSCW: Free up maps... */ 491 return error; 492 } 493 npe->ix_hw = hw; 494 } 495 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 496 BUS_DMASYNC_PREWRITE); 497 return 0; 498 } 499 500 #if 0 501 static void 502 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 503 { 504 int i; 505 506 /* XXXSCW: Clean this up */ 507 508 if (dma->hwbuf != NULL) { 509 for (i = 0; i < dma->nbuf; i++) { 510 struct npebuf *npe = &dma->buf[i]; 511 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 512 } 513 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 514 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 515 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 516 } 517 if (dma->buf != NULL) 518 free(dma->buf, M_TEMP); 519 memset(dma, 0, sizeof(*dma)); 520 } 521 #endif 522 523 static int 524 npe_activate(struct npe_softc *sc) 525 { 526 bus_dma_segment_t seg; 527 int unit = sc->sc_unit; 528 int error, i, rseg; 529 void *statbuf; 530 531 /* load NPE firmware and start it running */ 532 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 533 if (error != 0) 534 return error; 535 536 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 537 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 538 aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 539 npeconfig[unit].regbase, npeconfig[unit].regsize); 540 return ENOMEM; 541 } 542 543 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 544 /* 545 * The PHY's are only accessible from one MAC (it appears) 546 * so for other MAC's setup an additional mapping for 547 * frobbing the PHY registers. 548 */ 549 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 550 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 551 aprint_error_dev(sc->sc_dev, 552 "Cannot map MII registers 0x%x:0x%x\n", 553 npeconfig[unit].miibase, npeconfig[unit].miisize); 554 return ENOMEM; 555 } 556 } else 557 sc->sc_miih = sc->sc_ioh; 558 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 559 if (error != 0) 560 return error; 561 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 562 if (error != 0) 563 return error; 564 565 /* setup statistics block */ 566 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 567 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 568 if (error) { 569 aprint_error_dev(sc->sc_dev, 570 "unable to %s for %s, error %u\n", 571 "allocate memory", "stats block", error); 572 return error; 573 } 574 575 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 576 &statbuf, BUS_DMA_NOWAIT); 577 if (error) { 578 aprint_error_dev(sc->sc_dev, 579 "unable to %s for %s, error %u\n", 580 "map memory", "stats block", error); 581 return error; 582 } 583 sc->sc_stats = (void *)statbuf; 584 585 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 586 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 587 &sc->sc_stats_map); 588 if (error) { 589 aprint_error_dev(sc->sc_dev, 590 "unable to %s for %s, error %u\n", 591 "create map", "stats block", error); 592 return error; 593 } 594 595 error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 596 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 597 if (error) { 598 aprint_error_dev(sc->sc_dev, 599 "unable to %s for %s, error %u\n", 600 "load map", "stats block", error); 601 return error; 602 } 603 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 604 605 /* XXX disable half-bridge LEARNING+FILTERING feature */ 606 607 /* 608 * Setup h/w rx/tx queues. There are four q's: 609 * rx inbound q of rx'd frames 610 * rx_free pool of ixpbuf's for receiving frames 611 * tx outbound q of frames to send 612 * tx_done q of tx frames that have been processed 613 * 614 * The NPE handles the actual tx/rx process and the q manager 615 * handles the queues. The driver just writes entries to the 616 * q manager mailbox's and gets callbacks when there are rx'd 617 * frames to process or tx'd frames to reap. These callbacks 618 * are controlled by the q configurations; e.g. we get a 619 * callback when tx_done has 2 or more frames to process and 620 * when the rx q has at least one frame. These setings can 621 * changed at the time the q is configured. 622 */ 623 sc->rx_qid = npeconfig[unit].rx_qid; 624 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 625 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 626 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 627 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 628 /* tell the NPE to direct all traffic to rx_qid */ 629 #if 0 630 for (i = 0; i < 8; i++) 631 #else 632 printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 633 for (i = 0; i < 4; i++) 634 #endif 635 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 636 637 sc->tx_qid = npeconfig[unit].tx_qid; 638 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 639 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 640 if (tx_doneqid == -1) { 641 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 642 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 643 tx_doneqid = sc->tx_doneqid; 644 } 645 646 KASSERT(npes[npeconfig[unit].npeid] == NULL); 647 npes[npeconfig[unit].npeid] = sc; 648 649 return 0; 650 } 651 652 #if 0 653 static void 654 npe_deactivate(struct npe_softc *sc); 655 { 656 int unit = sc->sc_unit; 657 658 npes[npeconfig[unit].npeid] = NULL; 659 660 /* XXX disable q's */ 661 if (sc->sc_npe != NULL) 662 ixpnpe_stop(sc->sc_npe); 663 if (sc->sc_stats != NULL) { 664 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 665 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 666 sc->sc_stats_map); 667 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 668 } 669 if (sc->sc_stats_tag != NULL) 670 bus_dma_tag_destroy(sc->sc_stats_tag); 671 npe_dma_destroy(sc, &sc->txdma); 672 npe_dma_destroy(sc, &sc->rxdma); 673 bus_generic_detach(sc->sc_dev); 674 if (sc->sc_mii) 675 device_delete_child(sc->sc_dev, sc->sc_mii); 676 #if 0 677 /* XXX sc_ioh and sc_miih */ 678 if (sc->mem_res) 679 bus_release_resource(dev, SYS_RES_IOPORT, 680 rman_get_rid(sc->mem_res), sc->mem_res); 681 sc->mem_res = 0; 682 #endif 683 } 684 #endif 685 686 /* 687 * Notify the world which media we're using. 688 */ 689 static void 690 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 691 { 692 struct npe_softc *sc = ifp->if_softc; 693 694 mii_pollstat(&sc->sc_mii); 695 696 ifmr->ifm_active = sc->sc_mii.mii_media_active; 697 ifmr->ifm_status = sc->sc_mii.mii_media_status; 698 } 699 700 static void 701 npe_addstats(struct npe_softc *sc) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 struct npestats *ns = sc->sc_stats; 705 706 ifp->if_oerrors += 707 be32toh(ns->dot3StatsInternalMacTransmitErrors) 708 + be32toh(ns->dot3StatsCarrierSenseErrors) 709 + be32toh(ns->TxVLANIdFilterDiscards) 710 ; 711 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 712 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 713 + be32toh(ns->RxOverrunDiscards) 714 + be32toh(ns->RxUnderflowEntryDiscards) 715 ; 716 ifp->if_collisions += 717 be32toh(ns->dot3StatsSingleCollisionFrames) 718 + be32toh(ns->dot3StatsMultipleCollisionFrames) 719 ; 720 } 721 722 static void 723 npe_tick(void *xsc) 724 { 725 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 726 struct npe_softc *sc = xsc; 727 uint32_t msg[2]; 728 729 /* 730 * NB: to avoid sleeping with the softc lock held we 731 * split the NPE msg processing into two parts. The 732 * request for statistics is sent w/o waiting for a 733 * reply and then on the next tick we retrieve the 734 * results. This works because npe_tick is the only 735 * code that talks via the mailbox's (except at setup). 736 * This likely can be handled better. 737 */ 738 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 739 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 740 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 741 npe_addstats(sc); 742 } 743 npe_updatestats(sc); 744 mii_tick(&sc->sc_mii); 745 746 /* Schedule next poll */ 747 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 748 #undef ACK 749 } 750 751 static void 752 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 753 { 754 755 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 756 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 757 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 758 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 759 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 760 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 761 } 762 763 static void 764 npe_getmac(struct npe_softc *sc) 765 { 766 uint8_t *eaddr = sc->sc_enaddr; 767 768 if (npe_getmac_md != NULL) { 769 (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 770 } else { 771 /* 772 * Some system's unicast address appears to be loaded from 773 * EEPROM on reset 774 */ 775 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 776 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 777 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 778 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 779 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 780 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 781 } 782 } 783 784 struct txdone { 785 struct npebuf *head; 786 struct npebuf **tail; 787 int count; 788 }; 789 790 static __inline void 791 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 792 { 793 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 794 795 *td->tail = sc->tx_free; 796 sc->tx_free = td->head; 797 /* 798 * We're no longer busy, so clear the busy flag and call the 799 * start routine to xmit more packets. 800 */ 801 ifp->if_opackets += td->count; 802 ifp->if_flags &= ~IFF_OACTIVE; 803 ifp->if_timer = 0; 804 if_schedule_deferred_start(ifp); 805 } 806 807 /* 808 * Q manager callback on tx done queue. Reap mbufs 809 * and return tx buffers to the free list. Finally 810 * restart output. Note the microcode has only one 811 * txdone q wired into it so we must use the NPE ID 812 * returned with each npehwbuf to decide where to 813 * send buffers. 814 */ 815 static void 816 npe_txdone(int qid, void *arg) 817 { 818 #define P2V(a, dma) \ 819 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 820 struct npe_softc *sc; 821 struct npebuf *npe; 822 struct txdone *td, q[NPE_MAX]; 823 uint32_t entry; 824 825 /* XXX no NPE-A support */ 826 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 827 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 828 /* XXX max # at a time? */ 829 while (ixpqmgr_qread(qid, &entry) == 0) { 830 sc = npes[NPE_QM_Q_NPE(entry)]; 831 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 832 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 833 rnd_add_uint32(&sc->rnd_source, entry); 834 835 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 836 m_freem(npe->ix_m); 837 npe->ix_m = NULL; 838 839 td = &q[NPE_QM_Q_NPE(entry)]; 840 *td->tail = npe; 841 td->tail = &npe->ix_next; 842 td->count++; 843 } 844 845 if (q[NPE_B].count) 846 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 847 if (q[NPE_C].count) 848 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 849 #undef P2V 850 } 851 852 static __inline struct mbuf * 853 npe_getcl(void) 854 { 855 struct mbuf *m; 856 857 MGETHDR(m, M_DONTWAIT, MT_DATA); 858 if (m != NULL) { 859 MCLGET(m, M_DONTWAIT); 860 if ((m->m_flags & M_EXT) == 0) { 861 m_freem(m); 862 m = NULL; 863 } 864 } 865 return m; 866 } 867 868 static int 869 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 870 { 871 struct npehwbuf *hw; 872 int error; 873 874 if (m == NULL) { 875 m = npe_getcl(); 876 if (m == NULL) 877 return ENOBUFS; 878 } 879 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 880 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 881 /* backload payload and align ip hdr */ 882 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 883 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 884 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 885 BUS_DMA_READ | BUS_DMA_NOWAIT); 886 if (error != 0) { 887 m_freem(m); 888 return error; 889 } 890 hw = npe->ix_hw; 891 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 892 /* NB: NPE requires length be a multiple of 64 */ 893 /* NB: buffer length is shifted in word */ 894 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 895 hw->ix_ne[0].next = 0; 896 npe->ix_m = m; 897 /* Flush the memory in the mbuf */ 898 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 899 BUS_DMASYNC_PREREAD); 900 return 0; 901 } 902 903 /* 904 * RX q processing for a specific NPE. Claim entries 905 * from the hardware queue and pass the frames up the 906 * stack. Pass the rx buffers to the free list. 907 */ 908 static void 909 npe_rxdone(int qid, void *arg) 910 { 911 #define P2V(a, dma) \ 912 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 913 struct npe_softc *sc = arg; 914 struct npedma *dma = &sc->rxdma; 915 uint32_t entry; 916 917 while (ixpqmgr_qread(qid, &entry) == 0) { 918 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 919 struct mbuf *m; 920 921 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 922 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 923 rnd_add_uint32(&sc->rnd_source, entry); 924 /* 925 * Allocate a new mbuf to replenish the rx buffer. 926 * If doing so fails we drop the rx'd frame so we 927 * can reuse the previous mbuf. When we're able to 928 * allocate a new mbuf dispatch the mbuf w/ rx'd 929 * data up the stack and replace it with the newly 930 * allocated one. 931 */ 932 m = npe_getcl(); 933 if (m != NULL) { 934 struct mbuf *mrx = npe->ix_m; 935 struct npehwbuf *hw = npe->ix_hw; 936 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 937 938 /* Flush mbuf memory for rx'd data */ 939 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 940 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 941 942 /* XXX flush hw buffer; works now 'cuz coherent */ 943 /* set m_len etc. per rx frame size */ 944 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 945 mrx->m_pkthdr.len = mrx->m_len; 946 m_set_rcvif(mrx, ifp); 947 /* Don't add M_HASFCS. See below */ 948 949 #if 1 950 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 951 log(LOG_INFO, "%s: too short frame (len=%d)\n", 952 device_xname(sc->sc_dev), 953 mrx->m_pkthdr.len); 954 /* Back out "newly allocated" mbuf. */ 955 m_freem(m); 956 ifp->if_ierrors++; 957 goto fail; 958 } 959 if ((ifp->if_flags & IFF_PROMISC) == 0) { 960 struct ether_header *eh; 961 962 /* 963 * Workaround for "Non-Intel XScale Technology 964 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 965 * matches the filter (both unicast and 966 * multicast). 967 */ 968 eh = mtod(mrx, struct ether_header *); 969 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 970 /* Unicast */ 971 972 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 973 /* Discard it */ 974 #if 0 975 printf("discard it\n"); 976 #endif 977 /* 978 * Back out "newly allocated" 979 * mbuf. 980 */ 981 m_freem(m); 982 goto fail; 983 } 984 } else if (memcmp(eh->ether_dhost, 985 etherbroadcastaddr, 6) == 0) { 986 /* Always accept broadcast packet*/ 987 } else { 988 struct ethercom *ec = &sc->sc_ethercom; 989 struct ether_multi *enm; 990 struct ether_multistep step; 991 int match = 0; 992 993 /* Multicast */ 994 995 ETHER_LOCK(ec); 996 ETHER_FIRST_MULTI(step, ec, enm); 997 while (enm != NULL) { 998 uint64_t lowint, highint, dest; 999 1000 lowint = MAC2UINT64(enm->enm_addrlo); 1001 highint = MAC2UINT64(enm->enm_addrhi); 1002 dest = MAC2UINT64(eh->ether_dhost); 1003 #if 0 1004 printf("%llx\n", lowint); 1005 printf("%llx\n", dest); 1006 printf("%llx\n", highint); 1007 #endif 1008 if ((lowint <= dest) && (dest <= highint)) { 1009 match = 1; 1010 break; 1011 } 1012 ETHER_NEXT_MULTI(step, enm); 1013 } 1014 ETHER_UNLOCK(ec); 1015 1016 if (match == 0) { 1017 /* Discard it */ 1018 #if 0 1019 printf("discard it(M)\n"); 1020 #endif 1021 /* 1022 * Back out "newly allocated" 1023 * mbuf. 1024 */ 1025 m_freem(m); 1026 goto fail; 1027 } 1028 } 1029 } 1030 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1031 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1032 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 1033 /* Back out "newly allocated" mbuf. */ 1034 m_freem(m); 1035 ifp->if_ierrors++; 1036 goto fail; 1037 } 1038 #endif 1039 1040 /* 1041 * Trim FCS! 1042 * NPE always adds the FCS by this driver's setting, 1043 * so we always trim it here and not add M_HASFCS. 1044 */ 1045 m_adj(mrx, -ETHER_CRC_LEN); 1046 1047 /* 1048 * Tap off here if there is a bpf listener. 1049 */ 1050 1051 if_percpuq_enqueue(ifp->if_percpuq, mrx); 1052 } else { 1053 fail: 1054 /* discard frame and re-use mbuf */ 1055 m = npe->ix_m; 1056 } 1057 if (npe_rxbuf_init(sc, npe, m) == 0) { 1058 /* return npe buf to rx free list */ 1059 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1060 } else { 1061 /* XXX should not happen */ 1062 } 1063 } 1064 #undef P2V 1065 } 1066 1067 static void 1068 npe_startxmit(struct npe_softc *sc) 1069 { 1070 struct npedma *dma = &sc->txdma; 1071 int i; 1072 1073 sc->tx_free = NULL; 1074 for (i = 0; i < dma->nbuf; i++) { 1075 struct npebuf *npe = &dma->buf[i]; 1076 if (npe->ix_m != NULL) { 1077 /* NB: should not happen */ 1078 printf("%s: %s: free mbuf at entry %u\n", 1079 device_xname(sc->sc_dev), __func__, i); 1080 m_freem(npe->ix_m); 1081 } 1082 npe->ix_m = NULL; 1083 npe->ix_next = sc->tx_free; 1084 sc->tx_free = npe; 1085 } 1086 } 1087 1088 static void 1089 npe_startrecv(struct npe_softc *sc) 1090 { 1091 struct npedma *dma = &sc->rxdma; 1092 struct npebuf *npe; 1093 int i; 1094 1095 for (i = 0; i < dma->nbuf; i++) { 1096 npe = &dma->buf[i]; 1097 npe_rxbuf_init(sc, npe, npe->ix_m); 1098 /* Set npe buf on rx free list */ 1099 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1100 } 1101 } 1102 1103 static void 1104 npeinit_macreg(struct npe_softc *sc) 1105 { 1106 1107 /* 1108 * Reset MAC core. 1109 */ 1110 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1111 DELAY(NPE_MAC_RESET_DELAY); 1112 /* Configure MAC to generate MDC clock */ 1113 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1114 1115 /* Disable transmitter and reciver in the MAC */ 1116 WR4(sc, NPE_MAC_RX_CNTRL1, 1117 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1118 WR4(sc, NPE_MAC_TX_CNTRL1, 1119 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1120 1121 /* 1122 * Set the MAC core registers. 1123 */ 1124 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1125 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1126 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1127 /* Thresholds determined by NPE firmware FS */ 1128 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1129 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1130 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1131 /* tx fifo threshold (bytes) */ 1132 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1133 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1134 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1135 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1136 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1137 /* assumes MII mode */ 1138 WR4(sc, NPE_MAC_TX_CNTRL1, 1139 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1140 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1141 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1142 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1143 /* XXX pad strip? */ 1144 WR4(sc, NPE_MAC_RX_CNTRL1, 1145 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1146 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1147 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1148 } 1149 1150 static void 1151 npeinit_resetcb(void *xsc) 1152 { 1153 struct npe_softc *sc = xsc; 1154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1155 uint32_t msg[2]; 1156 1157 ifp->if_oerrors++; 1158 npeinit_locked(sc); 1159 1160 msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1161 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1162 msg[1] = 0; 1163 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1164 } 1165 1166 /* 1167 * Reset and initialize the chip 1168 */ 1169 static void 1170 npeinit_locked(void *xsc) 1171 { 1172 struct npe_softc *sc = xsc; 1173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1174 1175 /* Cancel any pending I/O. */ 1176 npestop(ifp, 0); 1177 1178 /* Reset the chip to a known state. */ 1179 npeinit_macreg(sc); 1180 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1181 ether_mediachange(ifp); 1182 npe_setmcast(sc); 1183 1184 npe_startxmit(sc); 1185 npe_startrecv(sc); 1186 1187 ifp->if_flags |= IFF_RUNNING; 1188 ifp->if_flags &= ~IFF_OACTIVE; 1189 ifp->if_timer = 0; /* just in case */ 1190 1191 /* Enable transmitter and reciver in the MAC */ 1192 WR4(sc, NPE_MAC_RX_CNTRL1, 1193 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1194 WR4(sc, NPE_MAC_TX_CNTRL1, 1195 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1196 1197 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1198 } 1199 1200 static int 1201 npeinit(struct ifnet *ifp) 1202 { 1203 struct npe_softc *sc = ifp->if_softc; 1204 int s; 1205 1206 s = splnet(); 1207 npeinit_locked(sc); 1208 splx(s); 1209 1210 return 0; 1211 } 1212 1213 /* 1214 * Defragment an mbuf chain, returning at most maxfrags separate 1215 * mbufs+clusters. If this is not possible NULL is returned and 1216 * the original mbuf chain is left in its present (potentially 1217 * modified) state. We use two techniques: collapsing consecutive 1218 * mbufs and replacing consecutive mbufs by a cluster. 1219 */ 1220 static __inline struct mbuf * 1221 npe_defrag(struct mbuf *m0) 1222 { 1223 struct mbuf *m; 1224 1225 MGETHDR(m, M_DONTWAIT, MT_DATA); 1226 if (m == NULL) 1227 return NULL; 1228 m_copy_pkthdr(m, m0); 1229 1230 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1231 MCLGET(m, M_DONTWAIT); 1232 if ((m->m_flags & M_EXT) == 0) { 1233 m_freem(m); 1234 return NULL; 1235 } 1236 } 1237 1238 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1239 m_freem(m0); 1240 1241 return m; 1242 } 1243 1244 /* 1245 * Dequeue packets and place on the h/w transmit queue. 1246 */ 1247 static void 1248 npestart(struct ifnet *ifp) 1249 { 1250 struct npe_softc *sc = ifp->if_softc; 1251 struct npebuf *npe; 1252 struct npehwbuf *hw; 1253 struct mbuf *m, *n; 1254 bus_dma_segment_t *segs; 1255 int nseg, len, error, i; 1256 uint32_t next; 1257 1258 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1259 return; 1260 1261 while (sc->tx_free != NULL) { 1262 IFQ_DEQUEUE(&ifp->if_snd, m); 1263 if (m == NULL) 1264 break; 1265 npe = sc->tx_free; 1266 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1267 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1268 if (error == EFBIG) { 1269 n = npe_defrag(m); 1270 if (n == NULL) { 1271 printf("%s: %s: too many fragments\n", 1272 device_xname(sc->sc_dev), __func__); 1273 m_freem(m); 1274 return; /* XXX? */ 1275 } 1276 m = n; 1277 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1278 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1279 } 1280 if (error != 0) { 1281 printf("%s: %s: error %u\n", 1282 device_xname(sc->sc_dev), __func__, error); 1283 m_freem(m); 1284 return; /* XXX? */ 1285 } 1286 sc->tx_free = npe->ix_next; 1287 1288 /* 1289 * Tap off here if there is a bpf listener. 1290 */ 1291 bpf_mtap(ifp, m, BPF_D_OUT); 1292 1293 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1294 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1295 1296 npe->ix_m = m; 1297 hw = npe->ix_hw; 1298 len = m->m_pkthdr.len; 1299 nseg = npe->ix_map->dm_nsegs; 1300 segs = npe->ix_map->dm_segs; 1301 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1302 for (i = 0; i < nseg; i++) { 1303 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1304 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1305 hw->ix_ne[i].next = htobe32(next); 1306 1307 len = 0; /* zero for segments > 1 */ 1308 next += sizeof(hw->ix_ne[0]); 1309 } 1310 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1311 /* XXX flush descriptor instead of using uncached memory */ 1312 1313 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1314 __func__, sc->tx_qid, npe->ix_neaddr, 1315 hw->ix_ne[0].data, hw->ix_ne[0].len); 1316 /* stick it on the tx q */ 1317 /* XXX add vlan priority */ 1318 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1319 1320 ifp->if_timer = 5; 1321 } 1322 if (sc->tx_free == NULL) 1323 ifp->if_flags |= IFF_OACTIVE; 1324 } 1325 1326 static void 1327 npe_stopxmit(struct npe_softc *sc) 1328 { 1329 struct npedma *dma = &sc->txdma; 1330 int i; 1331 1332 /* XXX qmgr */ 1333 for (i = 0; i < dma->nbuf; i++) { 1334 struct npebuf *npe = &dma->buf[i]; 1335 1336 if (npe->ix_m != NULL) { 1337 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1338 m_freem(npe->ix_m); 1339 npe->ix_m = NULL; 1340 } 1341 } 1342 } 1343 1344 static void 1345 npe_stoprecv(struct npe_softc *sc) 1346 { 1347 struct npedma *dma = &sc->rxdma; 1348 int i; 1349 1350 /* XXX qmgr */ 1351 for (i = 0; i < dma->nbuf; i++) { 1352 struct npebuf *npe = &dma->buf[i]; 1353 1354 if (npe->ix_m != NULL) { 1355 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1356 m_freem(npe->ix_m); 1357 npe->ix_m = NULL; 1358 } 1359 } 1360 } 1361 1362 /* 1363 * Turn off interrupts, and stop the nic. 1364 */ 1365 void 1366 npestop(struct ifnet *ifp, int disable) 1367 { 1368 struct npe_softc *sc = ifp->if_softc; 1369 1370 /* Disable transmitter and reciver in the MAC */ 1371 WR4(sc, NPE_MAC_RX_CNTRL1, 1372 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1373 WR4(sc, NPE_MAC_TX_CNTRL1, 1374 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1375 1376 callout_stop(&sc->sc_tick_ch); 1377 1378 npe_stopxmit(sc); 1379 npe_stoprecv(sc); 1380 /* XXX go into loopback & drain q's? */ 1381 /* XXX but beware of disabling tx above */ 1382 1383 /* 1384 * The MAC core rx/tx disable may leave the MAC hardware in an 1385 * unpredictable state. A hw reset is executed before resetting 1386 * all the MAC parameters to a known value. 1387 */ 1388 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1389 DELAY(NPE_MAC_RESET_DELAY); 1390 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1391 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1392 1393 ifp->if_timer = 0; 1394 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1395 } 1396 1397 void 1398 npewatchdog(struct ifnet *ifp) 1399 { 1400 struct npe_softc *sc = ifp->if_softc; 1401 int s; 1402 1403 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1404 s = splnet(); 1405 ifp->if_oerrors++; 1406 npeinit_locked(sc); 1407 splx(s); 1408 } 1409 1410 static int 1411 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1412 { 1413 struct npe_softc *sc = ifp->if_softc; 1414 struct ifreq *ifr = (struct ifreq *) data; 1415 int s, error = 0; 1416 1417 s = splnet(); 1418 1419 switch (cmd) { 1420 case SIOCSIFMEDIA: 1421 #if 0 /* not yet */ 1422 /* Flow control requires full-duplex mode. */ 1423 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1424 (ifr->ifr_media & IFM_FDX) == 0) 1425 ifr->ifr_media &= ~IFM_ETH_FMASK; 1426 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1427 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1428 /* We can do both TXPAUSE and RXPAUSE. */ 1429 ifr->ifr_media |= 1430 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1431 } 1432 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1433 } 1434 #endif 1435 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1436 break; 1437 case SIOCSIFFLAGS: 1438 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) { 1439 /* 1440 * If interface is marked down and it is running, 1441 * then stop and disable it. 1442 */ 1443 (*ifp->if_stop)(ifp, 1); 1444 } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) { 1445 /* 1446 * If interface is marked up and it is stopped, then 1447 * start it. 1448 */ 1449 error = (*ifp->if_init)(ifp); 1450 } else if ((ifp->if_flags & IFF_UP) != 0) { 1451 u_short diff; 1452 1453 /* Up (AND RUNNING). */ 1454 1455 diff = (ifp->if_flags ^ sc->sc_if_flags) 1456 & (IFF_PROMISC | IFF_ALLMULTI); 1457 if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1458 /* 1459 * If the difference bettween last flag and 1460 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1461 * set multicast filter only (don't reset to 1462 * prevent link down). 1463 */ 1464 npe_setmcast(sc); 1465 } else { 1466 /* 1467 * Reset the interface to pick up changes in 1468 * any other flags that affect the hardware 1469 * state. 1470 */ 1471 error = (*ifp->if_init)(ifp); 1472 } 1473 } 1474 sc->sc_if_flags = ifp->if_flags; 1475 break; 1476 default: 1477 error = ether_ioctl(ifp, cmd, data); 1478 if (error == ENETRESET) { 1479 /* 1480 * Multicast list has changed; set the hardware filter 1481 * accordingly. 1482 */ 1483 npe_setmcast(sc); 1484 error = 0; 1485 } 1486 } 1487 1488 npestart(ifp); 1489 1490 splx(s); 1491 return error; 1492 } 1493 1494 /* 1495 * Setup a traffic class -> rx queue mapping. 1496 */ 1497 static int 1498 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1499 { 1500 int npeid = npeconfig[sc->sc_unit].npeid; 1501 uint32_t msg[2]; 1502 1503 msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1504 | classix; 1505 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1506 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1507 } 1508 1509 /* 1510 * Update and reset the statistics in the NPE. 1511 */ 1512 static int 1513 npe_updatestats(struct npe_softc *sc) 1514 { 1515 uint32_t msg[2]; 1516 1517 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1518 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1519 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1520 } 1521 1522 #if 0 1523 /* 1524 * Get the current statistics block. 1525 */ 1526 static int 1527 npe_getstats(struct npe_softc *sc) 1528 { 1529 uint32_t msg[2]; 1530 1531 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1532 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1533 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1534 } 1535 1536 /* 1537 * Query the image id of the loaded firmware. 1538 */ 1539 static uint32_t 1540 npe_getimageid(struct npe_softc *sc) 1541 { 1542 uint32_t msg[2]; 1543 1544 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1545 msg[1] = 0; 1546 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1547 } 1548 1549 /* 1550 * Enable/disable loopback. 1551 */ 1552 static int 1553 npe_setloopback(struct npe_softc *sc, int ena) 1554 { 1555 uint32_t msg[2]; 1556 1557 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1558 msg[1] = 0; 1559 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1560 } 1561 #endif 1562 1563 /* 1564 * MII bus support routines. 1565 * 1566 * NB: ixp425 has one PHY per NPE 1567 */ 1568 static uint32_t 1569 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1570 { 1571 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1572 uint32_t v; 1573 1574 /* NB: registers are known to be sequential */ 1575 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1576 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1577 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1578 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1579 return v; 1580 #undef MII_RD4 1581 } 1582 1583 static void 1584 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1585 { 1586 #define MII_WR4(sc, reg, v) \ 1587 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1588 1589 /* NB: registers are known to be sequential */ 1590 MII_WR4(sc, reg+0, cmd & 0xff); 1591 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1592 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1593 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1594 #undef MII_WR4 1595 } 1596 1597 static int 1598 npe_mii_mdio_wait(struct npe_softc *sc) 1599 { 1600 #define MAXTRIES 100 /* XXX */ 1601 uint32_t v; 1602 int i; 1603 1604 for (i = 0; i < MAXTRIES; i++) { 1605 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1606 if ((v & NPE_MII_GO) == 0) 1607 return 0; 1608 } 1609 return ETIMEDOUT; 1610 #undef MAXTRIES 1611 } 1612 1613 static int 1614 npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val) 1615 { 1616 struct npe_softc *sc = device_private(self); 1617 uint32_t v; 1618 1619 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1620 return -1; 1621 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1622 | NPE_MII_GO; 1623 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1624 if (npe_mii_mdio_wait(sc) == 0) 1625 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1626 else 1627 v = 0xffff | NPE_MII_READ_FAIL; 1628 1629 if ((v & NPE_MII_READ_FAIL) != 0) 1630 return -1; 1631 1632 *val = v & 0xffff; 1633 return 0; 1634 #undef MAXTRIES 1635 } 1636 1637 static int 1638 npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val) 1639 { 1640 struct npe_softc *sc = device_private(self); 1641 uint32_t v; 1642 1643 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1644 return -1; 1645 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1646 | val | NPE_MII_WRITE 1647 | NPE_MII_GO; 1648 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1649 1650 return npe_mii_mdio_wait(sc); 1651 } 1652 1653 static void 1654 npe_miibus_statchg(struct ifnet *ifp) 1655 { 1656 struct npe_softc *sc = ifp->if_softc; 1657 uint32_t tx1, rx1; 1658 uint32_t randoff; 1659 1660 /* Sync MAC duplex state */ 1661 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1662 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1663 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1664 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1665 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1666 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1667 } else { 1668 struct timeval now; 1669 getmicrotime(&now); 1670 randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1671 & 0x7f; 1672 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1673 + randoff); 1674 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1675 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1676 } 1677 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1678 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1679 } 1680
Indexes created Thu Oct 02 10:09:58 GMT 2025