ixp425_if_npe.c revision 1.45
1 /* $NetBSD: ixp425_if_npe.c,v 1.45 2020/01/29 06:05:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #if 0 29 __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30 #endif 31 __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.45 2020/01/29 06:05:31 thorpej Exp $"); 32 33 /* 34 * Intel XScale NPE Ethernet driver. 35 * 36 * This driver handles the two ports present on the IXP425. 37 * Packet processing is done by the Network Processing Engines 38 * (NPE's) that work together with a MAC and PHY. The MAC 39 * is also mapped to the XScale cpu; the PHY is accessed via 40 * the MAC. NPE-XScale communication happens through h/w 41 * queues managed by the Q Manager block. 42 * 43 * The code here replaces the ethAcc, ethMii, and ethDB classes 44 * in the Intel Access Library (IAL) and the OS-specific driver. 45 * 46 * XXX add vlan support 47 * XXX NPE-C port doesn't work yet 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/socket.h> 58 #include <sys/endian.h> 59 #include <sys/ioctl.h> 60 #include <sys/syslog.h> 61 #include <sys/bus.h> 62 #include <sys/rndsource.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 #include <net/bpf.h> 69 70 #include <arm/xscale/ixp425reg.h> 71 #include <arm/xscale/ixp425var.h> 72 #include <arm/xscale/ixp425_qmgr.h> 73 #include <arm/xscale/ixp425_npevar.h> 74 #include <arm/xscale/ixp425_if_npereg.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include "locators.h" 79 80 struct npebuf { 81 struct npebuf *ix_next; /* chain to next buffer */ 82 void *ix_m; /* backpointer to mbuf */ 83 bus_dmamap_t ix_map; /* bus dma map for associated data */ 84 struct npehwbuf *ix_hw; /* associated h/w block */ 85 uint32_t ix_neaddr; /* phys address of ix_hw */ 86 }; 87 88 struct npedma { 89 const char* name; 90 int nbuf; /* # npebuf's allocated */ 91 bus_dmamap_t m_map; 92 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 93 bus_dmamap_t buf_map; 94 bus_addr_t buf_phys; /* phys addr of buffers */ 95 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 96 }; 97 98 struct npe_softc { 99 device_t sc_dev; 100 struct ethercom sc_ethercom; 101 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 102 struct mii_data sc_mii; 103 bus_space_tag_t sc_iot; 104 bus_dma_tag_t sc_dt; 105 bus_space_handle_t sc_ioh; /* MAC register window */ 106 bus_space_handle_t sc_miih; /* MII register window */ 107 struct ixpnpe_softc *sc_npe; /* NPE support */ 108 int sc_unit; 109 int sc_phy; 110 struct callout sc_tick_ch; /* Tick callout */ 111 struct npedma txdma; 112 struct npebuf *tx_free; /* list of free tx buffers */ 113 struct npedma rxdma; 114 int rx_qid; /* rx qid */ 115 int rx_freeqid; /* rx free buffers qid */ 116 int tx_qid; /* tx qid */ 117 int tx_doneqid; /* tx completed qid */ 118 struct npestats *sc_stats; 119 bus_dmamap_t sc_stats_map; 120 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 121 u_short sc_if_flags; /* keep last if_flags */ 122 krndsource_t rnd_source; /* random source */ 123 }; 124 125 /* 126 * Per-unit static configuration for IXP425. The tx and 127 * rx free Q id's are fixed by the NPE microcode. The 128 * rx Q id's are programmed to be separate to simplify 129 * multi-port processing. It may be better to handle 130 * all traffic through one Q (as done by the Intel drivers). 131 * 132 * Note that the PHY's are accessible only from MAC A 133 * on the IXP425. This and other platform-specific 134 * assumptions probably need to be handled through hints. 135 */ 136 static const struct { 137 const char *desc; /* device description */ 138 int npeid; /* NPE assignment */ 139 int macport; /* Port number of the MAC */ 140 uint32_t imageid; /* NPE firmware image id */ 141 uint32_t regbase; 142 int regsize; 143 uint32_t miibase; 144 int miisize; 145 uint8_t rx_qid; 146 uint8_t rx_freeqid; 147 uint8_t tx_qid; 148 uint8_t tx_doneqid; 149 } npeconfig[NPE_PORTS_MAX] = { 150 { .desc = "IXP NPE-B", 151 .npeid = NPE_B, 152 .macport = 0x10, 153 .imageid = IXP425_NPE_B_IMAGEID, 154 .regbase = IXP425_MAC_A_HWBASE, 155 .regsize = IXP425_MAC_A_SIZE, 156 .miibase = IXP425_MAC_A_HWBASE, 157 .miisize = IXP425_MAC_A_SIZE, 158 .rx_qid = 4, 159 .rx_freeqid = 27, 160 .tx_qid = 24, 161 .tx_doneqid = 31 162 }, 163 { .desc = "IXP NPE-C", 164 .npeid = NPE_C, 165 .macport = 0x20, 166 .imageid = IXP425_NPE_C_IMAGEID, 167 .regbase = IXP425_MAC_B_HWBASE, 168 .regsize = IXP425_MAC_B_SIZE, 169 .miibase = IXP425_MAC_A_HWBASE, 170 .miisize = IXP425_MAC_A_SIZE, 171 .rx_qid = 12, 172 .rx_freeqid = 28, 173 .tx_qid = 25, 174 .tx_doneqid = 31 175 }, 176 }; 177 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 178 179 static __inline uint32_t 180 RD4(struct npe_softc *sc, bus_size_t off) 181 { 182 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 183 } 184 185 static __inline void 186 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 187 { 188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 189 } 190 191 static int npe_activate(struct npe_softc *); 192 #if 0 193 static void npe_deactivate(struct npe_softc *); 194 #endif 195 static void npe_ifmedia_status(struct ifnet *, struct ifmediareq *); 196 static void npe_setmac(struct npe_softc *, const u_char *); 197 static void npe_getmac(struct npe_softc *); 198 static void npe_txdone(int, void *); 199 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 200 struct mbuf *); 201 static void npe_rxdone(int, void *); 202 static void npeinit_macreg(struct npe_softc *); 203 static int npeinit(struct ifnet *); 204 static void npeinit_resetcb(void *); 205 static void npeinit_locked(void *); 206 static void npestart(struct ifnet *); 207 static void npestop(struct ifnet *, int); 208 static void npewatchdog(struct ifnet *); 209 static int npeioctl(struct ifnet *, u_long, void *); 210 211 static int npe_setrxqosentry(struct npe_softc *, int, int, int); 212 static int npe_updatestats(struct npe_softc *); 213 #if 0 214 static int npe_getstats(struct npe_softc *); 215 static uint32_t npe_getimageid(struct npe_softc *); 216 static int npe_setloopback(struct npe_softc *, int); 217 #endif 218 219 static int npe_miibus_readreg(device_t, int, int, uint16_t *); 220 static int npe_miibus_writereg(device_t, int, int, uint16_t); 221 static void npe_miibus_statchg(struct ifnet *); 222 223 static int npe_debug; 224 #define DPRINTF(sc, fmt, ...) do { \ 225 if (npe_debug) printf(fmt, __VA_ARGS__); \ 226 } while (0) 227 #define DPRINTFn(n, sc, fmt, ...) do { \ 228 if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 229 } while (0) 230 231 #define NPE_TXBUF 128 232 #define NPE_RXBUF 64 233 234 #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 235 + ((uint64_t)addr[1] << 32) \ 236 + ((uint64_t)addr[2] << 24) \ 237 + ((uint64_t)addr[3] << 16) \ 238 + ((uint64_t)addr[4] << 8) \ 239 + (uint64_t)addr[5]) 240 241 /* NB: all tx done processing goes through one queue */ 242 static int tx_doneqid = -1; 243 244 void (*npe_getmac_md)(int, uint8_t *); 245 246 static int npe_match(device_t, cfdata_t, void *); 247 static void npe_attach(device_t, device_t, void *); 248 249 CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 250 npe_match, npe_attach, NULL, NULL); 251 252 static int 253 npe_match(device_t parent, cfdata_t cf, void *arg) 254 { 255 struct ixpnpe_attach_args *na = arg; 256 257 return (na->na_unit == NPE_B || na->na_unit == NPE_C); 258 } 259 260 static void 261 npe_attach(device_t parent, device_t self, void *arg) 262 { 263 struct npe_softc *sc = device_private(self); 264 struct ixpnpe_softc *isc = device_private(parent); 265 struct ixpnpe_attach_args *na = arg; 266 struct ifnet *ifp; 267 struct mii_data * const mii = &sc->sc_mii; 268 269 aprint_naive("\n"); 270 aprint_normal(": Ethernet co-processor\n"); 271 272 sc->sc_dev = self; 273 sc->sc_iot = na->na_iot; 274 sc->sc_dt = na->na_dt; 275 sc->sc_npe = na->na_npe; 276 sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 277 sc->sc_phy = na->na_phy; 278 279 memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 280 memset(mii, 0, sizeof(*mii)); 281 282 callout_init(&sc->sc_tick_ch, 0); 283 284 if (npe_activate(sc)) { 285 aprint_error_dev(sc->sc_dev, 286 "Failed to activate NPE (missing microcode?)\n"); 287 return; 288 } 289 290 npe_getmac(sc); 291 npeinit_macreg(sc); 292 293 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 294 ether_sprintf(sc->sc_enaddr)); 295 296 ifp = &sc->sc_ethercom.ec_if; 297 mii->mii_ifp = ifp; 298 mii->mii_readreg = npe_miibus_readreg; 299 mii->mii_writereg = npe_miibus_writereg; 300 mii->mii_statchg = npe_miibus_statchg; 301 sc->sc_ethercom.ec_mii = mii; 302 303 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 304 npe_ifmedia_status); 305 306 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 307 MII_OFFSET_ANY, MIIF_DOPAUSE); 308 if (LIST_FIRST(&mii->mii_phys) == NULL) { 309 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 310 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 311 } else 312 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 313 314 ifp->if_softc = sc; 315 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 317 ifp->if_start = npestart; 318 ifp->if_ioctl = npeioctl; 319 ifp->if_watchdog = npewatchdog; 320 ifp->if_init = npeinit; 321 ifp->if_stop = npestop; 322 IFQ_SET_READY(&ifp->if_snd); 323 324 /* VLAN capable */ 325 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 326 327 if_attach(ifp); 328 if_deferred_start_init(ifp, NULL); 329 ether_ifattach(ifp, sc->sc_enaddr); 330 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 331 RND_TYPE_NET, RND_FLAG_DEFAULT); 332 333 /* callback function to reset MAC */ 334 isc->macresetcbfunc = npeinit_resetcb; 335 isc->macresetcbarg = sc; 336 } 337 338 /* 339 * Compute and install the multicast filter. 340 */ 341 static void 342 npe_setmcast(struct npe_softc *sc) 343 { 344 struct ethercom *ec = &sc->sc_ethercom; 345 struct ifnet *ifp = &ec->ec_if; 346 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 347 uint32_t reg; 348 uint32_t msg[2]; 349 int i; 350 351 /* Always use filter. Is here a correct position? */ 352 reg = RD4(sc, NPE_MAC_RX_CNTRL1); 353 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 354 355 if (ifp->if_flags & IFF_PROMISC) { 356 memset(mask, 0, ETHER_ADDR_LEN); 357 memset(addr, 0, ETHER_ADDR_LEN); 358 } else if (ifp->if_flags & IFF_ALLMULTI) { 359 static const uint8_t allmulti[ETHER_ADDR_LEN] = 360 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 361 all_multi: 362 memcpy(mask, allmulti, ETHER_ADDR_LEN); 363 memcpy(addr, allmulti, ETHER_ADDR_LEN); 364 } else { 365 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 366 struct ether_multistep step; 367 struct ether_multi *enm; 368 369 memset(clr, 0, ETHER_ADDR_LEN); 370 memset(set, 0xff, ETHER_ADDR_LEN); 371 372 ETHER_LOCK(ec); 373 ETHER_FIRST_MULTI(step, ec, enm); 374 while (enm != NULL) { 375 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 376 ETHER_ADDR_LEN)) { 377 ifp->if_flags |= IFF_ALLMULTI; 378 ETHER_UNLOCK(ec); 379 goto all_multi; 380 } 381 382 for (i = 0; i < ETHER_ADDR_LEN; i++) { 383 clr[i] |= enm->enm_addrlo[i]; 384 set[i] &= enm->enm_addrlo[i]; 385 } 386 387 ETHER_NEXT_MULTI(step, enm); 388 } 389 ETHER_UNLOCK(ec); 390 391 for (i = 0; i < ETHER_ADDR_LEN; i++) { 392 mask[i] = set[i] | ~clr[i]; 393 addr[i] = set[i]; 394 } 395 } 396 397 /* 398 * Write the mask and address registers. 399 */ 400 for (i = 0; i < ETHER_ADDR_LEN; i++) { 401 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 402 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 403 } 404 405 msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 406 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 407 msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 408 | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 409 | (addr[5] << 8) | mask[5]; 410 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 411 } 412 413 static int 414 npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 415 const char *name, int nbuf, int maxseg) 416 { 417 bus_dma_segment_t seg; 418 int rseg, error, i; 419 void *hwbuf; 420 size_t size; 421 422 memset(dma, 0, sizeof(*dma)); 423 424 dma->name = name; 425 dma->nbuf = nbuf; 426 427 size = nbuf * sizeof(struct npehwbuf); 428 429 /* XXX COHERENT for now */ 430 error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 431 1, &rseg, BUS_DMA_NOWAIT); 432 if (error) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to %s for %s %s buffers, error %u\n", 435 "allocate memory", dma->name, "h/w", error); 436 } 437 438 error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 440 if (error) { 441 aprint_error_dev(sc->sc_dev, 442 "unable to %s for %s %s buffers, error %u\n", 443 "map memory", dma->name, "h/w", error); 444 free_dmamem: 445 bus_dmamem_free(sc->sc_dt, &seg, rseg); 446 return error; 447 } 448 dma->hwbuf = (void *)hwbuf; 449 450 error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 451 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 452 if (error) { 453 aprint_error_dev(sc->sc_dev, 454 "unable to %s for %s %s buffers, error %u\n", 455 "create map", dma->name, "h/w", error); 456 unmap_dmamem: 457 dma->hwbuf = NULL; 458 bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 459 goto free_dmamem; 460 } 461 462 error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 463 BUS_DMA_NOWAIT); 464 if (error) { 465 aprint_error_dev(sc->sc_dev, 466 "unable to %s for %s %s buffers, error %u\n", 467 "load map", dma->name, "h/w", error); 468 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 469 goto unmap_dmamem; 470 } 471 472 /* XXX M_TEMP */ 473 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, 474 M_WAITOK | M_ZERO); 475 dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 476 for (i = 0; i < dma->nbuf; i++) { 477 struct npebuf *npe = &dma->buf[i]; 478 struct npehwbuf *hw = &dma->hwbuf[i]; 479 480 /* Calculate offset to shared area */ 481 npe->ix_neaddr = dma->buf_phys + 482 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 483 KASSERT((npe->ix_neaddr & 0x1f) == 0); 484 error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 485 MCLBYTES, 0, 0, &npe->ix_map); 486 if (error != 0) { 487 aprint_error_dev(sc->sc_dev, 488 "unable to %s for %s buffer %u, error %u\n", 489 "create dmamap", dma->name, i, error); 490 /* XXXSCW: Free up maps... */ 491 return error; 492 } 493 npe->ix_hw = hw; 494 } 495 bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 496 BUS_DMASYNC_PREWRITE); 497 return 0; 498 } 499 500 #if 0 501 static void 502 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 503 { 504 int i; 505 506 /* XXXSCW: Clean this up */ 507 508 if (dma->hwbuf != NULL) { 509 for (i = 0; i < dma->nbuf; i++) { 510 struct npebuf *npe = &dma->buf[i]; 511 bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 512 } 513 bus_dmamap_unload(sc->sc_dt, dma->buf_map); 514 bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 515 bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 516 } 517 if (dma->buf != NULL) 518 free(dma->buf, M_TEMP); 519 memset(dma, 0, sizeof(*dma)); 520 } 521 #endif 522 523 static int 524 npe_activate(struct npe_softc *sc) 525 { 526 bus_dma_segment_t seg; 527 int unit = sc->sc_unit; 528 int error, i, rseg; 529 void *statbuf; 530 531 /* load NPE firmware and start it running */ 532 error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 533 if (error != 0) 534 return error; 535 536 if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 537 npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 538 aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 539 npeconfig[unit].regbase, npeconfig[unit].regsize); 540 return ENOMEM; 541 } 542 543 if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 544 /* 545 * The PHY's are only accessible from one MAC (it appears) 546 * so for other MAC's setup an additional mapping for 547 * frobbing the PHY registers. 548 */ 549 if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 550 npeconfig[unit].miisize, 0, &sc->sc_miih)) { 551 aprint_error_dev(sc->sc_dev, 552 "Cannot map MII registers 0x%x:0x%x\n", 553 npeconfig[unit].miibase, npeconfig[unit].miisize); 554 return ENOMEM; 555 } 556 } else 557 sc->sc_miih = sc->sc_ioh; 558 error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 559 if (error != 0) 560 return error; 561 error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 562 if (error != 0) 563 return error; 564 565 /* setup statistics block */ 566 error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 567 sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 568 if (error) { 569 aprint_error_dev(sc->sc_dev, 570 "unable to %s for %s, error %u\n", 571 "allocate memory", "stats block", error); 572 return error; 573 } 574 575 error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 576 &statbuf, BUS_DMA_NOWAIT); 577 if (error) { 578 aprint_error_dev(sc->sc_dev, 579 "unable to %s for %s, error %u\n", 580 "map memory", "stats block", error); 581 return error; 582 } 583 sc->sc_stats = (void *)statbuf; 584 585 error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 586 sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 587 &sc->sc_stats_map); 588 if (error) { 589 aprint_error_dev(sc->sc_dev, 590 "unable to %s for %s, error %u\n", 591 "create map", "stats block", error); 592 return error; 593 } 594 595 error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 596 sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 597 if (error) { 598 aprint_error_dev(sc->sc_dev, 599 "unable to %s for %s, error %u\n", 600 "load map", "stats block", error); 601 return error; 602 } 603 sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 604 605 /* XXX disable half-bridge LEARNING+FILTERING feature */ 606 607 /* 608 * Setup h/w rx/tx queues. There are four q's: 609 * rx inbound q of rx'd frames 610 * rx_free pool of ixpbuf's for receiving frames 611 * tx outbound q of frames to send 612 * tx_done q of tx frames that have been processed 613 * 614 * The NPE handles the actual tx/rx process and the q manager 615 * handles the queues. The driver just writes entries to the 616 * q manager mailbox's and gets callbacks when there are rx'd 617 * frames to process or tx'd frames to reap. These callbacks 618 * are controlled by the q configurations; e.g. we get a 619 * callback when tx_done has 2 or more frames to process and 620 * when the rx q has at least one frame. These setings can 621 * changed at the time the q is configured. 622 */ 623 sc->rx_qid = npeconfig[unit].rx_qid; 624 ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 625 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 626 sc->rx_freeqid = npeconfig[unit].rx_freeqid; 627 ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 628 /* tell the NPE to direct all traffic to rx_qid */ 629 #if 0 630 for (i = 0; i < 8; i++) 631 #else 632 printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 633 for (i = 0; i < 4; i++) 634 #endif 635 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 636 637 sc->tx_qid = npeconfig[unit].tx_qid; 638 sc->tx_doneqid = npeconfig[unit].tx_doneqid; 639 ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 640 if (tx_doneqid == -1) { 641 ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 642 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 643 tx_doneqid = sc->tx_doneqid; 644 } 645 646 KASSERT(npes[npeconfig[unit].npeid] == NULL); 647 npes[npeconfig[unit].npeid] = sc; 648 649 return 0; 650 } 651 652 #if 0 653 static void 654 npe_deactivate(struct npe_softc *sc); 655 { 656 int unit = sc->sc_unit; 657 658 npes[npeconfig[unit].npeid] = NULL; 659 660 /* XXX disable q's */ 661 if (sc->sc_npe != NULL) 662 ixpnpe_stop(sc->sc_npe); 663 if (sc->sc_stats != NULL) { 664 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 665 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 666 sc->sc_stats_map); 667 bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 668 } 669 if (sc->sc_stats_tag != NULL) 670 bus_dma_tag_destroy(sc->sc_stats_tag); 671 npe_dma_destroy(sc, &sc->txdma); 672 npe_dma_destroy(sc, &sc->rxdma); 673 bus_generic_detach(sc->sc_dev); 674 if (sc->sc_mii) 675 device_delete_child(sc->sc_dev, sc->sc_mii); 676 #if 0 677 /* XXX sc_ioh and sc_miih */ 678 if (sc->mem_res) 679 bus_release_resource(dev, SYS_RES_IOPORT, 680 rman_get_rid(sc->mem_res), sc->mem_res); 681 sc->mem_res = 0; 682 #endif 683 } 684 #endif 685 686 /* 687 * Notify the world which media we're using. 688 */ 689 static void 690 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 691 { 692 struct npe_softc *sc = ifp->if_softc; 693 694 mii_pollstat(&sc->sc_mii); 695 696 ifmr->ifm_active = sc->sc_mii.mii_media_active; 697 ifmr->ifm_status = sc->sc_mii.mii_media_status; 698 } 699 700 static void 701 npe_addstats(struct npe_softc *sc) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 struct npestats *ns = sc->sc_stats; 705 706 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 707 if_statadd_ref(nsr, if_oerrors, 708 be32toh(ns->dot3StatsInternalMacTransmitErrors) 709 + be32toh(ns->dot3StatsCarrierSenseErrors) 710 + be32toh(ns->TxVLANIdFilterDiscards) 711 ); 712 if_statadd_ref(nsr, if_ierrors, 713 be32toh(ns->dot3StatsFCSErrors) 714 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 715 + be32toh(ns->RxOverrunDiscards) 716 + be32toh(ns->RxUnderflowEntryDiscards) 717 ); 718 if_statadd_ref(nsr, if_collisions, 719 be32toh(ns->dot3StatsSingleCollisionFrames) 720 + be32toh(ns->dot3StatsMultipleCollisionFrames) 721 ); 722 IF_STAT_PUTREF(ifp); 723 } 724 725 static void 726 npe_tick(void *xsc) 727 { 728 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 729 struct npe_softc *sc = xsc; 730 uint32_t msg[2]; 731 732 /* 733 * NB: to avoid sleeping with the softc lock held we 734 * split the NPE msg processing into two parts. The 735 * request for statistics is sent w/o waiting for a 736 * reply and then on the next tick we retrieve the 737 * results. This works because npe_tick is the only 738 * code that talks via the mailbox's (except at setup). 739 * This likely can be handled better. 740 */ 741 if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 742 bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 743 sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 744 npe_addstats(sc); 745 } 746 npe_updatestats(sc); 747 mii_tick(&sc->sc_mii); 748 749 /* Schedule next poll */ 750 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 751 #undef ACK 752 } 753 754 static void 755 npe_setmac(struct npe_softc *sc, const u_char *eaddr) 756 { 757 758 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 759 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 760 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 761 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 762 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 763 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 764 } 765 766 static void 767 npe_getmac(struct npe_softc *sc) 768 { 769 uint8_t *eaddr = sc->sc_enaddr; 770 771 if (npe_getmac_md != NULL) { 772 (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 773 } else { 774 /* 775 * Some system's unicast address appears to be loaded from 776 * EEPROM on reset 777 */ 778 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 779 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 780 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 781 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 782 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 783 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 784 } 785 } 786 787 struct txdone { 788 struct npebuf *head; 789 struct npebuf **tail; 790 int count; 791 }; 792 793 static __inline void 794 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 795 { 796 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 797 798 *td->tail = sc->tx_free; 799 sc->tx_free = td->head; 800 /* 801 * We're no longer busy, so clear the busy flag and call the 802 * start routine to xmit more packets. 803 */ 804 if_statadd(ifp, if_opackets, td->count); 805 ifp->if_flags &= ~IFF_OACTIVE; 806 ifp->if_timer = 0; 807 if_schedule_deferred_start(ifp); 808 } 809 810 /* 811 * Q manager callback on tx done queue. Reap mbufs 812 * and return tx buffers to the free list. Finally 813 * restart output. Note the microcode has only one 814 * txdone q wired into it so we must use the NPE ID 815 * returned with each npehwbuf to decide where to 816 * send buffers. 817 */ 818 static void 819 npe_txdone(int qid, void *arg) 820 { 821 #define P2V(a, dma) \ 822 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 823 struct npe_softc *sc; 824 struct npebuf *npe; 825 struct txdone *td, q[NPE_MAX]; 826 uint32_t entry; 827 828 /* XXX no NPE-A support */ 829 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 830 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 831 /* XXX max # at a time? */ 832 while (ixpqmgr_qread(qid, &entry) == 0) { 833 sc = npes[NPE_QM_Q_NPE(entry)]; 834 DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 835 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 836 rnd_add_uint32(&sc->rnd_source, entry); 837 838 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 839 m_freem(npe->ix_m); 840 npe->ix_m = NULL; 841 842 td = &q[NPE_QM_Q_NPE(entry)]; 843 *td->tail = npe; 844 td->tail = &npe->ix_next; 845 td->count++; 846 } 847 848 if (q[NPE_B].count) 849 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 850 if (q[NPE_C].count) 851 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 852 #undef P2V 853 } 854 855 static __inline struct mbuf * 856 npe_getcl(void) 857 { 858 struct mbuf *m; 859 860 MGETHDR(m, M_DONTWAIT, MT_DATA); 861 if (m != NULL) { 862 MCLGET(m, M_DONTWAIT); 863 if ((m->m_flags & M_EXT) == 0) { 864 m_freem(m); 865 m = NULL; 866 } 867 } 868 return m; 869 } 870 871 static int 872 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 873 { 874 struct npehwbuf *hw; 875 int error; 876 877 if (m == NULL) { 878 m = npe_getcl(); 879 if (m == NULL) 880 return ENOBUFS; 881 } 882 KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 883 m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 884 /* backload payload and align ip hdr */ 885 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 886 - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 887 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 888 BUS_DMA_READ | BUS_DMA_NOWAIT); 889 if (error != 0) { 890 m_freem(m); 891 return error; 892 } 893 hw = npe->ix_hw; 894 hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 895 /* NB: NPE requires length be a multiple of 64 */ 896 /* NB: buffer length is shifted in word */ 897 hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 898 hw->ix_ne[0].next = 0; 899 npe->ix_m = m; 900 /* Flush the memory in the mbuf */ 901 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 902 BUS_DMASYNC_PREREAD); 903 return 0; 904 } 905 906 /* 907 * RX q processing for a specific NPE. Claim entries 908 * from the hardware queue and pass the frames up the 909 * stack. Pass the rx buffers to the free list. 910 */ 911 static void 912 npe_rxdone(int qid, void *arg) 913 { 914 #define P2V(a, dma) \ 915 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 916 struct npe_softc *sc = arg; 917 struct npedma *dma = &sc->rxdma; 918 uint32_t entry; 919 920 while (ixpqmgr_qread(qid, &entry) == 0) { 921 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 922 struct mbuf *m; 923 924 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 925 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 926 rnd_add_uint32(&sc->rnd_source, entry); 927 /* 928 * Allocate a new mbuf to replenish the rx buffer. 929 * If doing so fails we drop the rx'd frame so we 930 * can reuse the previous mbuf. When we're able to 931 * allocate a new mbuf dispatch the mbuf w/ rx'd 932 * data up the stack and replace it with the newly 933 * allocated one. 934 */ 935 m = npe_getcl(); 936 if (m != NULL) { 937 struct mbuf *mrx = npe->ix_m; 938 struct npehwbuf *hw = npe->ix_hw; 939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 940 941 /* Flush mbuf memory for rx'd data */ 942 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 943 npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 944 945 /* XXX flush hw buffer; works now 'cuz coherent */ 946 /* set m_len etc. per rx frame size */ 947 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 948 mrx->m_pkthdr.len = mrx->m_len; 949 m_set_rcvif(mrx, ifp); 950 /* Don't add M_HASFCS. See below */ 951 952 #if 1 953 if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 954 log(LOG_INFO, "%s: too short frame (len=%d)\n", 955 device_xname(sc->sc_dev), 956 mrx->m_pkthdr.len); 957 /* Back out "newly allocated" mbuf. */ 958 m_freem(m); 959 if_statinc(ifp, if_ierrors); 960 goto fail; 961 } 962 if ((ifp->if_flags & IFF_PROMISC) == 0) { 963 struct ether_header *eh; 964 965 /* 966 * Workaround for "Non-Intel XScale Technology 967 * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 968 * matches the filter (both unicast and 969 * multicast). 970 */ 971 eh = mtod(mrx, struct ether_header *); 972 if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 973 /* Unicast */ 974 975 if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 976 /* Discard it */ 977 #if 0 978 printf("discard it\n"); 979 #endif 980 /* 981 * Back out "newly allocated" 982 * mbuf. 983 */ 984 m_freem(m); 985 goto fail; 986 } 987 } else if (memcmp(eh->ether_dhost, 988 etherbroadcastaddr, 6) == 0) { 989 /* Always accept broadcast packet*/ 990 } else { 991 struct ethercom *ec = &sc->sc_ethercom; 992 struct ether_multi *enm; 993 struct ether_multistep step; 994 int match = 0; 995 996 /* Multicast */ 997 998 ETHER_LOCK(ec); 999 ETHER_FIRST_MULTI(step, ec, enm); 1000 while (enm != NULL) { 1001 uint64_t lowint, highint, dest; 1002 1003 lowint = MAC2UINT64(enm->enm_addrlo); 1004 highint = MAC2UINT64(enm->enm_addrhi); 1005 dest = MAC2UINT64(eh->ether_dhost); 1006 #if 0 1007 printf("%llx\n", lowint); 1008 printf("%llx\n", dest); 1009 printf("%llx\n", highint); 1010 #endif 1011 if ((lowint <= dest) && (dest <= highint)) { 1012 match = 1; 1013 break; 1014 } 1015 ETHER_NEXT_MULTI(step, enm); 1016 } 1017 ETHER_UNLOCK(ec); 1018 1019 if (match == 0) { 1020 /* Discard it */ 1021 #if 0 1022 printf("discard it(M)\n"); 1023 #endif 1024 /* 1025 * Back out "newly allocated" 1026 * mbuf. 1027 */ 1028 m_freem(m); 1029 goto fail; 1030 } 1031 } 1032 } 1033 if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 1034 log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1035 device_xname(sc->sc_dev), mrx->m_pkthdr.len); 1036 /* Back out "newly allocated" mbuf. */ 1037 m_freem(m); 1038 if_statinc(ifp, if_ierrors); 1039 goto fail; 1040 } 1041 #endif 1042 1043 /* 1044 * Trim FCS! 1045 * NPE always adds the FCS by this driver's setting, 1046 * so we always trim it here and not add M_HASFCS. 1047 */ 1048 m_adj(mrx, -ETHER_CRC_LEN); 1049 1050 /* 1051 * Tap off here if there is a bpf listener. 1052 */ 1053 1054 if_percpuq_enqueue(ifp->if_percpuq, mrx); 1055 } else { 1056 fail: 1057 /* discard frame and re-use mbuf */ 1058 m = npe->ix_m; 1059 } 1060 if (npe_rxbuf_init(sc, npe, m) == 0) { 1061 /* return npe buf to rx free list */ 1062 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1063 } else { 1064 /* XXX should not happen */ 1065 } 1066 } 1067 #undef P2V 1068 } 1069 1070 static void 1071 npe_startxmit(struct npe_softc *sc) 1072 { 1073 struct npedma *dma = &sc->txdma; 1074 int i; 1075 1076 sc->tx_free = NULL; 1077 for (i = 0; i < dma->nbuf; i++) { 1078 struct npebuf *npe = &dma->buf[i]; 1079 if (npe->ix_m != NULL) { 1080 /* NB: should not happen */ 1081 printf("%s: %s: free mbuf at entry %u\n", 1082 device_xname(sc->sc_dev), __func__, i); 1083 m_freem(npe->ix_m); 1084 } 1085 npe->ix_m = NULL; 1086 npe->ix_next = sc->tx_free; 1087 sc->tx_free = npe; 1088 } 1089 } 1090 1091 static void 1092 npe_startrecv(struct npe_softc *sc) 1093 { 1094 struct npedma *dma = &sc->rxdma; 1095 struct npebuf *npe; 1096 int i; 1097 1098 for (i = 0; i < dma->nbuf; i++) { 1099 npe = &dma->buf[i]; 1100 npe_rxbuf_init(sc, npe, npe->ix_m); 1101 /* Set npe buf on rx free list */ 1102 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1103 } 1104 } 1105 1106 static void 1107 npeinit_macreg(struct npe_softc *sc) 1108 { 1109 1110 /* 1111 * Reset MAC core. 1112 */ 1113 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1114 DELAY(NPE_MAC_RESET_DELAY); 1115 /* Configure MAC to generate MDC clock */ 1116 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1117 1118 /* Disable transmitter and receiver in the MAC */ 1119 WR4(sc, NPE_MAC_RX_CNTRL1, 1120 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1121 WR4(sc, NPE_MAC_TX_CNTRL1, 1122 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1123 1124 /* 1125 * Set the MAC core registers. 1126 */ 1127 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1128 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1129 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1130 /* Thresholds determined by NPE firmware FS */ 1131 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1132 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1133 WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1134 /* tx fifo threshold (bytes) */ 1135 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1136 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1137 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1138 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1139 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1140 /* assumes MII mode */ 1141 WR4(sc, NPE_MAC_TX_CNTRL1, 1142 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1143 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1144 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1145 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1146 /* XXX pad strip? */ 1147 WR4(sc, NPE_MAC_RX_CNTRL1, 1148 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1149 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1150 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1151 } 1152 1153 static void 1154 npeinit_resetcb(void *xsc) 1155 { 1156 struct npe_softc *sc = xsc; 1157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1158 uint32_t msg[2]; 1159 1160 if_statinc(ifp, if_oerrors); 1161 npeinit_locked(sc); 1162 1163 msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1164 | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1165 msg[1] = 0; 1166 ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1167 } 1168 1169 /* 1170 * Reset and initialize the chip 1171 */ 1172 static void 1173 npeinit_locked(void *xsc) 1174 { 1175 struct npe_softc *sc = xsc; 1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1177 1178 /* Cancel any pending I/O. */ 1179 npestop(ifp, 0); 1180 1181 /* Reset the chip to a known state. */ 1182 npeinit_macreg(sc); 1183 npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1184 ether_mediachange(ifp); 1185 npe_setmcast(sc); 1186 1187 npe_startxmit(sc); 1188 npe_startrecv(sc); 1189 1190 ifp->if_flags |= IFF_RUNNING; 1191 ifp->if_flags &= ~IFF_OACTIVE; 1192 ifp->if_timer = 0; /* just in case */ 1193 1194 /* Enable transmitter and receiver in the MAC */ 1195 WR4(sc, NPE_MAC_RX_CNTRL1, 1196 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1197 WR4(sc, NPE_MAC_TX_CNTRL1, 1198 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1199 1200 callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1201 } 1202 1203 static int 1204 npeinit(struct ifnet *ifp) 1205 { 1206 struct npe_softc *sc = ifp->if_softc; 1207 int s; 1208 1209 s = splnet(); 1210 npeinit_locked(sc); 1211 splx(s); 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * Defragment an mbuf chain, returning at most maxfrags separate 1218 * mbufs+clusters. If this is not possible NULL is returned and 1219 * the original mbuf chain is left in its present (potentially 1220 * modified) state. We use two techniques: collapsing consecutive 1221 * mbufs and replacing consecutive mbufs by a cluster. 1222 */ 1223 static __inline struct mbuf * 1224 npe_defrag(struct mbuf *m0) 1225 { 1226 struct mbuf *m; 1227 1228 MGETHDR(m, M_DONTWAIT, MT_DATA); 1229 if (m == NULL) 1230 return NULL; 1231 m_copy_pkthdr(m, m0); 1232 1233 if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1234 MCLGET(m, M_DONTWAIT); 1235 if ((m->m_flags & M_EXT) == 0) { 1236 m_freem(m); 1237 return NULL; 1238 } 1239 } 1240 1241 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1242 m_freem(m0); 1243 1244 return m; 1245 } 1246 1247 /* 1248 * Dequeue packets and place on the h/w transmit queue. 1249 */ 1250 static void 1251 npestart(struct ifnet *ifp) 1252 { 1253 struct npe_softc *sc = ifp->if_softc; 1254 struct npebuf *npe; 1255 struct npehwbuf *hw; 1256 struct mbuf *m, *n; 1257 bus_dma_segment_t *segs; 1258 int nseg, len, error, i; 1259 uint32_t next; 1260 1261 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1262 return; 1263 1264 while (sc->tx_free != NULL) { 1265 IFQ_DEQUEUE(&ifp->if_snd, m); 1266 if (m == NULL) 1267 break; 1268 npe = sc->tx_free; 1269 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1270 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1271 if (error == EFBIG) { 1272 n = npe_defrag(m); 1273 if (n == NULL) { 1274 printf("%s: %s: too many fragments\n", 1275 device_xname(sc->sc_dev), __func__); 1276 m_freem(m); 1277 return; /* XXX? */ 1278 } 1279 m = n; 1280 error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1281 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1282 } 1283 if (error != 0) { 1284 printf("%s: %s: error %u\n", 1285 device_xname(sc->sc_dev), __func__, error); 1286 m_freem(m); 1287 return; /* XXX? */ 1288 } 1289 sc->tx_free = npe->ix_next; 1290 1291 /* 1292 * Tap off here if there is a bpf listener. 1293 */ 1294 bpf_mtap(ifp, m, BPF_D_OUT); 1295 1296 bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1297 npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1298 1299 npe->ix_m = m; 1300 hw = npe->ix_hw; 1301 len = m->m_pkthdr.len; 1302 nseg = npe->ix_map->dm_nsegs; 1303 segs = npe->ix_map->dm_segs; 1304 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1305 for (i = 0; i < nseg; i++) { 1306 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1307 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1308 hw->ix_ne[i].next = htobe32(next); 1309 1310 len = 0; /* zero for segments > 1 */ 1311 next += sizeof(hw->ix_ne[0]); 1312 } 1313 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1314 /* XXX flush descriptor instead of using uncached memory */ 1315 1316 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1317 __func__, sc->tx_qid, npe->ix_neaddr, 1318 hw->ix_ne[0].data, hw->ix_ne[0].len); 1319 /* stick it on the tx q */ 1320 /* XXX add vlan priority */ 1321 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1322 1323 ifp->if_timer = 5; 1324 } 1325 if (sc->tx_free == NULL) 1326 ifp->if_flags |= IFF_OACTIVE; 1327 } 1328 1329 static void 1330 npe_stopxmit(struct npe_softc *sc) 1331 { 1332 struct npedma *dma = &sc->txdma; 1333 int i; 1334 1335 /* XXX qmgr */ 1336 for (i = 0; i < dma->nbuf; i++) { 1337 struct npebuf *npe = &dma->buf[i]; 1338 1339 if (npe->ix_m != NULL) { 1340 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1341 m_freem(npe->ix_m); 1342 npe->ix_m = NULL; 1343 } 1344 } 1345 } 1346 1347 static void 1348 npe_stoprecv(struct npe_softc *sc) 1349 { 1350 struct npedma *dma = &sc->rxdma; 1351 int i; 1352 1353 /* XXX qmgr */ 1354 for (i = 0; i < dma->nbuf; i++) { 1355 struct npebuf *npe = &dma->buf[i]; 1356 1357 if (npe->ix_m != NULL) { 1358 bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1359 m_freem(npe->ix_m); 1360 npe->ix_m = NULL; 1361 } 1362 } 1363 } 1364 1365 /* 1366 * Turn off interrupts, and stop the nic. 1367 */ 1368 void 1369 npestop(struct ifnet *ifp, int disable) 1370 { 1371 struct npe_softc *sc = ifp->if_softc; 1372 1373 /* Disable transmitter and receiver in the MAC */ 1374 WR4(sc, NPE_MAC_RX_CNTRL1, 1375 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1376 WR4(sc, NPE_MAC_TX_CNTRL1, 1377 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1378 1379 callout_stop(&sc->sc_tick_ch); 1380 1381 npe_stopxmit(sc); 1382 npe_stoprecv(sc); 1383 /* XXX go into loopback & drain q's? */ 1384 /* XXX but beware of disabling tx above */ 1385 1386 /* 1387 * The MAC core rx/tx disable may leave the MAC hardware in an 1388 * unpredictable state. A hw reset is executed before resetting 1389 * all the MAC parameters to a known value. 1390 */ 1391 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1392 DELAY(NPE_MAC_RESET_DELAY); 1393 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1394 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1395 1396 ifp->if_timer = 0; 1397 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1398 } 1399 1400 void 1401 npewatchdog(struct ifnet *ifp) 1402 { 1403 struct npe_softc *sc = ifp->if_softc; 1404 int s; 1405 1406 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1407 s = splnet(); 1408 if_statinc(ifp, if_oerrors); 1409 npeinit_locked(sc); 1410 splx(s); 1411 } 1412 1413 static int 1414 npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1415 { 1416 struct npe_softc *sc = ifp->if_softc; 1417 struct ifreq *ifr = (struct ifreq *) data; 1418 int s, error = 0; 1419 1420 s = splnet(); 1421 1422 switch (cmd) { 1423 case SIOCSIFMEDIA: 1424 #if 0 /* not yet */ 1425 /* Flow control requires full-duplex mode. */ 1426 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1427 (ifr->ifr_media & IFM_FDX) == 0) 1428 ifr->ifr_media &= ~IFM_ETH_FMASK; 1429 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1430 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1431 /* We can do both TXPAUSE and RXPAUSE. */ 1432 ifr->ifr_media |= 1433 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1434 } 1435 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1436 } 1437 #endif 1438 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1439 break; 1440 case SIOCSIFFLAGS: 1441 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) { 1442 /* 1443 * If interface is marked down and it is running, 1444 * then stop and disable it. 1445 */ 1446 (*ifp->if_stop)(ifp, 1); 1447 } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) { 1448 /* 1449 * If interface is marked up and it is stopped, then 1450 * start it. 1451 */ 1452 error = (*ifp->if_init)(ifp); 1453 } else if ((ifp->if_flags & IFF_UP) != 0) { 1454 u_short diff; 1455 1456 /* Up (AND RUNNING). */ 1457 1458 diff = (ifp->if_flags ^ sc->sc_if_flags) 1459 & (IFF_PROMISC | IFF_ALLMULTI); 1460 if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1461 /* 1462 * If the difference bettween last flag and 1463 * new flag only IFF_PROMISC or IFF_ALLMULTI, 1464 * set multicast filter only (don't reset to 1465 * prevent link down). 1466 */ 1467 npe_setmcast(sc); 1468 } else { 1469 /* 1470 * Reset the interface to pick up changes in 1471 * any other flags that affect the hardware 1472 * state. 1473 */ 1474 error = (*ifp->if_init)(ifp); 1475 } 1476 } 1477 sc->sc_if_flags = ifp->if_flags; 1478 break; 1479 default: 1480 error = ether_ioctl(ifp, cmd, data); 1481 if (error == ENETRESET) { 1482 /* 1483 * Multicast list has changed; set the hardware filter 1484 * accordingly. 1485 */ 1486 npe_setmcast(sc); 1487 error = 0; 1488 } 1489 } 1490 1491 npestart(ifp); 1492 1493 splx(s); 1494 return error; 1495 } 1496 1497 /* 1498 * Setup a traffic class -> rx queue mapping. 1499 */ 1500 static int 1501 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1502 { 1503 int npeid = npeconfig[sc->sc_unit].npeid; 1504 uint32_t msg[2]; 1505 1506 msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1507 | classix; 1508 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1509 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1510 } 1511 1512 /* 1513 * Update and reset the statistics in the NPE. 1514 */ 1515 static int 1516 npe_updatestats(struct npe_softc *sc) 1517 { 1518 uint32_t msg[2]; 1519 1520 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1521 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1522 return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1523 } 1524 1525 #if 0 1526 /* 1527 * Get the current statistics block. 1528 */ 1529 static int 1530 npe_getstats(struct npe_softc *sc) 1531 { 1532 uint32_t msg[2]; 1533 1534 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1535 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1536 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1537 } 1538 1539 /* 1540 * Query the image id of the loaded firmware. 1541 */ 1542 static uint32_t 1543 npe_getimageid(struct npe_softc *sc) 1544 { 1545 uint32_t msg[2]; 1546 1547 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1548 msg[1] = 0; 1549 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1550 } 1551 1552 /* 1553 * Enable/disable loopback. 1554 */ 1555 static int 1556 npe_setloopback(struct npe_softc *sc, int ena) 1557 { 1558 uint32_t msg[2]; 1559 1560 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1561 msg[1] = 0; 1562 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1563 } 1564 #endif 1565 1566 /* 1567 * MII bus support routines. 1568 * 1569 * NB: ixp425 has one PHY per NPE 1570 */ 1571 static uint32_t 1572 npe_mii_mdio_read(struct npe_softc *sc, int reg) 1573 { 1574 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1575 uint32_t v; 1576 1577 /* NB: registers are known to be sequential */ 1578 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1579 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1580 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1581 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1582 return v; 1583 #undef MII_RD4 1584 } 1585 1586 static void 1587 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1588 { 1589 #define MII_WR4(sc, reg, v) \ 1590 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1591 1592 /* NB: registers are known to be sequential */ 1593 MII_WR4(sc, reg+0, cmd & 0xff); 1594 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1595 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1596 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1597 #undef MII_WR4 1598 } 1599 1600 static int 1601 npe_mii_mdio_wait(struct npe_softc *sc) 1602 { 1603 #define MAXTRIES 100 /* XXX */ 1604 uint32_t v; 1605 int i; 1606 1607 for (i = 0; i < MAXTRIES; i++) { 1608 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1609 if ((v & NPE_MII_GO) == 0) 1610 return 0; 1611 } 1612 return ETIMEDOUT; 1613 #undef MAXTRIES 1614 } 1615 1616 static int 1617 npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val) 1618 { 1619 struct npe_softc *sc = device_private(self); 1620 uint32_t v; 1621 1622 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1623 return -1; 1624 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1625 | NPE_MII_GO; 1626 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1627 if (npe_mii_mdio_wait(sc) == 0) 1628 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1629 else 1630 v = 0xffff | NPE_MII_READ_FAIL; 1631 1632 if ((v & NPE_MII_READ_FAIL) != 0) 1633 return -1; 1634 1635 *val = v & 0xffff; 1636 return 0; 1637 #undef MAXTRIES 1638 } 1639 1640 static int 1641 npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val) 1642 { 1643 struct npe_softc *sc = device_private(self); 1644 uint32_t v; 1645 1646 if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1647 return -1; 1648 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1649 | val | NPE_MII_WRITE 1650 | NPE_MII_GO; 1651 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1652 1653 return npe_mii_mdio_wait(sc); 1654 } 1655 1656 static void 1657 npe_miibus_statchg(struct ifnet *ifp) 1658 { 1659 struct npe_softc *sc = ifp->if_softc; 1660 uint32_t tx1, rx1; 1661 uint32_t randoff; 1662 1663 /* Sync MAC duplex state */ 1664 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1665 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1666 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1667 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1668 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1669 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1670 } else { 1671 struct timeval now; 1672 getmicrotime(&now); 1673 randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1674 & 0x7f; 1675 WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1676 + randoff); 1677 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1678 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1679 } 1680 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1681 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1682 } 1683
Indexes created Thu Oct 02 10:09:58 GMT 2025